cyapa.h 14 KB

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  1. /*
  2. * Cypress APA trackpad with I2C interface
  3. *
  4. * Author: Dudley Du <dudl@cypress.com>
  5. *
  6. * Copyright (C) 2014-2015 Cypress Semiconductor, Inc.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file COPYING in the main directory of this archive for
  10. * more details.
  11. */
  12. #ifndef _CYAPA_H
  13. #define _CYAPA_H
  14. #include <linux/firmware.h>
  15. /* APA trackpad firmware generation number. */
  16. #define CYAPA_GEN_UNKNOWN 0x00 /* unknown protocol. */
  17. #define CYAPA_GEN3 0x03 /* support MT-protocol B with tracking ID. */
  18. #define CYAPA_GEN5 0x05 /* support TrueTouch GEN5 trackpad device. */
  19. #define CYAPA_GEN6 0x06 /* support TrueTouch GEN6 trackpad device. */
  20. #define CYAPA_NAME "Cypress APA Trackpad (cyapa)"
  21. /*
  22. * Macros for SMBus communication
  23. */
  24. #define SMBUS_READ 0x01
  25. #define SMBUS_WRITE 0x00
  26. #define SMBUS_ENCODE_IDX(cmd, idx) ((cmd) | (((idx) & 0x03) << 1))
  27. #define SMBUS_ENCODE_RW(cmd, rw) ((cmd) | ((rw) & 0x01))
  28. #define SMBUS_BYTE_BLOCK_CMD_MASK 0x80
  29. #define SMBUS_GROUP_BLOCK_CMD_MASK 0x40
  30. /* Commands for read/write registers of Cypress trackpad */
  31. #define CYAPA_CMD_SOFT_RESET 0x00
  32. #define CYAPA_CMD_POWER_MODE 0x01
  33. #define CYAPA_CMD_DEV_STATUS 0x02
  34. #define CYAPA_CMD_GROUP_DATA 0x03
  35. #define CYAPA_CMD_GROUP_CMD 0x04
  36. #define CYAPA_CMD_GROUP_QUERY 0x05
  37. #define CYAPA_CMD_BL_STATUS 0x06
  38. #define CYAPA_CMD_BL_HEAD 0x07
  39. #define CYAPA_CMD_BL_CMD 0x08
  40. #define CYAPA_CMD_BL_DATA 0x09
  41. #define CYAPA_CMD_BL_ALL 0x0a
  42. #define CYAPA_CMD_BLK_PRODUCT_ID 0x0b
  43. #define CYAPA_CMD_BLK_HEAD 0x0c
  44. #define CYAPA_CMD_MAX_BASELINE 0x0d
  45. #define CYAPA_CMD_MIN_BASELINE 0x0e
  46. #define BL_HEAD_OFFSET 0x00
  47. #define BL_DATA_OFFSET 0x10
  48. #define BL_STATUS_SIZE 3 /* Length of gen3 bootloader status registers */
  49. #define CYAPA_REG_MAP_SIZE 256
  50. /*
  51. * Gen3 Operational Device Status Register
  52. *
  53. * bit 7: Valid interrupt source
  54. * bit 6 - 4: Reserved
  55. * bit 3 - 2: Power status
  56. * bit 1 - 0: Device status
  57. */
  58. #define REG_OP_STATUS 0x00
  59. #define OP_STATUS_SRC 0x80
  60. #define OP_STATUS_POWER 0x0c
  61. #define OP_STATUS_DEV 0x03
  62. #define OP_STATUS_MASK (OP_STATUS_SRC | OP_STATUS_POWER | OP_STATUS_DEV)
  63. /*
  64. * Operational Finger Count/Button Flags Register
  65. *
  66. * bit 7 - 4: Number of touched finger
  67. * bit 3: Valid data
  68. * bit 2: Middle Physical Button
  69. * bit 1: Right Physical Button
  70. * bit 0: Left physical Button
  71. */
  72. #define REG_OP_DATA1 0x01
  73. #define OP_DATA_VALID 0x08
  74. #define OP_DATA_MIDDLE_BTN 0x04
  75. #define OP_DATA_RIGHT_BTN 0x02
  76. #define OP_DATA_LEFT_BTN 0x01
  77. #define OP_DATA_BTN_MASK (OP_DATA_MIDDLE_BTN | OP_DATA_RIGHT_BTN | \
  78. OP_DATA_LEFT_BTN)
  79. /*
  80. * Write-only command file register used to issue commands and
  81. * parameters to the bootloader.
  82. * The default value read from it is always 0x00.
  83. */
  84. #define REG_BL_FILE 0x00
  85. #define BL_FILE 0x00
  86. /*
  87. * Bootloader Status Register
  88. *
  89. * bit 7: Busy
  90. * bit 6 - 5: Reserved
  91. * bit 4: Bootloader running
  92. * bit 3 - 2: Reserved
  93. * bit 1: Watchdog Reset
  94. * bit 0: Checksum valid
  95. */
  96. #define REG_BL_STATUS 0x01
  97. #define BL_STATUS_REV_6_5 0x60
  98. #define BL_STATUS_BUSY 0x80
  99. #define BL_STATUS_RUNNING 0x10
  100. #define BL_STATUS_REV_3_2 0x0c
  101. #define BL_STATUS_WATCHDOG 0x02
  102. #define BL_STATUS_CSUM_VALID 0x01
  103. #define BL_STATUS_REV_MASK (BL_STATUS_WATCHDOG | BL_STATUS_REV_3_2 | \
  104. BL_STATUS_REV_6_5)
  105. /*
  106. * Bootloader Error Register
  107. *
  108. * bit 7: Invalid
  109. * bit 6: Invalid security key
  110. * bit 5: Bootloading
  111. * bit 4: Command checksum
  112. * bit 3: Flash protection error
  113. * bit 2: Flash checksum error
  114. * bit 1 - 0: Reserved
  115. */
  116. #define REG_BL_ERROR 0x02
  117. #define BL_ERROR_INVALID 0x80
  118. #define BL_ERROR_INVALID_KEY 0x40
  119. #define BL_ERROR_BOOTLOADING 0x20
  120. #define BL_ERROR_CMD_CSUM 0x10
  121. #define BL_ERROR_FLASH_PROT 0x08
  122. #define BL_ERROR_FLASH_CSUM 0x04
  123. #define BL_ERROR_RESERVED 0x03
  124. #define BL_ERROR_NO_ERR_IDLE 0x00
  125. #define BL_ERROR_NO_ERR_ACTIVE (BL_ERROR_BOOTLOADING)
  126. #define CAPABILITY_BTN_SHIFT 3
  127. #define CAPABILITY_LEFT_BTN_MASK (0x01 << 3)
  128. #define CAPABILITY_RIGHT_BTN_MASK (0x01 << 4)
  129. #define CAPABILITY_MIDDLE_BTN_MASK (0x01 << 5)
  130. #define CAPABILITY_BTN_MASK (CAPABILITY_LEFT_BTN_MASK | \
  131. CAPABILITY_RIGHT_BTN_MASK | \
  132. CAPABILITY_MIDDLE_BTN_MASK)
  133. #define PWR_MODE_MASK 0xfc
  134. #define PWR_MODE_FULL_ACTIVE (0x3f << 2)
  135. #define PWR_MODE_IDLE (0x03 << 2) /* Default rt suspend scanrate: 30ms */
  136. #define PWR_MODE_SLEEP (0x05 << 2) /* Default suspend scanrate: 50ms */
  137. #define PWR_MODE_BTN_ONLY (0x01 << 2)
  138. #define PWR_MODE_OFF (0x00 << 2)
  139. #define PWR_STATUS_MASK 0x0c
  140. #define PWR_STATUS_ACTIVE (0x03 << 2)
  141. #define PWR_STATUS_IDLE (0x02 << 2)
  142. #define PWR_STATUS_BTN_ONLY (0x01 << 2)
  143. #define PWR_STATUS_OFF (0x00 << 2)
  144. #define AUTOSUSPEND_DELAY 2000 /* unit : ms */
  145. #define BTN_ONLY_MODE_NAME "buttononly"
  146. #define OFF_MODE_NAME "off"
  147. /* Common macros for PIP interface. */
  148. #define PIP_HID_DESCRIPTOR_ADDR 0x0001
  149. #define PIP_REPORT_DESCRIPTOR_ADDR 0x0002
  150. #define PIP_INPUT_REPORT_ADDR 0x0003
  151. #define PIP_OUTPUT_REPORT_ADDR 0x0004
  152. #define PIP_CMD_DATA_ADDR 0x0006
  153. #define PIP_RETRIEVE_DATA_STRUCTURE 0x24
  154. #define PIP_CMD_CALIBRATE 0x28
  155. #define PIP_BL_CMD_VERIFY_APP_INTEGRITY 0x31
  156. #define PIP_BL_CMD_GET_BL_INFO 0x38
  157. #define PIP_BL_CMD_PROGRAM_VERIFY_ROW 0x39
  158. #define PIP_BL_CMD_LAUNCH_APP 0x3b
  159. #define PIP_BL_CMD_INITIATE_BL 0x48
  160. #define PIP_INVALID_CMD 0xff
  161. #define PIP_HID_DESCRIPTOR_SIZE 32
  162. #define PIP_HID_APP_REPORT_ID 0xf7
  163. #define PIP_HID_BL_REPORT_ID 0xff
  164. #define PIP_BL_CMD_REPORT_ID 0x40
  165. #define PIP_BL_RESP_REPORT_ID 0x30
  166. #define PIP_APP_CMD_REPORT_ID 0x2f
  167. #define PIP_APP_RESP_REPORT_ID 0x1f
  168. #define PIP_READ_SYS_INFO_CMD_LENGTH 7
  169. #define PIP_BL_READ_APP_INFO_CMD_LENGTH 13
  170. #define PIP_MIN_BL_CMD_LENGTH 13
  171. #define PIP_MIN_BL_RESP_LENGTH 11
  172. #define PIP_MIN_APP_CMD_LENGTH 7
  173. #define PIP_MIN_APP_RESP_LENGTH 5
  174. #define PIP_UNSUPPORTED_CMD_RESP_LENGTH 6
  175. #define PIP_READ_SYS_INFO_RESP_LENGTH 71
  176. #define PIP_BL_APP_INFO_RESP_LENGTH 30
  177. #define PIP_BL_GET_INFO_RESP_LENGTH 19
  178. #define PIP_BL_PLATFORM_VER_SHIFT 4
  179. #define PIP_BL_PLATFORM_VER_MASK 0x0f
  180. #define PIP_PRODUCT_FAMILY_MASK 0xf000
  181. #define PIP_PRODUCT_FAMILY_TRACKPAD 0x1000
  182. #define PIP_DEEP_SLEEP_STATE_ON 0x00
  183. #define PIP_DEEP_SLEEP_STATE_OFF 0x01
  184. #define PIP_DEEP_SLEEP_STATE_MASK 0x03
  185. #define PIP_APP_DEEP_SLEEP_REPORT_ID 0xf0
  186. #define PIP_DEEP_SLEEP_RESP_LENGTH 5
  187. #define PIP_DEEP_SLEEP_OPCODE 0x08
  188. #define PIP_DEEP_SLEEP_OPCODE_MASK 0x0f
  189. #define PIP_RESP_LENGTH_OFFSET 0
  190. #define PIP_RESP_LENGTH_SIZE 2
  191. #define PIP_RESP_REPORT_ID_OFFSET 2
  192. #define PIP_RESP_RSVD_OFFSET 3
  193. #define PIP_RESP_RSVD_KEY 0x00
  194. #define PIP_RESP_BL_SOP_OFFSET 4
  195. #define PIP_SOP_KEY 0x01 /* Start of Packet */
  196. #define PIP_EOP_KEY 0x17 /* End of Packet */
  197. #define PIP_RESP_APP_CMD_OFFSET 4
  198. #define GET_PIP_CMD_CODE(reg) ((reg) & 0x7f)
  199. #define PIP_RESP_STATUS_OFFSET 5
  200. #define VALID_CMD_RESP_HEADER(resp, cmd) \
  201. (((resp)[PIP_RESP_REPORT_ID_OFFSET] == PIP_APP_RESP_REPORT_ID) && \
  202. ((resp)[PIP_RESP_RSVD_OFFSET] == PIP_RESP_RSVD_KEY) && \
  203. (GET_PIP_CMD_CODE((resp)[PIP_RESP_APP_CMD_OFFSET]) == (cmd)))
  204. #define PIP_CMD_COMPLETE_SUCCESS(resp_data) \
  205. ((resp_data)[PIP_RESP_STATUS_OFFSET] == 0x00)
  206. /* Variables to record latest gen5 trackpad power states. */
  207. #define UNINIT_SLEEP_TIME 0xffff
  208. #define UNINIT_PWR_MODE 0xff
  209. #define PIP_DEV_SET_PWR_STATE(cyapa, s) ((cyapa)->dev_pwr_mode = (s))
  210. #define PIP_DEV_GET_PWR_STATE(cyapa) ((cyapa)->dev_pwr_mode)
  211. #define PIP_DEV_SET_SLEEP_TIME(cyapa, t) ((cyapa)->dev_sleep_time = (t))
  212. #define PIP_DEV_GET_SLEEP_TIME(cyapa) ((cyapa)->dev_sleep_time)
  213. #define PIP_DEV_UNINIT_SLEEP_TIME(cyapa) \
  214. (((cyapa)->dev_sleep_time) == UNINIT_SLEEP_TIME)
  215. /* The touch.id is used as the MT slot id, thus max MT slot is 15 */
  216. #define CYAPA_MAX_MT_SLOTS 15
  217. struct cyapa;
  218. typedef bool (*cb_sort)(struct cyapa *, u8 *, int);
  219. enum cyapa_pm_stage {
  220. CYAPA_PM_DEACTIVE,
  221. CYAPA_PM_ACTIVE,
  222. CYAPA_PM_SUSPEND,
  223. CYAPA_PM_RESUME,
  224. CYAPA_PM_RUNTIME_SUSPEND,
  225. CYAPA_PM_RUNTIME_RESUME,
  226. };
  227. struct cyapa_dev_ops {
  228. int (*check_fw)(struct cyapa *, const struct firmware *);
  229. int (*bl_enter)(struct cyapa *);
  230. int (*bl_activate)(struct cyapa *);
  231. int (*bl_initiate)(struct cyapa *, const struct firmware *);
  232. int (*update_fw)(struct cyapa *, const struct firmware *);
  233. int (*bl_deactivate)(struct cyapa *);
  234. ssize_t (*show_baseline)(struct device *,
  235. struct device_attribute *, char *);
  236. ssize_t (*calibrate_store)(struct device *,
  237. struct device_attribute *, const char *, size_t);
  238. int (*initialize)(struct cyapa *cyapa);
  239. int (*state_parse)(struct cyapa *cyapa, u8 *reg_status, int len);
  240. int (*operational_check)(struct cyapa *cyapa);
  241. int (*irq_handler)(struct cyapa *);
  242. bool (*irq_cmd_handler)(struct cyapa *);
  243. int (*sort_empty_output_data)(struct cyapa *,
  244. u8 *, int *, cb_sort);
  245. int (*set_power_mode)(struct cyapa *, u8, u16, enum cyapa_pm_stage);
  246. int (*set_proximity)(struct cyapa *, bool);
  247. };
  248. struct cyapa_pip_cmd_states {
  249. struct mutex cmd_lock;
  250. struct completion cmd_ready;
  251. atomic_t cmd_issued;
  252. u8 in_progress_cmd;
  253. bool is_irq_mode;
  254. cb_sort resp_sort_func;
  255. u8 *resp_data;
  256. int *resp_len;
  257. enum cyapa_pm_stage pm_stage;
  258. struct mutex pm_stage_lock;
  259. u8 irq_cmd_buf[CYAPA_REG_MAP_SIZE];
  260. u8 empty_buf[CYAPA_REG_MAP_SIZE];
  261. };
  262. union cyapa_cmd_states {
  263. struct cyapa_pip_cmd_states pip;
  264. };
  265. enum cyapa_state {
  266. CYAPA_STATE_NO_DEVICE,
  267. CYAPA_STATE_BL_BUSY,
  268. CYAPA_STATE_BL_IDLE,
  269. CYAPA_STATE_BL_ACTIVE,
  270. CYAPA_STATE_OP,
  271. CYAPA_STATE_GEN5_BL,
  272. CYAPA_STATE_GEN5_APP,
  273. CYAPA_STATE_GEN6_BL,
  274. CYAPA_STATE_GEN6_APP,
  275. };
  276. struct gen6_interval_setting {
  277. u16 active_interval;
  278. u16 lp1_interval;
  279. u16 lp2_interval;
  280. };
  281. /* The main device structure */
  282. struct cyapa {
  283. enum cyapa_state state;
  284. u8 status[BL_STATUS_SIZE];
  285. bool operational; /* true: ready for data reporting; false: not. */
  286. struct regulator *vcc;
  287. struct i2c_client *client;
  288. struct input_dev *input;
  289. char phys[32]; /* Device physical location */
  290. bool irq_wake; /* Irq wake is enabled */
  291. bool smbus;
  292. /* power mode settings */
  293. u8 suspend_power_mode;
  294. u16 suspend_sleep_time;
  295. u8 runtime_suspend_power_mode;
  296. u16 runtime_suspend_sleep_time;
  297. u8 dev_pwr_mode;
  298. u16 dev_sleep_time;
  299. struct gen6_interval_setting gen6_interval_setting;
  300. /* Read from query data region. */
  301. char product_id[16];
  302. u8 platform_ver; /* Platform version. */
  303. u8 fw_maj_ver; /* Firmware major version. */
  304. u8 fw_min_ver; /* Firmware minor version. */
  305. u8 btn_capability;
  306. u8 gen;
  307. int max_abs_x;
  308. int max_abs_y;
  309. int physical_size_x;
  310. int physical_size_y;
  311. /* Used in ttsp and truetouch based trackpad devices. */
  312. u8 x_origin; /* X Axis Origin: 0 = left side; 1 = right side. */
  313. u8 y_origin; /* Y Axis Origin: 0 = top; 1 = bottom. */
  314. int electrodes_x; /* Number of electrodes on the X Axis*/
  315. int electrodes_y; /* Number of electrodes on the Y Axis*/
  316. int electrodes_rx; /* Number of Rx electrodes */
  317. int aligned_electrodes_rx; /* 4 aligned */
  318. int max_z;
  319. /*
  320. * Used to synchronize the access or update the device state.
  321. * And since update firmware and read firmware image process will take
  322. * quite long time, maybe more than 10 seconds, so use mutex_lock
  323. * to sync and wait other interface and detecting are done or ready.
  324. */
  325. struct mutex state_sync_lock;
  326. const struct cyapa_dev_ops *ops;
  327. union cyapa_cmd_states cmd_states;
  328. };
  329. ssize_t cyapa_i2c_reg_read_block(struct cyapa *cyapa, u8 reg, size_t len,
  330. u8 *values);
  331. ssize_t cyapa_smbus_read_block(struct cyapa *cyapa, u8 cmd, size_t len,
  332. u8 *values);
  333. ssize_t cyapa_read_block(struct cyapa *cyapa, u8 cmd_idx, u8 *values);
  334. int cyapa_poll_state(struct cyapa *cyapa, unsigned int timeout);
  335. u8 cyapa_sleep_time_to_pwr_cmd(u16 sleep_time);
  336. u16 cyapa_pwr_cmd_to_sleep_time(u8 pwr_mode);
  337. ssize_t cyapa_i2c_pip_read(struct cyapa *cyapa, u8 *buf, size_t size);
  338. ssize_t cyapa_i2c_pip_write(struct cyapa *cyapa, u8 *buf, size_t size);
  339. int cyapa_empty_pip_output_data(struct cyapa *cyapa,
  340. u8 *buf, int *len, cb_sort func);
  341. int cyapa_i2c_pip_cmd_irq_sync(struct cyapa *cyapa,
  342. u8 *cmd, int cmd_len,
  343. u8 *resp_data, int *resp_len,
  344. unsigned long timeout,
  345. cb_sort func,
  346. bool irq_mode);
  347. int cyapa_pip_state_parse(struct cyapa *cyapa, u8 *reg_data, int len);
  348. bool cyapa_pip_sort_system_info_data(struct cyapa *cyapa, u8 *buf, int len);
  349. bool cyapa_sort_tsg_pip_bl_resp_data(struct cyapa *cyapa, u8 *data, int len);
  350. int cyapa_pip_deep_sleep(struct cyapa *cyapa, u8 state);
  351. bool cyapa_sort_tsg_pip_app_resp_data(struct cyapa *cyapa, u8 *data, int len);
  352. int cyapa_pip_bl_exit(struct cyapa *cyapa);
  353. int cyapa_pip_bl_enter(struct cyapa *cyapa);
  354. bool cyapa_is_pip_bl_mode(struct cyapa *cyapa);
  355. bool cyapa_is_pip_app_mode(struct cyapa *cyapa);
  356. int cyapa_pip_cmd_state_initialize(struct cyapa *cyapa);
  357. int cyapa_pip_resume_scanning(struct cyapa *cyapa);
  358. int cyapa_pip_suspend_scanning(struct cyapa *cyapa);
  359. int cyapa_pip_check_fw(struct cyapa *cyapa, const struct firmware *fw);
  360. int cyapa_pip_bl_initiate(struct cyapa *cyapa, const struct firmware *fw);
  361. int cyapa_pip_do_fw_update(struct cyapa *cyapa, const struct firmware *fw);
  362. int cyapa_pip_bl_activate(struct cyapa *cyapa);
  363. int cyapa_pip_bl_deactivate(struct cyapa *cyapa);
  364. ssize_t cyapa_pip_do_calibrate(struct device *dev,
  365. struct device_attribute *attr,
  366. const char *buf, size_t count);
  367. int cyapa_pip_set_proximity(struct cyapa *cyapa, bool enable);
  368. bool cyapa_pip_irq_cmd_handler(struct cyapa *cyapa);
  369. int cyapa_pip_irq_handler(struct cyapa *cyapa);
  370. extern u8 pip_read_sys_info[];
  371. extern u8 pip_bl_read_app_info[];
  372. extern const char product_id[];
  373. extern const struct cyapa_dev_ops cyapa_gen3_ops;
  374. extern const struct cyapa_dev_ops cyapa_gen5_ops;
  375. extern const struct cyapa_dev_ops cyapa_gen6_ops;
  376. #endif