tegra-kbc.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
  4. * keyboard controller
  5. *
  6. * Copyright (c) 2009-2011, NVIDIA Corporation.
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/input.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/delay.h>
  13. #include <linux/io.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/clk.h>
  18. #include <linux/slab.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/reset.h>
  21. #include <linux/err.h>
  22. #define KBC_MAX_KPENT 8
  23. /* Maximum row/column supported by Tegra KBC yet is 16x8 */
  24. #define KBC_MAX_GPIO 24
  25. /* Maximum keys supported by Tegra KBC yet is 16 x 8*/
  26. #define KBC_MAX_KEY (16 * 8)
  27. #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
  28. /* KBC row scan time and delay for beginning the row scan. */
  29. #define KBC_ROW_SCAN_TIME 16
  30. #define KBC_ROW_SCAN_DLY 5
  31. /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
  32. #define KBC_CYCLE_MS 32
  33. /* KBC Registers */
  34. /* KBC Control Register */
  35. #define KBC_CONTROL_0 0x0
  36. #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
  37. #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
  38. #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
  39. #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
  40. #define KBC_CONTROL_KBC_EN (1 << 0)
  41. /* KBC Interrupt Register */
  42. #define KBC_INT_0 0x4
  43. #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
  44. #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
  45. #define KBC_ROW_CFG0_0 0x8
  46. #define KBC_COL_CFG0_0 0x18
  47. #define KBC_TO_CNT_0 0x24
  48. #define KBC_INIT_DLY_0 0x28
  49. #define KBC_RPT_DLY_0 0x2c
  50. #define KBC_KP_ENT0_0 0x30
  51. #define KBC_KP_ENT1_0 0x34
  52. #define KBC_ROW0_MASK_0 0x38
  53. #define KBC_ROW_SHIFT 3
  54. enum tegra_pin_type {
  55. PIN_CFG_IGNORE,
  56. PIN_CFG_COL,
  57. PIN_CFG_ROW,
  58. };
  59. /* Tegra KBC hw support */
  60. struct tegra_kbc_hw_support {
  61. int max_rows;
  62. int max_columns;
  63. };
  64. struct tegra_kbc_pin_cfg {
  65. enum tegra_pin_type type;
  66. unsigned char num;
  67. };
  68. struct tegra_kbc {
  69. struct device *dev;
  70. unsigned int debounce_cnt;
  71. unsigned int repeat_cnt;
  72. struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
  73. const struct matrix_keymap_data *keymap_data;
  74. bool wakeup;
  75. void __iomem *mmio;
  76. struct input_dev *idev;
  77. int irq;
  78. spinlock_t lock;
  79. unsigned int repoll_dly;
  80. unsigned long cp_dly_jiffies;
  81. unsigned int cp_to_wkup_dly;
  82. bool use_fn_map;
  83. bool use_ghost_filter;
  84. bool keypress_caused_wake;
  85. unsigned short keycode[KBC_MAX_KEY * 2];
  86. unsigned short current_keys[KBC_MAX_KPENT];
  87. unsigned int num_pressed_keys;
  88. u32 wakeup_key;
  89. struct timer_list timer;
  90. struct clk *clk;
  91. struct reset_control *rst;
  92. const struct tegra_kbc_hw_support *hw_support;
  93. int max_keys;
  94. int num_rows_and_columns;
  95. };
  96. static void tegra_kbc_report_released_keys(struct input_dev *input,
  97. unsigned short old_keycodes[],
  98. unsigned int old_num_keys,
  99. unsigned short new_keycodes[],
  100. unsigned int new_num_keys)
  101. {
  102. unsigned int i, j;
  103. for (i = 0; i < old_num_keys; i++) {
  104. for (j = 0; j < new_num_keys; j++)
  105. if (old_keycodes[i] == new_keycodes[j])
  106. break;
  107. if (j == new_num_keys)
  108. input_report_key(input, old_keycodes[i], 0);
  109. }
  110. }
  111. static void tegra_kbc_report_pressed_keys(struct input_dev *input,
  112. unsigned char scancodes[],
  113. unsigned short keycodes[],
  114. unsigned int num_pressed_keys)
  115. {
  116. unsigned int i;
  117. for (i = 0; i < num_pressed_keys; i++) {
  118. input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
  119. input_report_key(input, keycodes[i], 1);
  120. }
  121. }
  122. static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
  123. {
  124. unsigned char scancodes[KBC_MAX_KPENT];
  125. unsigned short keycodes[KBC_MAX_KPENT];
  126. u32 val = 0;
  127. unsigned int i;
  128. unsigned int num_down = 0;
  129. bool fn_keypress = false;
  130. bool key_in_same_row = false;
  131. bool key_in_same_col = false;
  132. for (i = 0; i < KBC_MAX_KPENT; i++) {
  133. if ((i % 4) == 0)
  134. val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
  135. if (val & 0x80) {
  136. unsigned int col = val & 0x07;
  137. unsigned int row = (val >> 3) & 0x0f;
  138. unsigned char scancode =
  139. MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
  140. scancodes[num_down] = scancode;
  141. keycodes[num_down] = kbc->keycode[scancode];
  142. /* If driver uses Fn map, do not report the Fn key. */
  143. if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
  144. fn_keypress = true;
  145. else
  146. num_down++;
  147. }
  148. val >>= 8;
  149. }
  150. /*
  151. * Matrix keyboard designs are prone to keyboard ghosting.
  152. * Ghosting occurs if there are 3 keys such that -
  153. * any 2 of the 3 keys share a row, and any 2 of them share a column.
  154. * If so ignore the key presses for this iteration.
  155. */
  156. if (kbc->use_ghost_filter && num_down >= 3) {
  157. for (i = 0; i < num_down; i++) {
  158. unsigned int j;
  159. u8 curr_col = scancodes[i] & 0x07;
  160. u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
  161. /*
  162. * Find 2 keys such that one key is in the same row
  163. * and the other is in the same column as the i-th key.
  164. */
  165. for (j = i + 1; j < num_down; j++) {
  166. u8 col = scancodes[j] & 0x07;
  167. u8 row = scancodes[j] >> KBC_ROW_SHIFT;
  168. if (col == curr_col)
  169. key_in_same_col = true;
  170. if (row == curr_row)
  171. key_in_same_row = true;
  172. }
  173. }
  174. }
  175. /*
  176. * If the platform uses Fn keymaps, translate keys on a Fn keypress.
  177. * Function keycodes are max_keys apart from the plain keycodes.
  178. */
  179. if (fn_keypress) {
  180. for (i = 0; i < num_down; i++) {
  181. scancodes[i] += kbc->max_keys;
  182. keycodes[i] = kbc->keycode[scancodes[i]];
  183. }
  184. }
  185. /* Ignore the key presses for this iteration? */
  186. if (key_in_same_col && key_in_same_row)
  187. return;
  188. tegra_kbc_report_released_keys(kbc->idev,
  189. kbc->current_keys, kbc->num_pressed_keys,
  190. keycodes, num_down);
  191. tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
  192. input_sync(kbc->idev);
  193. memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
  194. kbc->num_pressed_keys = num_down;
  195. }
  196. static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable)
  197. {
  198. u32 val;
  199. val = readl(kbc->mmio + KBC_CONTROL_0);
  200. if (enable)
  201. val |= KBC_CONTROL_FIFO_CNT_INT_EN;
  202. else
  203. val &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
  204. writel(val, kbc->mmio + KBC_CONTROL_0);
  205. }
  206. static void tegra_kbc_keypress_timer(struct timer_list *t)
  207. {
  208. struct tegra_kbc *kbc = from_timer(kbc, t, timer);
  209. unsigned long flags;
  210. u32 val;
  211. unsigned int i;
  212. spin_lock_irqsave(&kbc->lock, flags);
  213. val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
  214. if (val) {
  215. unsigned long dly;
  216. tegra_kbc_report_keys(kbc);
  217. /*
  218. * If more than one keys are pressed we need not wait
  219. * for the repoll delay.
  220. */
  221. dly = (val == 1) ? kbc->repoll_dly : 1;
  222. mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
  223. } else {
  224. /* Release any pressed keys and exit the polling loop */
  225. for (i = 0; i < kbc->num_pressed_keys; i++)
  226. input_report_key(kbc->idev, kbc->current_keys[i], 0);
  227. input_sync(kbc->idev);
  228. kbc->num_pressed_keys = 0;
  229. /* All keys are released so enable the keypress interrupt */
  230. tegra_kbc_set_fifo_interrupt(kbc, true);
  231. }
  232. spin_unlock_irqrestore(&kbc->lock, flags);
  233. }
  234. static irqreturn_t tegra_kbc_isr(int irq, void *args)
  235. {
  236. struct tegra_kbc *kbc = args;
  237. unsigned long flags;
  238. u32 val;
  239. spin_lock_irqsave(&kbc->lock, flags);
  240. /*
  241. * Quickly bail out & reenable interrupts if the fifo threshold
  242. * count interrupt wasn't the interrupt source
  243. */
  244. val = readl(kbc->mmio + KBC_INT_0);
  245. writel(val, kbc->mmio + KBC_INT_0);
  246. if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
  247. /*
  248. * Until all keys are released, defer further processing to
  249. * the polling loop in tegra_kbc_keypress_timer.
  250. */
  251. tegra_kbc_set_fifo_interrupt(kbc, false);
  252. mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
  253. } else if (val & KBC_INT_KEYPRESS_INT_STATUS) {
  254. /* We can be here only through system resume path */
  255. kbc->keypress_caused_wake = true;
  256. }
  257. spin_unlock_irqrestore(&kbc->lock, flags);
  258. return IRQ_HANDLED;
  259. }
  260. static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
  261. {
  262. int i;
  263. unsigned int rst_val;
  264. /* Either mask all keys or none. */
  265. rst_val = (filter && !kbc->wakeup) ? ~0 : 0;
  266. for (i = 0; i < kbc->hw_support->max_rows; i++)
  267. writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
  268. }
  269. static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
  270. {
  271. int i;
  272. for (i = 0; i < KBC_MAX_GPIO; i++) {
  273. u32 r_shft = 5 * (i % 6);
  274. u32 c_shft = 4 * (i % 8);
  275. u32 r_mask = 0x1f << r_shft;
  276. u32 c_mask = 0x0f << c_shft;
  277. u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
  278. u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
  279. u32 row_cfg = readl(kbc->mmio + r_offs);
  280. u32 col_cfg = readl(kbc->mmio + c_offs);
  281. row_cfg &= ~r_mask;
  282. col_cfg &= ~c_mask;
  283. switch (kbc->pin_cfg[i].type) {
  284. case PIN_CFG_ROW:
  285. row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft;
  286. break;
  287. case PIN_CFG_COL:
  288. col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft;
  289. break;
  290. case PIN_CFG_IGNORE:
  291. break;
  292. }
  293. writel(row_cfg, kbc->mmio + r_offs);
  294. writel(col_cfg, kbc->mmio + c_offs);
  295. }
  296. }
  297. static int tegra_kbc_start(struct tegra_kbc *kbc)
  298. {
  299. unsigned int debounce_cnt;
  300. u32 val = 0;
  301. int ret;
  302. ret = clk_prepare_enable(kbc->clk);
  303. if (ret)
  304. return ret;
  305. /* Reset the KBC controller to clear all previous status.*/
  306. reset_control_assert(kbc->rst);
  307. udelay(100);
  308. reset_control_deassert(kbc->rst);
  309. udelay(100);
  310. tegra_kbc_config_pins(kbc);
  311. tegra_kbc_setup_wakekeys(kbc, false);
  312. writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
  313. /* Keyboard debounce count is maximum of 12 bits. */
  314. debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
  315. val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
  316. val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
  317. val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
  318. val |= KBC_CONTROL_KBC_EN; /* enable */
  319. writel(val, kbc->mmio + KBC_CONTROL_0);
  320. /*
  321. * Compute the delay(ns) from interrupt mode to continuous polling
  322. * mode so the timer routine is scheduled appropriately.
  323. */
  324. val = readl(kbc->mmio + KBC_INIT_DLY_0);
  325. kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
  326. kbc->num_pressed_keys = 0;
  327. /*
  328. * Atomically clear out any remaining entries in the key FIFO
  329. * and enable keyboard interrupts.
  330. */
  331. while (1) {
  332. val = readl(kbc->mmio + KBC_INT_0);
  333. val >>= 4;
  334. if (!val)
  335. break;
  336. val = readl(kbc->mmio + KBC_KP_ENT0_0);
  337. val = readl(kbc->mmio + KBC_KP_ENT1_0);
  338. }
  339. writel(0x7, kbc->mmio + KBC_INT_0);
  340. enable_irq(kbc->irq);
  341. return 0;
  342. }
  343. static void tegra_kbc_stop(struct tegra_kbc *kbc)
  344. {
  345. unsigned long flags;
  346. u32 val;
  347. spin_lock_irqsave(&kbc->lock, flags);
  348. val = readl(kbc->mmio + KBC_CONTROL_0);
  349. val &= ~1;
  350. writel(val, kbc->mmio + KBC_CONTROL_0);
  351. spin_unlock_irqrestore(&kbc->lock, flags);
  352. disable_irq(kbc->irq);
  353. del_timer_sync(&kbc->timer);
  354. clk_disable_unprepare(kbc->clk);
  355. }
  356. static int tegra_kbc_open(struct input_dev *dev)
  357. {
  358. struct tegra_kbc *kbc = input_get_drvdata(dev);
  359. return tegra_kbc_start(kbc);
  360. }
  361. static void tegra_kbc_close(struct input_dev *dev)
  362. {
  363. struct tegra_kbc *kbc = input_get_drvdata(dev);
  364. return tegra_kbc_stop(kbc);
  365. }
  366. static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc,
  367. unsigned int *num_rows)
  368. {
  369. int i;
  370. *num_rows = 0;
  371. for (i = 0; i < KBC_MAX_GPIO; i++) {
  372. const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i];
  373. switch (pin_cfg->type) {
  374. case PIN_CFG_ROW:
  375. if (pin_cfg->num >= kbc->hw_support->max_rows) {
  376. dev_err(kbc->dev,
  377. "pin_cfg[%d]: invalid row number %d\n",
  378. i, pin_cfg->num);
  379. return false;
  380. }
  381. (*num_rows)++;
  382. break;
  383. case PIN_CFG_COL:
  384. if (pin_cfg->num >= kbc->hw_support->max_columns) {
  385. dev_err(kbc->dev,
  386. "pin_cfg[%d]: invalid column number %d\n",
  387. i, pin_cfg->num);
  388. return false;
  389. }
  390. break;
  391. case PIN_CFG_IGNORE:
  392. break;
  393. default:
  394. dev_err(kbc->dev,
  395. "pin_cfg[%d]: invalid entry type %d\n",
  396. pin_cfg->type, pin_cfg->num);
  397. return false;
  398. }
  399. }
  400. return true;
  401. }
  402. static int tegra_kbc_parse_dt(struct tegra_kbc *kbc)
  403. {
  404. struct device_node *np = kbc->dev->of_node;
  405. u32 prop;
  406. int i;
  407. u32 num_rows = 0;
  408. u32 num_cols = 0;
  409. u32 cols_cfg[KBC_MAX_GPIO];
  410. u32 rows_cfg[KBC_MAX_GPIO];
  411. int proplen;
  412. int ret;
  413. if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop))
  414. kbc->debounce_cnt = prop;
  415. if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop))
  416. kbc->repeat_cnt = prop;
  417. if (of_find_property(np, "nvidia,needs-ghost-filter", NULL))
  418. kbc->use_ghost_filter = true;
  419. if (of_property_read_bool(np, "wakeup-source") ||
  420. of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */
  421. kbc->wakeup = true;
  422. if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) {
  423. dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n");
  424. return -ENOENT;
  425. }
  426. num_rows = proplen / sizeof(u32);
  427. if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) {
  428. dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n");
  429. return -ENOENT;
  430. }
  431. num_cols = proplen / sizeof(u32);
  432. if (num_rows > kbc->hw_support->max_rows) {
  433. dev_err(kbc->dev,
  434. "Number of rows is more than supported by hardware\n");
  435. return -EINVAL;
  436. }
  437. if (num_cols > kbc->hw_support->max_columns) {
  438. dev_err(kbc->dev,
  439. "Number of cols is more than supported by hardware\n");
  440. return -EINVAL;
  441. }
  442. if (!of_get_property(np, "linux,keymap", &proplen)) {
  443. dev_err(kbc->dev, "property linux,keymap not found\n");
  444. return -ENOENT;
  445. }
  446. if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) {
  447. dev_err(kbc->dev,
  448. "keypad rows/columns not properly specified\n");
  449. return -EINVAL;
  450. }
  451. /* Set all pins as non-configured */
  452. for (i = 0; i < kbc->num_rows_and_columns; i++)
  453. kbc->pin_cfg[i].type = PIN_CFG_IGNORE;
  454. ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins",
  455. rows_cfg, num_rows);
  456. if (ret < 0) {
  457. dev_err(kbc->dev, "Rows configurations are not proper\n");
  458. return -EINVAL;
  459. }
  460. ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins",
  461. cols_cfg, num_cols);
  462. if (ret < 0) {
  463. dev_err(kbc->dev, "Cols configurations are not proper\n");
  464. return -EINVAL;
  465. }
  466. for (i = 0; i < num_rows; i++) {
  467. kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW;
  468. kbc->pin_cfg[rows_cfg[i]].num = i;
  469. }
  470. for (i = 0; i < num_cols; i++) {
  471. kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL;
  472. kbc->pin_cfg[cols_cfg[i]].num = i;
  473. }
  474. return 0;
  475. }
  476. static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = {
  477. .max_rows = 16,
  478. .max_columns = 8,
  479. };
  480. static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = {
  481. .max_rows = 11,
  482. .max_columns = 8,
  483. };
  484. static const struct of_device_id tegra_kbc_of_match[] = {
  485. { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support},
  486. { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support},
  487. { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support},
  488. { },
  489. };
  490. MODULE_DEVICE_TABLE(of, tegra_kbc_of_match);
  491. static int tegra_kbc_probe(struct platform_device *pdev)
  492. {
  493. struct tegra_kbc *kbc;
  494. struct resource *res;
  495. int err;
  496. int num_rows = 0;
  497. unsigned int debounce_cnt;
  498. unsigned int scan_time_rows;
  499. unsigned int keymap_rows;
  500. const struct of_device_id *match;
  501. match = of_match_device(tegra_kbc_of_match, &pdev->dev);
  502. kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL);
  503. if (!kbc) {
  504. dev_err(&pdev->dev, "failed to alloc memory for kbc\n");
  505. return -ENOMEM;
  506. }
  507. kbc->dev = &pdev->dev;
  508. kbc->hw_support = match->data;
  509. kbc->max_keys = kbc->hw_support->max_rows *
  510. kbc->hw_support->max_columns;
  511. kbc->num_rows_and_columns = kbc->hw_support->max_rows +
  512. kbc->hw_support->max_columns;
  513. keymap_rows = kbc->max_keys;
  514. spin_lock_init(&kbc->lock);
  515. err = tegra_kbc_parse_dt(kbc);
  516. if (err)
  517. return err;
  518. if (!tegra_kbc_check_pin_cfg(kbc, &num_rows))
  519. return -EINVAL;
  520. kbc->irq = platform_get_irq(pdev, 0);
  521. if (kbc->irq < 0)
  522. return -ENXIO;
  523. kbc->idev = devm_input_allocate_device(&pdev->dev);
  524. if (!kbc->idev) {
  525. dev_err(&pdev->dev, "failed to allocate input device\n");
  526. return -ENOMEM;
  527. }
  528. timer_setup(&kbc->timer, tegra_kbc_keypress_timer, 0);
  529. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  530. kbc->mmio = devm_ioremap_resource(&pdev->dev, res);
  531. if (IS_ERR(kbc->mmio))
  532. return PTR_ERR(kbc->mmio);
  533. kbc->clk = devm_clk_get(&pdev->dev, NULL);
  534. if (IS_ERR(kbc->clk)) {
  535. dev_err(&pdev->dev, "failed to get keyboard clock\n");
  536. return PTR_ERR(kbc->clk);
  537. }
  538. kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
  539. if (IS_ERR(kbc->rst)) {
  540. dev_err(&pdev->dev, "failed to get keyboard reset\n");
  541. return PTR_ERR(kbc->rst);
  542. }
  543. /*
  544. * The time delay between two consecutive reads of the FIFO is
  545. * the sum of the repeat time and the time taken for scanning
  546. * the rows. There is an additional delay before the row scanning
  547. * starts. The repoll delay is computed in milliseconds.
  548. */
  549. debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
  550. scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
  551. kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt;
  552. kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
  553. kbc->idev->name = pdev->name;
  554. kbc->idev->id.bustype = BUS_HOST;
  555. kbc->idev->dev.parent = &pdev->dev;
  556. kbc->idev->open = tegra_kbc_open;
  557. kbc->idev->close = tegra_kbc_close;
  558. if (kbc->keymap_data && kbc->use_fn_map)
  559. keymap_rows *= 2;
  560. err = matrix_keypad_build_keymap(kbc->keymap_data, NULL,
  561. keymap_rows,
  562. kbc->hw_support->max_columns,
  563. kbc->keycode, kbc->idev);
  564. if (err) {
  565. dev_err(&pdev->dev, "failed to setup keymap\n");
  566. return err;
  567. }
  568. __set_bit(EV_REP, kbc->idev->evbit);
  569. input_set_capability(kbc->idev, EV_MSC, MSC_SCAN);
  570. input_set_drvdata(kbc->idev, kbc);
  571. err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr,
  572. IRQF_TRIGGER_HIGH, pdev->name, kbc);
  573. if (err) {
  574. dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
  575. return err;
  576. }
  577. disable_irq(kbc->irq);
  578. err = input_register_device(kbc->idev);
  579. if (err) {
  580. dev_err(&pdev->dev, "failed to register input device\n");
  581. return err;
  582. }
  583. platform_set_drvdata(pdev, kbc);
  584. device_init_wakeup(&pdev->dev, kbc->wakeup);
  585. return 0;
  586. }
  587. #ifdef CONFIG_PM_SLEEP
  588. static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable)
  589. {
  590. u32 val;
  591. val = readl(kbc->mmio + KBC_CONTROL_0);
  592. if (enable)
  593. val |= KBC_CONTROL_KEYPRESS_INT_EN;
  594. else
  595. val &= ~KBC_CONTROL_KEYPRESS_INT_EN;
  596. writel(val, kbc->mmio + KBC_CONTROL_0);
  597. }
  598. static int tegra_kbc_suspend(struct device *dev)
  599. {
  600. struct platform_device *pdev = to_platform_device(dev);
  601. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  602. mutex_lock(&kbc->idev->mutex);
  603. if (device_may_wakeup(&pdev->dev)) {
  604. disable_irq(kbc->irq);
  605. del_timer_sync(&kbc->timer);
  606. tegra_kbc_set_fifo_interrupt(kbc, false);
  607. /* Forcefully clear the interrupt status */
  608. writel(0x7, kbc->mmio + KBC_INT_0);
  609. /*
  610. * Store the previous resident time of continuous polling mode.
  611. * Force the keyboard into interrupt mode.
  612. */
  613. kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0);
  614. writel(0, kbc->mmio + KBC_TO_CNT_0);
  615. tegra_kbc_setup_wakekeys(kbc, true);
  616. msleep(30);
  617. kbc->keypress_caused_wake = false;
  618. /* Enable keypress interrupt before going into suspend. */
  619. tegra_kbc_set_keypress_interrupt(kbc, true);
  620. enable_irq(kbc->irq);
  621. enable_irq_wake(kbc->irq);
  622. } else {
  623. if (kbc->idev->users)
  624. tegra_kbc_stop(kbc);
  625. }
  626. mutex_unlock(&kbc->idev->mutex);
  627. return 0;
  628. }
  629. static int tegra_kbc_resume(struct device *dev)
  630. {
  631. struct platform_device *pdev = to_platform_device(dev);
  632. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  633. int err = 0;
  634. mutex_lock(&kbc->idev->mutex);
  635. if (device_may_wakeup(&pdev->dev)) {
  636. disable_irq_wake(kbc->irq);
  637. tegra_kbc_setup_wakekeys(kbc, false);
  638. /* We will use fifo interrupts for key detection. */
  639. tegra_kbc_set_keypress_interrupt(kbc, false);
  640. /* Restore the resident time of continuous polling mode. */
  641. writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
  642. tegra_kbc_set_fifo_interrupt(kbc, true);
  643. if (kbc->keypress_caused_wake && kbc->wakeup_key) {
  644. /*
  645. * We can't report events directly from the ISR
  646. * because timekeeping is stopped when processing
  647. * wakeup request and we get a nasty warning when
  648. * we try to call do_gettimeofday() in evdev
  649. * handler.
  650. */
  651. input_report_key(kbc->idev, kbc->wakeup_key, 1);
  652. input_sync(kbc->idev);
  653. input_report_key(kbc->idev, kbc->wakeup_key, 0);
  654. input_sync(kbc->idev);
  655. }
  656. } else {
  657. if (kbc->idev->users)
  658. err = tegra_kbc_start(kbc);
  659. }
  660. mutex_unlock(&kbc->idev->mutex);
  661. return err;
  662. }
  663. #endif
  664. static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
  665. static struct platform_driver tegra_kbc_driver = {
  666. .probe = tegra_kbc_probe,
  667. .driver = {
  668. .name = "tegra-kbc",
  669. .pm = &tegra_kbc_pm_ops,
  670. .of_match_table = tegra_kbc_of_match,
  671. },
  672. };
  673. module_platform_driver(tegra_kbc_driver);
  674. MODULE_LICENSE("GPL");
  675. MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
  676. MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
  677. MODULE_ALIAS("platform:tegra-kbc");