mpu3050-core.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MPU3050 gyroscope driver
  4. *
  5. * Copyright (C) 2016 Linaro Ltd.
  6. * Author: Linus Walleij <linus.walleij@linaro.org>
  7. *
  8. * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
  9. * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
  10. * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
  11. * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
  12. *
  13. * TODO: add support for setting up the low pass 3dB frequency.
  14. */
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/iio/buffer.h>
  19. #include <linux/iio/iio.h>
  20. #include <linux/iio/sysfs.h>
  21. #include <linux/iio/trigger.h>
  22. #include <linux/iio/trigger_consumer.h>
  23. #include <linux/iio/triggered_buffer.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/module.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/random.h>
  28. #include <linux/slab.h>
  29. #include "mpu3050.h"
  30. #define MPU3050_CHIP_ID 0x68
  31. #define MPU3050_CHIP_ID_MASK 0x7E
  32. /*
  33. * Register map: anything suffixed *_H is a big-endian high byte and always
  34. * followed by the corresponding low byte (*_L) even though these are not
  35. * explicitly included in the register definitions.
  36. */
  37. #define MPU3050_CHIP_ID_REG 0x00
  38. #define MPU3050_PRODUCT_ID_REG 0x01
  39. #define MPU3050_XG_OFFS_TC 0x05
  40. #define MPU3050_YG_OFFS_TC 0x08
  41. #define MPU3050_ZG_OFFS_TC 0x0B
  42. #define MPU3050_X_OFFS_USR_H 0x0C
  43. #define MPU3050_Y_OFFS_USR_H 0x0E
  44. #define MPU3050_Z_OFFS_USR_H 0x10
  45. #define MPU3050_FIFO_EN 0x12
  46. #define MPU3050_AUX_VDDIO 0x13
  47. #define MPU3050_SLV_ADDR 0x14
  48. #define MPU3050_SMPLRT_DIV 0x15
  49. #define MPU3050_DLPF_FS_SYNC 0x16
  50. #define MPU3050_INT_CFG 0x17
  51. #define MPU3050_AUX_ADDR 0x18
  52. #define MPU3050_INT_STATUS 0x1A
  53. #define MPU3050_TEMP_H 0x1B
  54. #define MPU3050_XOUT_H 0x1D
  55. #define MPU3050_YOUT_H 0x1F
  56. #define MPU3050_ZOUT_H 0x21
  57. #define MPU3050_DMP_CFG1 0x35
  58. #define MPU3050_DMP_CFG2 0x36
  59. #define MPU3050_BANK_SEL 0x37
  60. #define MPU3050_MEM_START_ADDR 0x38
  61. #define MPU3050_MEM_R_W 0x39
  62. #define MPU3050_FIFO_COUNT_H 0x3A
  63. #define MPU3050_FIFO_R 0x3C
  64. #define MPU3050_USR_CTRL 0x3D
  65. #define MPU3050_PWR_MGM 0x3E
  66. /* MPU memory bank read options */
  67. #define MPU3050_MEM_PRFTCH BIT(5)
  68. #define MPU3050_MEM_USER_BANK BIT(4)
  69. /* Bits 8-11 select memory bank */
  70. #define MPU3050_MEM_RAM_BANK_0 0
  71. #define MPU3050_MEM_RAM_BANK_1 1
  72. #define MPU3050_MEM_RAM_BANK_2 2
  73. #define MPU3050_MEM_RAM_BANK_3 3
  74. #define MPU3050_MEM_OTP_BANK_0 4
  75. #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
  76. /* Register bits */
  77. /* FIFO Enable */
  78. #define MPU3050_FIFO_EN_FOOTER BIT(0)
  79. #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
  80. #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
  81. #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
  82. #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
  83. #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
  84. #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
  85. #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
  86. /*
  87. * Digital Low Pass filter (DLPF)
  88. * Full Scale (FS)
  89. * and Synchronization
  90. */
  91. #define MPU3050_EXT_SYNC_NONE 0x00
  92. #define MPU3050_EXT_SYNC_TEMP 0x20
  93. #define MPU3050_EXT_SYNC_GYROX 0x40
  94. #define MPU3050_EXT_SYNC_GYROY 0x60
  95. #define MPU3050_EXT_SYNC_GYROZ 0x80
  96. #define MPU3050_EXT_SYNC_ACCELX 0xA0
  97. #define MPU3050_EXT_SYNC_ACCELY 0xC0
  98. #define MPU3050_EXT_SYNC_ACCELZ 0xE0
  99. #define MPU3050_EXT_SYNC_MASK 0xE0
  100. #define MPU3050_EXT_SYNC_SHIFT 5
  101. #define MPU3050_FS_250DPS 0x00
  102. #define MPU3050_FS_500DPS 0x08
  103. #define MPU3050_FS_1000DPS 0x10
  104. #define MPU3050_FS_2000DPS 0x18
  105. #define MPU3050_FS_MASK 0x18
  106. #define MPU3050_FS_SHIFT 3
  107. #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
  108. #define MPU3050_DLPF_CFG_188HZ 0x01
  109. #define MPU3050_DLPF_CFG_98HZ 0x02
  110. #define MPU3050_DLPF_CFG_42HZ 0x03
  111. #define MPU3050_DLPF_CFG_20HZ 0x04
  112. #define MPU3050_DLPF_CFG_10HZ 0x05
  113. #define MPU3050_DLPF_CFG_5HZ 0x06
  114. #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
  115. #define MPU3050_DLPF_CFG_MASK 0x07
  116. #define MPU3050_DLPF_CFG_SHIFT 0
  117. /* Interrupt config */
  118. #define MPU3050_INT_RAW_RDY_EN BIT(0)
  119. #define MPU3050_INT_DMP_DONE_EN BIT(1)
  120. #define MPU3050_INT_MPU_RDY_EN BIT(2)
  121. #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
  122. #define MPU3050_INT_LATCH_EN BIT(5)
  123. #define MPU3050_INT_OPEN BIT(6)
  124. #define MPU3050_INT_ACTL BIT(7)
  125. /* Interrupt status */
  126. #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
  127. #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
  128. #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
  129. #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
  130. /* USR_CTRL */
  131. #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
  132. #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
  133. #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
  134. #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
  135. #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
  136. /* PWR_MGM */
  137. #define MPU3050_PWR_MGM_PLL_X 0x01
  138. #define MPU3050_PWR_MGM_PLL_Y 0x02
  139. #define MPU3050_PWR_MGM_PLL_Z 0x03
  140. #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
  141. #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
  142. #define MPU3050_PWR_MGM_STBY_YG BIT(4)
  143. #define MPU3050_PWR_MGM_STBY_XG BIT(5)
  144. #define MPU3050_PWR_MGM_SLEEP BIT(6)
  145. #define MPU3050_PWR_MGM_RESET BIT(7)
  146. #define MPU3050_PWR_MGM_MASK 0xff
  147. /*
  148. * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
  149. * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
  150. * in two's complement.
  151. */
  152. static unsigned int mpu3050_fs_precision[] = {
  153. IIO_DEGREE_TO_RAD(250),
  154. IIO_DEGREE_TO_RAD(500),
  155. IIO_DEGREE_TO_RAD(1000),
  156. IIO_DEGREE_TO_RAD(2000)
  157. };
  158. /*
  159. * Regulator names
  160. */
  161. static const char mpu3050_reg_vdd[] = "vdd";
  162. static const char mpu3050_reg_vlogic[] = "vlogic";
  163. static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
  164. {
  165. unsigned int freq;
  166. if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
  167. freq = 8000;
  168. else
  169. freq = 1000;
  170. freq /= (mpu3050->divisor + 1);
  171. return freq;
  172. }
  173. static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
  174. {
  175. __be16 raw_val[3];
  176. int ret;
  177. int i;
  178. /* Reset */
  179. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  180. MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
  181. if (ret)
  182. return ret;
  183. /* Turn on the Z-axis PLL */
  184. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  185. MPU3050_PWR_MGM_CLKSEL_MASK,
  186. MPU3050_PWR_MGM_PLL_Z);
  187. if (ret)
  188. return ret;
  189. /* Write calibration offset registers */
  190. for (i = 0; i < 3; i++)
  191. raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
  192. ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
  193. sizeof(raw_val));
  194. if (ret)
  195. return ret;
  196. /* Set low pass filter (sample rate), sync and full scale */
  197. ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
  198. MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
  199. mpu3050->fullscale << MPU3050_FS_SHIFT |
  200. mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
  201. if (ret)
  202. return ret;
  203. /* Set up sampling frequency */
  204. ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
  205. if (ret)
  206. return ret;
  207. /*
  208. * Max 50 ms start-up time after setting DLPF_FS_SYNC
  209. * according to the data sheet, then wait for the next sample
  210. * at this frequency T = 1000/f ms.
  211. */
  212. msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
  213. return 0;
  214. }
  215. static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
  216. {
  217. int ret;
  218. u8 divisor;
  219. enum mpu3050_lpf lpf;
  220. lpf = mpu3050->lpf;
  221. divisor = mpu3050->divisor;
  222. mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
  223. mpu3050->divisor = 0; /* Divide by 1 */
  224. ret = mpu3050_start_sampling(mpu3050);
  225. mpu3050->lpf = lpf;
  226. mpu3050->divisor = divisor;
  227. return ret;
  228. }
  229. static int mpu3050_read_raw(struct iio_dev *indio_dev,
  230. struct iio_chan_spec const *chan,
  231. int *val, int *val2,
  232. long mask)
  233. {
  234. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  235. int ret;
  236. __be16 raw_val;
  237. switch (mask) {
  238. case IIO_CHAN_INFO_OFFSET:
  239. switch (chan->type) {
  240. case IIO_TEMP:
  241. /*
  242. * The temperature scaling is (x+23000)/280 Celsius
  243. * for the "best fit straight line" temperature range
  244. * of -30C..85C. The 23000 includes room temperature
  245. * offset of +35C, 280 is the precision scale and x is
  246. * the 16-bit signed integer reported by hardware.
  247. *
  248. * Temperature value itself represents temperature of
  249. * the sensor die.
  250. */
  251. *val = 23000;
  252. return IIO_VAL_INT;
  253. default:
  254. return -EINVAL;
  255. }
  256. case IIO_CHAN_INFO_CALIBBIAS:
  257. switch (chan->type) {
  258. case IIO_ANGL_VEL:
  259. *val = mpu3050->calibration[chan->scan_index-1];
  260. return IIO_VAL_INT;
  261. default:
  262. return -EINVAL;
  263. }
  264. case IIO_CHAN_INFO_SAMP_FREQ:
  265. *val = mpu3050_get_freq(mpu3050);
  266. return IIO_VAL_INT;
  267. case IIO_CHAN_INFO_SCALE:
  268. switch (chan->type) {
  269. case IIO_TEMP:
  270. /* Millidegrees, see about temperature scaling above */
  271. *val = 1000;
  272. *val2 = 280;
  273. return IIO_VAL_FRACTIONAL;
  274. case IIO_ANGL_VEL:
  275. /*
  276. * Convert to the corresponding full scale in
  277. * radians. All 16 bits are used with sign to
  278. * span the available scale: to account for the one
  279. * missing value if we multiply by 1/S16_MAX, instead
  280. * multiply with 2/U16_MAX.
  281. */
  282. *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
  283. *val2 = U16_MAX;
  284. return IIO_VAL_FRACTIONAL;
  285. default:
  286. return -EINVAL;
  287. }
  288. case IIO_CHAN_INFO_RAW:
  289. /* Resume device */
  290. pm_runtime_get_sync(mpu3050->dev);
  291. mutex_lock(&mpu3050->lock);
  292. ret = mpu3050_set_8khz_samplerate(mpu3050);
  293. if (ret)
  294. goto out_read_raw_unlock;
  295. switch (chan->type) {
  296. case IIO_TEMP:
  297. ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
  298. &raw_val, sizeof(raw_val));
  299. if (ret) {
  300. dev_err(mpu3050->dev,
  301. "error reading temperature\n");
  302. goto out_read_raw_unlock;
  303. }
  304. *val = (s16)be16_to_cpu(raw_val);
  305. ret = IIO_VAL_INT;
  306. goto out_read_raw_unlock;
  307. case IIO_ANGL_VEL:
  308. ret = regmap_bulk_read(mpu3050->map,
  309. MPU3050_AXIS_REGS(chan->scan_index-1),
  310. &raw_val,
  311. sizeof(raw_val));
  312. if (ret) {
  313. dev_err(mpu3050->dev,
  314. "error reading axis data\n");
  315. goto out_read_raw_unlock;
  316. }
  317. *val = be16_to_cpu(raw_val);
  318. ret = IIO_VAL_INT;
  319. goto out_read_raw_unlock;
  320. default:
  321. ret = -EINVAL;
  322. goto out_read_raw_unlock;
  323. }
  324. default:
  325. break;
  326. }
  327. return -EINVAL;
  328. out_read_raw_unlock:
  329. mutex_unlock(&mpu3050->lock);
  330. pm_runtime_mark_last_busy(mpu3050->dev);
  331. pm_runtime_put_autosuspend(mpu3050->dev);
  332. return ret;
  333. }
  334. static int mpu3050_write_raw(struct iio_dev *indio_dev,
  335. const struct iio_chan_spec *chan,
  336. int val, int val2, long mask)
  337. {
  338. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  339. /*
  340. * Couldn't figure out a way to precalculate these at compile time.
  341. */
  342. unsigned int fs250 =
  343. DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
  344. U16_MAX);
  345. unsigned int fs500 =
  346. DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
  347. U16_MAX);
  348. unsigned int fs1000 =
  349. DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
  350. U16_MAX);
  351. unsigned int fs2000 =
  352. DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
  353. U16_MAX);
  354. switch (mask) {
  355. case IIO_CHAN_INFO_CALIBBIAS:
  356. if (chan->type != IIO_ANGL_VEL)
  357. return -EINVAL;
  358. mpu3050->calibration[chan->scan_index-1] = val;
  359. return 0;
  360. case IIO_CHAN_INFO_SAMP_FREQ:
  361. /*
  362. * The max samplerate is 8000 Hz, the minimum
  363. * 1000 / 256 ~= 4 Hz
  364. */
  365. if (val < 4 || val > 8000)
  366. return -EINVAL;
  367. /*
  368. * Above 1000 Hz we must turn off the digital low pass filter
  369. * so we get a base frequency of 8kHz to the divider
  370. */
  371. if (val > 1000) {
  372. mpu3050->lpf = LPF_256_HZ_NOLPF;
  373. mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
  374. return 0;
  375. }
  376. mpu3050->lpf = LPF_188_HZ;
  377. mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
  378. return 0;
  379. case IIO_CHAN_INFO_SCALE:
  380. if (chan->type != IIO_ANGL_VEL)
  381. return -EINVAL;
  382. /*
  383. * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
  384. * which means we need to round to the closest radians
  385. * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
  386. * rad/s. The scale is then for the 16 bits used to cover
  387. * it 2/(2^16) of that.
  388. */
  389. /* Just too large, set the max range */
  390. if (val != 0) {
  391. mpu3050->fullscale = FS_2000_DPS;
  392. return 0;
  393. }
  394. /*
  395. * Now we're dealing with fractions below zero in millirad/s
  396. * do some integer interpolation and match with the closest
  397. * fullscale in the table.
  398. */
  399. if (val2 <= fs250 ||
  400. val2 < ((fs500 + fs250) / 2))
  401. mpu3050->fullscale = FS_250_DPS;
  402. else if (val2 <= fs500 ||
  403. val2 < ((fs1000 + fs500) / 2))
  404. mpu3050->fullscale = FS_500_DPS;
  405. else if (val2 <= fs1000 ||
  406. val2 < ((fs2000 + fs1000) / 2))
  407. mpu3050->fullscale = FS_1000_DPS;
  408. else
  409. /* Catch-all */
  410. mpu3050->fullscale = FS_2000_DPS;
  411. return 0;
  412. default:
  413. break;
  414. }
  415. return -EINVAL;
  416. }
  417. static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
  418. {
  419. const struct iio_poll_func *pf = p;
  420. struct iio_dev *indio_dev = pf->indio_dev;
  421. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  422. int ret;
  423. /*
  424. * Temperature 1*16 bits
  425. * Three axes 3*16 bits
  426. * Timestamp 64 bits (4*16 bits)
  427. * Sum total 8*16 bits
  428. */
  429. __be16 hw_values[8];
  430. s64 timestamp;
  431. unsigned int datums_from_fifo = 0;
  432. /*
  433. * If we're using the hardware trigger, get the precise timestamp from
  434. * the top half of the threaded IRQ handler. Otherwise get the
  435. * timestamp here so it will be close in time to the actual values
  436. * read from the registers.
  437. */
  438. if (iio_trigger_using_own(indio_dev))
  439. timestamp = mpu3050->hw_timestamp;
  440. else
  441. timestamp = iio_get_time_ns(indio_dev);
  442. mutex_lock(&mpu3050->lock);
  443. /* Using the hardware IRQ trigger? Check the buffer then. */
  444. if (mpu3050->hw_irq_trigger) {
  445. __be16 raw_fifocnt;
  446. u16 fifocnt;
  447. /* X, Y, Z + temperature */
  448. unsigned int bytes_per_datum = 8;
  449. bool fifo_overflow = false;
  450. ret = regmap_bulk_read(mpu3050->map,
  451. MPU3050_FIFO_COUNT_H,
  452. &raw_fifocnt,
  453. sizeof(raw_fifocnt));
  454. if (ret)
  455. goto out_trigger_unlock;
  456. fifocnt = be16_to_cpu(raw_fifocnt);
  457. if (fifocnt == 512) {
  458. dev_info(mpu3050->dev,
  459. "FIFO overflow! Emptying and resetting FIFO\n");
  460. fifo_overflow = true;
  461. /* Reset and enable the FIFO */
  462. ret = regmap_update_bits(mpu3050->map,
  463. MPU3050_USR_CTRL,
  464. MPU3050_USR_CTRL_FIFO_EN |
  465. MPU3050_USR_CTRL_FIFO_RST,
  466. MPU3050_USR_CTRL_FIFO_EN |
  467. MPU3050_USR_CTRL_FIFO_RST);
  468. if (ret) {
  469. dev_info(mpu3050->dev, "error resetting FIFO\n");
  470. goto out_trigger_unlock;
  471. }
  472. mpu3050->pending_fifo_footer = false;
  473. }
  474. if (fifocnt)
  475. dev_dbg(mpu3050->dev,
  476. "%d bytes in the FIFO\n",
  477. fifocnt);
  478. while (!fifo_overflow && fifocnt > bytes_per_datum) {
  479. unsigned int toread;
  480. unsigned int offset;
  481. __be16 fifo_values[5];
  482. /*
  483. * If there is a FIFO footer in the pipe, first clear
  484. * that out. This follows the complex algorithm in the
  485. * datasheet that states that you may never leave the
  486. * FIFO empty after the first reading: you have to
  487. * always leave two footer bytes in it. The footer is
  488. * in practice just two zero bytes.
  489. */
  490. if (mpu3050->pending_fifo_footer) {
  491. toread = bytes_per_datum + 2;
  492. offset = 0;
  493. } else {
  494. toread = bytes_per_datum;
  495. offset = 1;
  496. /* Put in some dummy value */
  497. fifo_values[0] = cpu_to_be16(0xAAAA);
  498. }
  499. ret = regmap_bulk_read(mpu3050->map,
  500. MPU3050_FIFO_R,
  501. &fifo_values[offset],
  502. toread);
  503. if (ret)
  504. goto out_trigger_unlock;
  505. dev_dbg(mpu3050->dev,
  506. "%04x %04x %04x %04x %04x\n",
  507. fifo_values[0],
  508. fifo_values[1],
  509. fifo_values[2],
  510. fifo_values[3],
  511. fifo_values[4]);
  512. /* Index past the footer (fifo_values[0]) and push */
  513. iio_push_to_buffers_with_timestamp(indio_dev,
  514. &fifo_values[1],
  515. timestamp);
  516. fifocnt -= toread;
  517. datums_from_fifo++;
  518. mpu3050->pending_fifo_footer = true;
  519. /*
  520. * If we're emptying the FIFO, just make sure to
  521. * check if something new appeared.
  522. */
  523. if (fifocnt < bytes_per_datum) {
  524. ret = regmap_bulk_read(mpu3050->map,
  525. MPU3050_FIFO_COUNT_H,
  526. &raw_fifocnt,
  527. sizeof(raw_fifocnt));
  528. if (ret)
  529. goto out_trigger_unlock;
  530. fifocnt = be16_to_cpu(raw_fifocnt);
  531. }
  532. if (fifocnt < bytes_per_datum)
  533. dev_dbg(mpu3050->dev,
  534. "%d bytes left in the FIFO\n",
  535. fifocnt);
  536. /*
  537. * At this point, the timestamp that triggered the
  538. * hardware interrupt is no longer valid for what
  539. * we are reading (the interrupt likely fired for
  540. * the value on the top of the FIFO), so set the
  541. * timestamp to zero and let userspace deal with it.
  542. */
  543. timestamp = 0;
  544. }
  545. }
  546. /*
  547. * If we picked some datums from the FIFO that's enough, else
  548. * fall through and just read from the current value registers.
  549. * This happens in two cases:
  550. *
  551. * - We are using some other trigger (external, like an HRTimer)
  552. * than the sensor's own sample generator. In this case the
  553. * sensor is just set to the max sampling frequency and we give
  554. * the trigger a copy of the latest value every time we get here.
  555. *
  556. * - The hardware trigger is active but unused and we actually use
  557. * another trigger which calls here with a frequency higher
  558. * than what the device provides data. We will then just read
  559. * duplicate values directly from the hardware registers.
  560. */
  561. if (datums_from_fifo) {
  562. dev_dbg(mpu3050->dev,
  563. "read %d datums from the FIFO\n",
  564. datums_from_fifo);
  565. goto out_trigger_unlock;
  566. }
  567. ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values,
  568. sizeof(hw_values));
  569. if (ret) {
  570. dev_err(mpu3050->dev,
  571. "error reading axis data\n");
  572. goto out_trigger_unlock;
  573. }
  574. iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp);
  575. out_trigger_unlock:
  576. mutex_unlock(&mpu3050->lock);
  577. iio_trigger_notify_done(indio_dev->trig);
  578. return IRQ_HANDLED;
  579. }
  580. static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
  581. {
  582. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  583. pm_runtime_get_sync(mpu3050->dev);
  584. /* Unless we have OUR trigger active, run at full speed */
  585. if (!mpu3050->hw_irq_trigger)
  586. return mpu3050_set_8khz_samplerate(mpu3050);
  587. return 0;
  588. }
  589. static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
  590. {
  591. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  592. pm_runtime_mark_last_busy(mpu3050->dev);
  593. pm_runtime_put_autosuspend(mpu3050->dev);
  594. return 0;
  595. }
  596. static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
  597. .preenable = mpu3050_buffer_preenable,
  598. .postdisable = mpu3050_buffer_postdisable,
  599. };
  600. static const struct iio_mount_matrix *
  601. mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
  602. const struct iio_chan_spec *chan)
  603. {
  604. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  605. return &mpu3050->orientation;
  606. }
  607. static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
  608. IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
  609. { },
  610. };
  611. #define MPU3050_AXIS_CHANNEL(axis, index) \
  612. { \
  613. .type = IIO_ANGL_VEL, \
  614. .modified = 1, \
  615. .channel2 = IIO_MOD_##axis, \
  616. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  617. BIT(IIO_CHAN_INFO_CALIBBIAS), \
  618. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  619. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
  620. .ext_info = mpu3050_ext_info, \
  621. .scan_index = index, \
  622. .scan_type = { \
  623. .sign = 's', \
  624. .realbits = 16, \
  625. .storagebits = 16, \
  626. .endianness = IIO_BE, \
  627. }, \
  628. }
  629. static const struct iio_chan_spec mpu3050_channels[] = {
  630. {
  631. .type = IIO_TEMP,
  632. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  633. BIT(IIO_CHAN_INFO_SCALE) |
  634. BIT(IIO_CHAN_INFO_OFFSET),
  635. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
  636. .scan_index = 0,
  637. .scan_type = {
  638. .sign = 's',
  639. .realbits = 16,
  640. .storagebits = 16,
  641. .endianness = IIO_BE,
  642. },
  643. },
  644. MPU3050_AXIS_CHANNEL(X, 1),
  645. MPU3050_AXIS_CHANNEL(Y, 2),
  646. MPU3050_AXIS_CHANNEL(Z, 3),
  647. IIO_CHAN_SOFT_TIMESTAMP(4),
  648. };
  649. /* Four channels apart from timestamp, scan mask = 0x0f */
  650. static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
  651. /*
  652. * These are just the hardcoded factors resulting from the more elaborate
  653. * calculations done with fractions in the scale raw get/set functions.
  654. */
  655. static IIO_CONST_ATTR(anglevel_scale_available,
  656. "0.000122070 "
  657. "0.000274658 "
  658. "0.000518798 "
  659. "0.001068115");
  660. static struct attribute *mpu3050_attributes[] = {
  661. &iio_const_attr_anglevel_scale_available.dev_attr.attr,
  662. NULL,
  663. };
  664. static const struct attribute_group mpu3050_attribute_group = {
  665. .attrs = mpu3050_attributes,
  666. };
  667. static const struct iio_info mpu3050_info = {
  668. .read_raw = mpu3050_read_raw,
  669. .write_raw = mpu3050_write_raw,
  670. .attrs = &mpu3050_attribute_group,
  671. };
  672. /**
  673. * mpu3050_read_mem() - read MPU-3050 internal memory
  674. * @mpu3050: device to read from
  675. * @bank: target bank
  676. * @addr: target address
  677. * @len: number of bytes
  678. * @buf: the buffer to store the read bytes in
  679. */
  680. static int mpu3050_read_mem(struct mpu3050 *mpu3050,
  681. u8 bank,
  682. u8 addr,
  683. u8 len,
  684. u8 *buf)
  685. {
  686. int ret;
  687. ret = regmap_write(mpu3050->map,
  688. MPU3050_BANK_SEL,
  689. bank);
  690. if (ret)
  691. return ret;
  692. ret = regmap_write(mpu3050->map,
  693. MPU3050_MEM_START_ADDR,
  694. addr);
  695. if (ret)
  696. return ret;
  697. return regmap_bulk_read(mpu3050->map,
  698. MPU3050_MEM_R_W,
  699. buf,
  700. len);
  701. }
  702. static int mpu3050_hw_init(struct mpu3050 *mpu3050)
  703. {
  704. int ret;
  705. u8 otp[8];
  706. /* Reset */
  707. ret = regmap_update_bits(mpu3050->map,
  708. MPU3050_PWR_MGM,
  709. MPU3050_PWR_MGM_RESET,
  710. MPU3050_PWR_MGM_RESET);
  711. if (ret)
  712. return ret;
  713. /* Turn on the PLL */
  714. ret = regmap_update_bits(mpu3050->map,
  715. MPU3050_PWR_MGM,
  716. MPU3050_PWR_MGM_CLKSEL_MASK,
  717. MPU3050_PWR_MGM_PLL_Z);
  718. if (ret)
  719. return ret;
  720. /* Disable IRQs */
  721. ret = regmap_write(mpu3050->map,
  722. MPU3050_INT_CFG,
  723. 0);
  724. if (ret)
  725. return ret;
  726. /* Read out the 8 bytes of OTP (one-time-programmable) memory */
  727. ret = mpu3050_read_mem(mpu3050,
  728. (MPU3050_MEM_PRFTCH |
  729. MPU3050_MEM_USER_BANK |
  730. MPU3050_MEM_OTP_BANK_0),
  731. 0,
  732. sizeof(otp),
  733. otp);
  734. if (ret)
  735. return ret;
  736. /* This is device-unique data so it goes into the entropy pool */
  737. add_device_randomness(otp, sizeof(otp));
  738. dev_info(mpu3050->dev,
  739. "die ID: %04X, wafer ID: %02X, A lot ID: %04X, "
  740. "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n",
  741. /* Die ID, bits 0-12 */
  742. (otp[1] << 8 | otp[0]) & 0x1fff,
  743. /* Wafer ID, bits 13-17 */
  744. ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5,
  745. /* A lot ID, bits 18-33 */
  746. ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2,
  747. /* W lot ID, bits 34-45 */
  748. ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2,
  749. /* WP ID, bits 47-49 */
  750. ((otp[6] << 8 | otp[5]) & 0x0380) >> 7,
  751. /* rev ID, bits 50-55 */
  752. otp[6] >> 2);
  753. return 0;
  754. }
  755. static int mpu3050_power_up(struct mpu3050 *mpu3050)
  756. {
  757. int ret;
  758. ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
  759. if (ret) {
  760. dev_err(mpu3050->dev, "cannot enable regulators\n");
  761. return ret;
  762. }
  763. /*
  764. * 20-100 ms start-up time for register read/write according to
  765. * the datasheet, be on the safe side and wait 200 ms.
  766. */
  767. msleep(200);
  768. /* Take device out of sleep mode */
  769. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  770. MPU3050_PWR_MGM_SLEEP, 0);
  771. if (ret) {
  772. dev_err(mpu3050->dev, "error setting power mode\n");
  773. return ret;
  774. }
  775. usleep_range(10000, 20000);
  776. return 0;
  777. }
  778. static int mpu3050_power_down(struct mpu3050 *mpu3050)
  779. {
  780. int ret;
  781. /*
  782. * Put MPU-3050 into sleep mode before cutting regulators.
  783. * This is important, because we may not be the sole user
  784. * of the regulator so the power may stay on after this, and
  785. * then we would be wasting power unless we go to sleep mode
  786. * first.
  787. */
  788. ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
  789. MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
  790. if (ret)
  791. dev_err(mpu3050->dev, "error putting to sleep\n");
  792. ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
  793. if (ret)
  794. dev_err(mpu3050->dev, "error disabling regulators\n");
  795. return 0;
  796. }
  797. static irqreturn_t mpu3050_irq_handler(int irq, void *p)
  798. {
  799. struct iio_trigger *trig = p;
  800. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  801. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  802. if (!mpu3050->hw_irq_trigger)
  803. return IRQ_NONE;
  804. /* Get the time stamp as close in time as possible */
  805. mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
  806. return IRQ_WAKE_THREAD;
  807. }
  808. static irqreturn_t mpu3050_irq_thread(int irq, void *p)
  809. {
  810. struct iio_trigger *trig = p;
  811. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  812. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  813. unsigned int val;
  814. int ret;
  815. /* ACK IRQ and check if it was from us */
  816. ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
  817. if (ret) {
  818. dev_err(mpu3050->dev, "error reading IRQ status\n");
  819. return IRQ_HANDLED;
  820. }
  821. if (!(val & MPU3050_INT_STATUS_RAW_RDY))
  822. return IRQ_NONE;
  823. iio_trigger_poll_chained(p);
  824. return IRQ_HANDLED;
  825. }
  826. /**
  827. * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
  828. * @trig: trigger instance
  829. * @enable: true if trigger should be enabled, false to disable
  830. */
  831. static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
  832. bool enable)
  833. {
  834. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  835. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  836. unsigned int val;
  837. int ret;
  838. /* Disabling trigger: disable interrupt and return */
  839. if (!enable) {
  840. /* Disable all interrupts */
  841. ret = regmap_write(mpu3050->map,
  842. MPU3050_INT_CFG,
  843. 0);
  844. if (ret)
  845. dev_err(mpu3050->dev, "error disabling IRQ\n");
  846. /* Clear IRQ flag */
  847. ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
  848. if (ret)
  849. dev_err(mpu3050->dev, "error clearing IRQ status\n");
  850. /* Disable all things in the FIFO and reset it */
  851. ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
  852. if (ret)
  853. dev_err(mpu3050->dev, "error disabling FIFO\n");
  854. ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
  855. MPU3050_USR_CTRL_FIFO_RST);
  856. if (ret)
  857. dev_err(mpu3050->dev, "error resetting FIFO\n");
  858. pm_runtime_mark_last_busy(mpu3050->dev);
  859. pm_runtime_put_autosuspend(mpu3050->dev);
  860. mpu3050->hw_irq_trigger = false;
  861. return 0;
  862. } else {
  863. /* Else we're enabling the trigger from this point */
  864. pm_runtime_get_sync(mpu3050->dev);
  865. mpu3050->hw_irq_trigger = true;
  866. /* Disable all things in the FIFO */
  867. ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
  868. if (ret)
  869. return ret;
  870. /* Reset and enable the FIFO */
  871. ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
  872. MPU3050_USR_CTRL_FIFO_EN |
  873. MPU3050_USR_CTRL_FIFO_RST,
  874. MPU3050_USR_CTRL_FIFO_EN |
  875. MPU3050_USR_CTRL_FIFO_RST);
  876. if (ret)
  877. return ret;
  878. mpu3050->pending_fifo_footer = false;
  879. /* Turn on the FIFO for temp+X+Y+Z */
  880. ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
  881. MPU3050_FIFO_EN_TEMP_OUT |
  882. MPU3050_FIFO_EN_GYRO_XOUT |
  883. MPU3050_FIFO_EN_GYRO_YOUT |
  884. MPU3050_FIFO_EN_GYRO_ZOUT |
  885. MPU3050_FIFO_EN_FOOTER);
  886. if (ret)
  887. return ret;
  888. /* Configure the sample engine */
  889. ret = mpu3050_start_sampling(mpu3050);
  890. if (ret)
  891. return ret;
  892. /* Clear IRQ flag */
  893. ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
  894. if (ret)
  895. dev_err(mpu3050->dev, "error clearing IRQ status\n");
  896. /* Give us interrupts whenever there is new data ready */
  897. val = MPU3050_INT_RAW_RDY_EN;
  898. if (mpu3050->irq_actl)
  899. val |= MPU3050_INT_ACTL;
  900. if (mpu3050->irq_latch)
  901. val |= MPU3050_INT_LATCH_EN;
  902. if (mpu3050->irq_opendrain)
  903. val |= MPU3050_INT_OPEN;
  904. ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
  905. if (ret)
  906. return ret;
  907. }
  908. return 0;
  909. }
  910. static const struct iio_trigger_ops mpu3050_trigger_ops = {
  911. .set_trigger_state = mpu3050_drdy_trigger_set_state,
  912. };
  913. static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
  914. {
  915. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  916. unsigned long irq_trig;
  917. int ret;
  918. mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
  919. "%s-dev%d",
  920. indio_dev->name,
  921. indio_dev->id);
  922. if (!mpu3050->trig)
  923. return -ENOMEM;
  924. /* Check if IRQ is open drain */
  925. if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
  926. mpu3050->irq_opendrain = true;
  927. irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
  928. /*
  929. * Configure the interrupt generator hardware to supply whatever
  930. * the interrupt is configured for, edges low/high level low/high,
  931. * we can provide it all.
  932. */
  933. switch (irq_trig) {
  934. case IRQF_TRIGGER_RISING:
  935. dev_info(&indio_dev->dev,
  936. "pulse interrupts on the rising edge\n");
  937. break;
  938. case IRQF_TRIGGER_FALLING:
  939. mpu3050->irq_actl = true;
  940. dev_info(&indio_dev->dev,
  941. "pulse interrupts on the falling edge\n");
  942. break;
  943. case IRQF_TRIGGER_HIGH:
  944. mpu3050->irq_latch = true;
  945. dev_info(&indio_dev->dev,
  946. "interrupts active high level\n");
  947. /*
  948. * With level IRQs, we mask the IRQ until it is processed,
  949. * but with edge IRQs (pulses) we can queue several interrupts
  950. * in the top half.
  951. */
  952. irq_trig |= IRQF_ONESHOT;
  953. break;
  954. case IRQF_TRIGGER_LOW:
  955. mpu3050->irq_latch = true;
  956. mpu3050->irq_actl = true;
  957. irq_trig |= IRQF_ONESHOT;
  958. dev_info(&indio_dev->dev,
  959. "interrupts active low level\n");
  960. break;
  961. default:
  962. /* This is the most preferred mode, if possible */
  963. dev_err(&indio_dev->dev,
  964. "unsupported IRQ trigger specified (%lx), enforce "
  965. "rising edge\n", irq_trig);
  966. irq_trig = IRQF_TRIGGER_RISING;
  967. break;
  968. }
  969. /* An open drain line can be shared with several devices */
  970. if (mpu3050->irq_opendrain)
  971. irq_trig |= IRQF_SHARED;
  972. ret = request_threaded_irq(irq,
  973. mpu3050_irq_handler,
  974. mpu3050_irq_thread,
  975. irq_trig,
  976. mpu3050->trig->name,
  977. mpu3050->trig);
  978. if (ret) {
  979. dev_err(mpu3050->dev,
  980. "can't get IRQ %d, error %d\n", irq, ret);
  981. return ret;
  982. }
  983. mpu3050->irq = irq;
  984. mpu3050->trig->dev.parent = mpu3050->dev;
  985. mpu3050->trig->ops = &mpu3050_trigger_ops;
  986. iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
  987. ret = iio_trigger_register(mpu3050->trig);
  988. if (ret)
  989. return ret;
  990. indio_dev->trig = iio_trigger_get(mpu3050->trig);
  991. return 0;
  992. }
  993. int mpu3050_common_probe(struct device *dev,
  994. struct regmap *map,
  995. int irq,
  996. const char *name)
  997. {
  998. struct iio_dev *indio_dev;
  999. struct mpu3050 *mpu3050;
  1000. unsigned int val;
  1001. int ret;
  1002. indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
  1003. if (!indio_dev)
  1004. return -ENOMEM;
  1005. mpu3050 = iio_priv(indio_dev);
  1006. mpu3050->dev = dev;
  1007. mpu3050->map = map;
  1008. mutex_init(&mpu3050->lock);
  1009. /* Default fullscale: 2000 degrees per second */
  1010. mpu3050->fullscale = FS_2000_DPS;
  1011. /* 1 kHz, divide by 100, default frequency = 10 Hz */
  1012. mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
  1013. mpu3050->divisor = 99;
  1014. /* Read the mounting matrix, if present */
  1015. ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation);
  1016. if (ret)
  1017. return ret;
  1018. /* Fetch and turn on regulators */
  1019. mpu3050->regs[0].supply = mpu3050_reg_vdd;
  1020. mpu3050->regs[1].supply = mpu3050_reg_vlogic;
  1021. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
  1022. mpu3050->regs);
  1023. if (ret) {
  1024. dev_err(dev, "Cannot get regulators\n");
  1025. return ret;
  1026. }
  1027. ret = mpu3050_power_up(mpu3050);
  1028. if (ret)
  1029. return ret;
  1030. ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
  1031. if (ret) {
  1032. dev_err(dev, "could not read device ID\n");
  1033. ret = -ENODEV;
  1034. goto err_power_down;
  1035. }
  1036. if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
  1037. dev_err(dev, "unsupported chip id %02x\n",
  1038. (u8)(val & MPU3050_CHIP_ID_MASK));
  1039. ret = -ENODEV;
  1040. goto err_power_down;
  1041. }
  1042. ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
  1043. if (ret) {
  1044. dev_err(dev, "could not read device ID\n");
  1045. ret = -ENODEV;
  1046. goto err_power_down;
  1047. }
  1048. dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
  1049. ((val >> 4) & 0xf), (val & 0xf));
  1050. ret = mpu3050_hw_init(mpu3050);
  1051. if (ret)
  1052. goto err_power_down;
  1053. indio_dev->channels = mpu3050_channels;
  1054. indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
  1055. indio_dev->info = &mpu3050_info;
  1056. indio_dev->available_scan_masks = mpu3050_scan_masks;
  1057. indio_dev->modes = INDIO_DIRECT_MODE;
  1058. indio_dev->name = name;
  1059. ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
  1060. mpu3050_trigger_handler,
  1061. &mpu3050_buffer_setup_ops);
  1062. if (ret) {
  1063. dev_err(dev, "triggered buffer setup failed\n");
  1064. goto err_power_down;
  1065. }
  1066. ret = iio_device_register(indio_dev);
  1067. if (ret) {
  1068. dev_err(dev, "device register failed\n");
  1069. goto err_cleanup_buffer;
  1070. }
  1071. dev_set_drvdata(dev, indio_dev);
  1072. /* Check if we have an assigned IRQ to use as trigger */
  1073. if (irq) {
  1074. ret = mpu3050_trigger_probe(indio_dev, irq);
  1075. if (ret)
  1076. dev_err(dev, "failed to register trigger\n");
  1077. }
  1078. /* Enable runtime PM */
  1079. pm_runtime_get_noresume(dev);
  1080. pm_runtime_set_active(dev);
  1081. pm_runtime_enable(dev);
  1082. /*
  1083. * Set autosuspend to two orders of magnitude larger than the
  1084. * start-up time. 100ms start-up time means 10000ms autosuspend,
  1085. * i.e. 10 seconds.
  1086. */
  1087. pm_runtime_set_autosuspend_delay(dev, 10000);
  1088. pm_runtime_use_autosuspend(dev);
  1089. pm_runtime_put(dev);
  1090. return 0;
  1091. err_cleanup_buffer:
  1092. iio_triggered_buffer_cleanup(indio_dev);
  1093. err_power_down:
  1094. mpu3050_power_down(mpu3050);
  1095. return ret;
  1096. }
  1097. EXPORT_SYMBOL(mpu3050_common_probe);
  1098. int mpu3050_common_remove(struct device *dev)
  1099. {
  1100. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1101. struct mpu3050 *mpu3050 = iio_priv(indio_dev);
  1102. pm_runtime_get_sync(dev);
  1103. pm_runtime_put_noidle(dev);
  1104. pm_runtime_disable(dev);
  1105. iio_triggered_buffer_cleanup(indio_dev);
  1106. if (mpu3050->irq)
  1107. free_irq(mpu3050->irq, mpu3050);
  1108. iio_device_unregister(indio_dev);
  1109. mpu3050_power_down(mpu3050);
  1110. return 0;
  1111. }
  1112. EXPORT_SYMBOL(mpu3050_common_remove);
  1113. #ifdef CONFIG_PM
  1114. static int mpu3050_runtime_suspend(struct device *dev)
  1115. {
  1116. return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
  1117. }
  1118. static int mpu3050_runtime_resume(struct device *dev)
  1119. {
  1120. return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
  1121. }
  1122. #endif /* CONFIG_PM */
  1123. const struct dev_pm_ops mpu3050_dev_pm_ops = {
  1124. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1125. pm_runtime_force_resume)
  1126. SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
  1127. mpu3050_runtime_resume, NULL)
  1128. };
  1129. EXPORT_SYMBOL(mpu3050_dev_pm_ops);
  1130. MODULE_AUTHOR("Linus Walleij");
  1131. MODULE_DESCRIPTION("MPU3050 gyroscope driver");
  1132. MODULE_LICENSE("GPL");