fxas21002c_core.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for NXP FXAS21002C Gyroscope - Core
  4. *
  5. * Copyright (C) 2019 Linaro Ltd.
  6. */
  7. #include <linux/interrupt.h>
  8. #include <linux/module.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/pm.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/regmap.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/iio/events.h>
  15. #include <linux/iio/iio.h>
  16. #include <linux/iio/buffer.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/iio/trigger.h>
  19. #include <linux/iio/trigger_consumer.h>
  20. #include <linux/iio/triggered_buffer.h>
  21. #include "fxas21002c.h"
  22. #define FXAS21002C_CHIP_ID_1 0xD6
  23. #define FXAS21002C_CHIP_ID_2 0xD7
  24. enum fxas21002c_mode_state {
  25. FXAS21002C_MODE_STANDBY,
  26. FXAS21002C_MODE_READY,
  27. FXAS21002C_MODE_ACTIVE,
  28. };
  29. #define FXAS21002C_STANDBY_ACTIVE_TIME_MS 62
  30. #define FXAS21002C_READY_ACTIVE_TIME_MS 7
  31. #define FXAS21002C_ODR_LIST_MAX 10
  32. #define FXAS21002C_SCALE_FRACTIONAL 32
  33. #define FXAS21002C_RANGE_LIMIT_DOUBLE 2000
  34. #define FXAS21002C_AXIS_TO_REG(axis) (FXAS21002C_REG_OUT_X_MSB + ((axis) * 2))
  35. static const struct reg_field fxas21002c_reg_fields[] = {
  36. [F_DR_STATUS] = REG_FIELD(FXAS21002C_REG_STATUS, 0, 7),
  37. [F_OUT_X_MSB] = REG_FIELD(FXAS21002C_REG_OUT_X_MSB, 0, 7),
  38. [F_OUT_X_LSB] = REG_FIELD(FXAS21002C_REG_OUT_X_LSB, 0, 7),
  39. [F_OUT_Y_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_MSB, 0, 7),
  40. [F_OUT_Y_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_LSB, 0, 7),
  41. [F_OUT_Z_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_MSB, 0, 7),
  42. [F_OUT_Z_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_LSB, 0, 7),
  43. [F_ZYX_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 7, 7),
  44. [F_Z_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 6, 6),
  45. [F_Y_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 5, 5),
  46. [F_X_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 4, 4),
  47. [F_ZYX_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 3, 3),
  48. [F_Z_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 2, 2),
  49. [F_Y_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 1, 1),
  50. [F_X_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 0, 0),
  51. [F_OVF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 7, 7),
  52. [F_WMKF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 6, 6),
  53. [F_CNT] = REG_FIELD(FXAS21002C_REG_F_STATUS, 0, 5),
  54. [F_MODE] = REG_FIELD(FXAS21002C_REG_F_SETUP, 6, 7),
  55. [F_WMRK] = REG_FIELD(FXAS21002C_REG_F_SETUP, 0, 5),
  56. [F_EVENT] = REG_FIELD(FXAS21002C_REG_F_EVENT, 5, 5),
  57. [FE_TIME] = REG_FIELD(FXAS21002C_REG_F_EVENT, 0, 4),
  58. [F_BOOTEND] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 3, 3),
  59. [F_SRC_FIFO] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 2, 2),
  60. [F_SRC_RT] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 1, 1),
  61. [F_SRC_DRDY] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 0, 0),
  62. [F_WHO_AM_I] = REG_FIELD(FXAS21002C_REG_WHO_AM_I, 0, 7),
  63. [F_BW] = REG_FIELD(FXAS21002C_REG_CTRL0, 6, 7),
  64. [F_SPIW] = REG_FIELD(FXAS21002C_REG_CTRL0, 5, 5),
  65. [F_SEL] = REG_FIELD(FXAS21002C_REG_CTRL0, 3, 4),
  66. [F_HPF_EN] = REG_FIELD(FXAS21002C_REG_CTRL0, 2, 2),
  67. [F_FS] = REG_FIELD(FXAS21002C_REG_CTRL0, 0, 1),
  68. [F_ELE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 3, 3),
  69. [F_ZTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 2, 2),
  70. [F_YTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 1, 1),
  71. [F_XTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 0, 0),
  72. [F_EA] = REG_FIELD(FXAS21002C_REG_RT_SRC, 6, 6),
  73. [F_ZRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 5, 5),
  74. [F_ZRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 4, 4),
  75. [F_YRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 3, 3),
  76. [F_YRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 2, 2),
  77. [F_XRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 1, 1),
  78. [F_XRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 0),
  79. [F_DBCNTM] = REG_FIELD(FXAS21002C_REG_RT_THS, 7, 7),
  80. [F_THS] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 6),
  81. [F_RT_COUNT] = REG_FIELD(FXAS21002C_REG_RT_COUNT, 0, 7),
  82. [F_TEMP] = REG_FIELD(FXAS21002C_REG_TEMP, 0, 7),
  83. [F_RST] = REG_FIELD(FXAS21002C_REG_CTRL1, 6, 6),
  84. [F_ST] = REG_FIELD(FXAS21002C_REG_CTRL1, 5, 5),
  85. [F_DR] = REG_FIELD(FXAS21002C_REG_CTRL1, 2, 4),
  86. [F_ACTIVE] = REG_FIELD(FXAS21002C_REG_CTRL1, 1, 1),
  87. [F_READY] = REG_FIELD(FXAS21002C_REG_CTRL1, 0, 0),
  88. [F_INT_CFG_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 7, 7),
  89. [F_INT_EN_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 6, 6),
  90. [F_INT_CFG_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 5, 5),
  91. [F_INT_EN_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 4, 4),
  92. [F_INT_CFG_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 3, 3),
  93. [F_INT_EN_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 2, 2),
  94. [F_IPOL] = REG_FIELD(FXAS21002C_REG_CTRL2, 1, 1),
  95. [F_PP_OD] = REG_FIELD(FXAS21002C_REG_CTRL2, 0, 0),
  96. [F_WRAPTOONE] = REG_FIELD(FXAS21002C_REG_CTRL3, 3, 3),
  97. [F_EXTCTRLEN] = REG_FIELD(FXAS21002C_REG_CTRL3, 2, 2),
  98. [F_FS_DOUBLE] = REG_FIELD(FXAS21002C_REG_CTRL3, 0, 0),
  99. };
  100. static const int fxas21002c_odr_values[] = {
  101. 800, 400, 200, 100, 50, 25, 12, 12
  102. };
  103. /*
  104. * These values are taken from the low-pass filter cutoff frequency calculated
  105. * ODR * 0.lpf_values. So, for ODR = 800Hz with a lpf value = 0.32
  106. * => LPF cutoff frequency = 800 * 0.32 = 256 Hz
  107. */
  108. static const int fxas21002c_lpf_values[] = {
  109. 32, 16, 8
  110. };
  111. /*
  112. * These values are taken from the high-pass filter cutoff frequency calculated
  113. * ODR * 0.0hpf_values. So, for ODR = 800Hz with a hpf value = 0.018750
  114. * => HPF cutoff frequency = 800 * 0.018750 = 15 Hz
  115. */
  116. static const int fxas21002c_hpf_values[] = {
  117. 18750, 9625, 4875, 2475
  118. };
  119. static const int fxas21002c_range_values[] = {
  120. 4000, 2000, 1000, 500, 250
  121. };
  122. struct fxas21002c_data {
  123. u8 chip_id;
  124. enum fxas21002c_mode_state mode;
  125. enum fxas21002c_mode_state prev_mode;
  126. struct mutex lock; /* serialize data access */
  127. struct regmap *regmap;
  128. struct regmap_field *regmap_fields[F_MAX_FIELDS];
  129. struct iio_trigger *dready_trig;
  130. s64 timestamp;
  131. int irq;
  132. struct regulator *vdd;
  133. struct regulator *vddio;
  134. /*
  135. * DMA (thus cache coherency maintenance) requires the
  136. * transfer buffers to live in their own cache lines.
  137. */
  138. s16 buffer[8] ____cacheline_aligned;
  139. };
  140. enum fxas21002c_channel_index {
  141. CHANNEL_SCAN_INDEX_X,
  142. CHANNEL_SCAN_INDEX_Y,
  143. CHANNEL_SCAN_INDEX_Z,
  144. CHANNEL_SCAN_MAX,
  145. };
  146. static int fxas21002c_odr_hz_from_value(struct fxas21002c_data *data, u8 value)
  147. {
  148. int odr_value_max = ARRAY_SIZE(fxas21002c_odr_values) - 1;
  149. value = min_t(u8, value, odr_value_max);
  150. return fxas21002c_odr_values[value];
  151. }
  152. static int fxas21002c_odr_value_from_hz(struct fxas21002c_data *data,
  153. unsigned int hz)
  154. {
  155. int odr_table_size = ARRAY_SIZE(fxas21002c_odr_values);
  156. int i;
  157. for (i = 0; i < odr_table_size; i++)
  158. if (fxas21002c_odr_values[i] == hz)
  159. return i;
  160. return -EINVAL;
  161. }
  162. static int fxas21002c_lpf_bw_from_value(struct fxas21002c_data *data, u8 value)
  163. {
  164. int lpf_value_max = ARRAY_SIZE(fxas21002c_lpf_values) - 1;
  165. value = min_t(u8, value, lpf_value_max);
  166. return fxas21002c_lpf_values[value];
  167. }
  168. static int fxas21002c_lpf_value_from_bw(struct fxas21002c_data *data,
  169. unsigned int hz)
  170. {
  171. int lpf_table_size = ARRAY_SIZE(fxas21002c_lpf_values);
  172. int i;
  173. for (i = 0; i < lpf_table_size; i++)
  174. if (fxas21002c_lpf_values[i] == hz)
  175. return i;
  176. return -EINVAL;
  177. }
  178. static int fxas21002c_hpf_sel_from_value(struct fxas21002c_data *data, u8 value)
  179. {
  180. int hpf_value_max = ARRAY_SIZE(fxas21002c_hpf_values) - 1;
  181. value = min_t(u8, value, hpf_value_max);
  182. return fxas21002c_hpf_values[value];
  183. }
  184. static int fxas21002c_hpf_value_from_sel(struct fxas21002c_data *data,
  185. unsigned int hz)
  186. {
  187. int hpf_table_size = ARRAY_SIZE(fxas21002c_hpf_values);
  188. int i;
  189. for (i = 0; i < hpf_table_size; i++)
  190. if (fxas21002c_hpf_values[i] == hz)
  191. return i;
  192. return -EINVAL;
  193. }
  194. static int fxas21002c_range_fs_from_value(struct fxas21002c_data *data,
  195. u8 value)
  196. {
  197. int range_value_max = ARRAY_SIZE(fxas21002c_range_values) - 1;
  198. unsigned int fs_double;
  199. int ret;
  200. /* We need to check if FS_DOUBLE is enabled to offset the value */
  201. ret = regmap_field_read(data->regmap_fields[F_FS_DOUBLE], &fs_double);
  202. if (ret < 0)
  203. return ret;
  204. if (!fs_double)
  205. value += 1;
  206. value = min_t(u8, value, range_value_max);
  207. return fxas21002c_range_values[value];
  208. }
  209. static int fxas21002c_range_value_from_fs(struct fxas21002c_data *data,
  210. unsigned int range)
  211. {
  212. int range_table_size = ARRAY_SIZE(fxas21002c_range_values);
  213. bool found = false;
  214. int fs_double = 0;
  215. int ret;
  216. int i;
  217. for (i = 0; i < range_table_size; i++)
  218. if (fxas21002c_range_values[i] == range) {
  219. found = true;
  220. break;
  221. }
  222. if (!found)
  223. return -EINVAL;
  224. if (range > FXAS21002C_RANGE_LIMIT_DOUBLE)
  225. fs_double = 1;
  226. ret = regmap_field_write(data->regmap_fields[F_FS_DOUBLE], fs_double);
  227. if (ret < 0)
  228. return ret;
  229. return i;
  230. }
  231. static int fxas21002c_mode_get(struct fxas21002c_data *data)
  232. {
  233. unsigned int active;
  234. unsigned int ready;
  235. int ret;
  236. ret = regmap_field_read(data->regmap_fields[F_ACTIVE], &active);
  237. if (ret < 0)
  238. return ret;
  239. if (active)
  240. return FXAS21002C_MODE_ACTIVE;
  241. ret = regmap_field_read(data->regmap_fields[F_READY], &ready);
  242. if (ret < 0)
  243. return ret;
  244. if (ready)
  245. return FXAS21002C_MODE_READY;
  246. return FXAS21002C_MODE_STANDBY;
  247. }
  248. static int fxas21002c_mode_set(struct fxas21002c_data *data,
  249. enum fxas21002c_mode_state mode)
  250. {
  251. int ret;
  252. if (mode == data->mode)
  253. return 0;
  254. if (mode == FXAS21002C_MODE_READY)
  255. ret = regmap_field_write(data->regmap_fields[F_READY], 1);
  256. else
  257. ret = regmap_field_write(data->regmap_fields[F_READY], 0);
  258. if (ret < 0)
  259. return ret;
  260. if (mode == FXAS21002C_MODE_ACTIVE)
  261. ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 1);
  262. else
  263. ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 0);
  264. if (ret < 0)
  265. return ret;
  266. /* if going to active wait the setup times */
  267. if (mode == FXAS21002C_MODE_ACTIVE &&
  268. data->mode == FXAS21002C_MODE_STANDBY)
  269. msleep_interruptible(FXAS21002C_STANDBY_ACTIVE_TIME_MS);
  270. if (data->mode == FXAS21002C_MODE_READY)
  271. msleep_interruptible(FXAS21002C_READY_ACTIVE_TIME_MS);
  272. data->prev_mode = data->mode;
  273. data->mode = mode;
  274. return ret;
  275. }
  276. static int fxas21002c_write(struct fxas21002c_data *data,
  277. enum fxas21002c_fields field, int bits)
  278. {
  279. int actual_mode;
  280. int ret;
  281. mutex_lock(&data->lock);
  282. actual_mode = fxas21002c_mode_get(data);
  283. if (actual_mode < 0) {
  284. ret = actual_mode;
  285. goto out_unlock;
  286. }
  287. ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
  288. if (ret < 0)
  289. goto out_unlock;
  290. ret = regmap_field_write(data->regmap_fields[field], bits);
  291. if (ret < 0)
  292. goto out_unlock;
  293. ret = fxas21002c_mode_set(data, data->prev_mode);
  294. out_unlock:
  295. mutex_unlock(&data->lock);
  296. return ret;
  297. }
  298. static int fxas21002c_pm_get(struct fxas21002c_data *data)
  299. {
  300. return pm_runtime_resume_and_get(regmap_get_device(data->regmap));
  301. }
  302. static int fxas21002c_pm_put(struct fxas21002c_data *data)
  303. {
  304. struct device *dev = regmap_get_device(data->regmap);
  305. pm_runtime_mark_last_busy(dev);
  306. return pm_runtime_put_autosuspend(dev);
  307. }
  308. static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val)
  309. {
  310. struct device *dev = regmap_get_device(data->regmap);
  311. unsigned int temp;
  312. int ret;
  313. mutex_lock(&data->lock);
  314. ret = fxas21002c_pm_get(data);
  315. if (ret < 0)
  316. goto data_unlock;
  317. ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp);
  318. if (ret < 0) {
  319. dev_err(dev, "failed to read temp: %d\n", ret);
  320. fxas21002c_pm_put(data);
  321. goto data_unlock;
  322. }
  323. *val = sign_extend32(temp, 7);
  324. ret = fxas21002c_pm_put(data);
  325. if (ret < 0)
  326. goto data_unlock;
  327. ret = IIO_VAL_INT;
  328. data_unlock:
  329. mutex_unlock(&data->lock);
  330. return ret;
  331. }
  332. static int fxas21002c_axis_get(struct fxas21002c_data *data,
  333. int index, int *val)
  334. {
  335. struct device *dev = regmap_get_device(data->regmap);
  336. __be16 axis_be;
  337. int ret;
  338. mutex_lock(&data->lock);
  339. ret = fxas21002c_pm_get(data);
  340. if (ret < 0)
  341. goto data_unlock;
  342. ret = regmap_bulk_read(data->regmap, FXAS21002C_AXIS_TO_REG(index),
  343. &axis_be, sizeof(axis_be));
  344. if (ret < 0) {
  345. dev_err(dev, "failed to read axis: %d: %d\n", index, ret);
  346. fxas21002c_pm_put(data);
  347. goto data_unlock;
  348. }
  349. *val = sign_extend32(be16_to_cpu(axis_be), 15);
  350. ret = fxas21002c_pm_put(data);
  351. if (ret < 0)
  352. goto data_unlock;
  353. ret = IIO_VAL_INT;
  354. data_unlock:
  355. mutex_unlock(&data->lock);
  356. return ret;
  357. }
  358. static int fxas21002c_odr_get(struct fxas21002c_data *data, int *odr)
  359. {
  360. unsigned int odr_bits;
  361. int ret;
  362. mutex_lock(&data->lock);
  363. ret = regmap_field_read(data->regmap_fields[F_DR], &odr_bits);
  364. if (ret < 0)
  365. goto data_unlock;
  366. *odr = fxas21002c_odr_hz_from_value(data, odr_bits);
  367. ret = IIO_VAL_INT;
  368. data_unlock:
  369. mutex_unlock(&data->lock);
  370. return ret;
  371. }
  372. static int fxas21002c_odr_set(struct fxas21002c_data *data, int odr)
  373. {
  374. int odr_bits;
  375. odr_bits = fxas21002c_odr_value_from_hz(data, odr);
  376. if (odr_bits < 0)
  377. return odr_bits;
  378. return fxas21002c_write(data, F_DR, odr_bits);
  379. }
  380. static int fxas21002c_lpf_get(struct fxas21002c_data *data, int *val2)
  381. {
  382. unsigned int bw_bits;
  383. int ret;
  384. mutex_lock(&data->lock);
  385. ret = regmap_field_read(data->regmap_fields[F_BW], &bw_bits);
  386. if (ret < 0)
  387. goto data_unlock;
  388. *val2 = fxas21002c_lpf_bw_from_value(data, bw_bits) * 10000;
  389. ret = IIO_VAL_INT_PLUS_MICRO;
  390. data_unlock:
  391. mutex_unlock(&data->lock);
  392. return ret;
  393. }
  394. static int fxas21002c_lpf_set(struct fxas21002c_data *data, int bw)
  395. {
  396. int bw_bits;
  397. int odr;
  398. int ret;
  399. bw_bits = fxas21002c_lpf_value_from_bw(data, bw);
  400. if (bw_bits < 0)
  401. return bw_bits;
  402. /*
  403. * From table 33 of the device spec, for ODR = 25Hz and 12.5 value 0.08
  404. * is not allowed and for ODR = 12.5 value 0.16 is also not allowed
  405. */
  406. ret = fxas21002c_odr_get(data, &odr);
  407. if (ret < 0)
  408. return -EINVAL;
  409. if ((odr == 25 && bw_bits > 0x01) || (odr == 12 && bw_bits > 0))
  410. return -EINVAL;
  411. return fxas21002c_write(data, F_BW, bw_bits);
  412. }
  413. static int fxas21002c_hpf_get(struct fxas21002c_data *data, int *val2)
  414. {
  415. unsigned int sel_bits;
  416. int ret;
  417. mutex_lock(&data->lock);
  418. ret = regmap_field_read(data->regmap_fields[F_SEL], &sel_bits);
  419. if (ret < 0)
  420. goto data_unlock;
  421. *val2 = fxas21002c_hpf_sel_from_value(data, sel_bits);
  422. ret = IIO_VAL_INT_PLUS_MICRO;
  423. data_unlock:
  424. mutex_unlock(&data->lock);
  425. return ret;
  426. }
  427. static int fxas21002c_hpf_set(struct fxas21002c_data *data, int sel)
  428. {
  429. int sel_bits;
  430. sel_bits = fxas21002c_hpf_value_from_sel(data, sel);
  431. if (sel_bits < 0)
  432. return sel_bits;
  433. return fxas21002c_write(data, F_SEL, sel_bits);
  434. }
  435. static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val)
  436. {
  437. int fs_bits;
  438. int scale;
  439. int ret;
  440. mutex_lock(&data->lock);
  441. ret = regmap_field_read(data->regmap_fields[F_FS], &fs_bits);
  442. if (ret < 0)
  443. goto data_unlock;
  444. scale = fxas21002c_range_fs_from_value(data, fs_bits);
  445. if (scale < 0) {
  446. ret = scale;
  447. goto data_unlock;
  448. }
  449. *val = scale;
  450. data_unlock:
  451. mutex_unlock(&data->lock);
  452. return ret;
  453. }
  454. static int fxas21002c_scale_set(struct fxas21002c_data *data, int range)
  455. {
  456. int fs_bits;
  457. fs_bits = fxas21002c_range_value_from_fs(data, range);
  458. if (fs_bits < 0)
  459. return fs_bits;
  460. return fxas21002c_write(data, F_FS, fs_bits);
  461. }
  462. static int fxas21002c_read_raw(struct iio_dev *indio_dev,
  463. struct iio_chan_spec const *chan, int *val,
  464. int *val2, long mask)
  465. {
  466. struct fxas21002c_data *data = iio_priv(indio_dev);
  467. int ret;
  468. switch (mask) {
  469. case IIO_CHAN_INFO_RAW:
  470. switch (chan->type) {
  471. case IIO_TEMP:
  472. return fxas21002c_temp_get(data, val);
  473. case IIO_ANGL_VEL:
  474. return fxas21002c_axis_get(data, chan->scan_index, val);
  475. default:
  476. return -EINVAL;
  477. }
  478. case IIO_CHAN_INFO_SCALE:
  479. switch (chan->type) {
  480. case IIO_ANGL_VEL:
  481. *val2 = FXAS21002C_SCALE_FRACTIONAL;
  482. ret = fxas21002c_scale_get(data, val);
  483. if (ret < 0)
  484. return ret;
  485. return IIO_VAL_FRACTIONAL;
  486. default:
  487. return -EINVAL;
  488. }
  489. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  490. *val = 0;
  491. return fxas21002c_lpf_get(data, val2);
  492. case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
  493. *val = 0;
  494. return fxas21002c_hpf_get(data, val2);
  495. case IIO_CHAN_INFO_SAMP_FREQ:
  496. *val2 = 0;
  497. return fxas21002c_odr_get(data, val);
  498. default:
  499. return -EINVAL;
  500. }
  501. }
  502. static int fxas21002c_write_raw(struct iio_dev *indio_dev,
  503. struct iio_chan_spec const *chan, int val,
  504. int val2, long mask)
  505. {
  506. struct fxas21002c_data *data = iio_priv(indio_dev);
  507. int range;
  508. switch (mask) {
  509. case IIO_CHAN_INFO_SAMP_FREQ:
  510. if (val2)
  511. return -EINVAL;
  512. return fxas21002c_odr_set(data, val);
  513. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  514. if (val)
  515. return -EINVAL;
  516. val2 = val2 / 10000;
  517. return fxas21002c_lpf_set(data, val2);
  518. case IIO_CHAN_INFO_SCALE:
  519. switch (chan->type) {
  520. case IIO_ANGL_VEL:
  521. range = (((val * 1000 + val2 / 1000) *
  522. FXAS21002C_SCALE_FRACTIONAL) / 1000);
  523. return fxas21002c_scale_set(data, range);
  524. default:
  525. return -EINVAL;
  526. }
  527. case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
  528. return fxas21002c_hpf_set(data, val2);
  529. default:
  530. return -EINVAL;
  531. }
  532. }
  533. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800");
  534. static IIO_CONST_ATTR(in_anglvel_filter_low_pass_3db_frequency_available,
  535. "0.32 0.16 0.08");
  536. static IIO_CONST_ATTR(in_anglvel_filter_high_pass_3db_frequency_available,
  537. "0.018750 0.009625 0.004875 0.002475");
  538. static IIO_CONST_ATTR(in_anglvel_scale_available,
  539. "125.0 62.5 31.25 15.625 7.8125");
  540. static struct attribute *fxas21002c_attributes[] = {
  541. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  542. &iio_const_attr_in_anglvel_filter_low_pass_3db_frequency_available.dev_attr.attr,
  543. &iio_const_attr_in_anglvel_filter_high_pass_3db_frequency_available.dev_attr.attr,
  544. &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
  545. NULL,
  546. };
  547. static const struct attribute_group fxas21002c_attrs_group = {
  548. .attrs = fxas21002c_attributes,
  549. };
  550. #define FXAS21002C_CHANNEL(_axis) { \
  551. .type = IIO_ANGL_VEL, \
  552. .modified = 1, \
  553. .channel2 = IIO_MOD_##_axis, \
  554. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  555. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  556. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
  557. BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
  558. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  559. .scan_index = CHANNEL_SCAN_INDEX_##_axis, \
  560. .scan_type = { \
  561. .sign = 's', \
  562. .realbits = 16, \
  563. .storagebits = 16, \
  564. .endianness = IIO_BE, \
  565. }, \
  566. }
  567. static const struct iio_chan_spec fxas21002c_channels[] = {
  568. {
  569. .type = IIO_TEMP,
  570. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
  571. .scan_index = -1,
  572. },
  573. FXAS21002C_CHANNEL(X),
  574. FXAS21002C_CHANNEL(Y),
  575. FXAS21002C_CHANNEL(Z),
  576. };
  577. static const struct iio_info fxas21002c_info = {
  578. .attrs = &fxas21002c_attrs_group,
  579. .read_raw = &fxas21002c_read_raw,
  580. .write_raw = &fxas21002c_write_raw,
  581. };
  582. static irqreturn_t fxas21002c_trigger_handler(int irq, void *p)
  583. {
  584. struct iio_poll_func *pf = p;
  585. struct iio_dev *indio_dev = pf->indio_dev;
  586. struct fxas21002c_data *data = iio_priv(indio_dev);
  587. int ret;
  588. mutex_lock(&data->lock);
  589. ret = regmap_bulk_read(data->regmap, FXAS21002C_REG_OUT_X_MSB,
  590. data->buffer, CHANNEL_SCAN_MAX * sizeof(s16));
  591. if (ret < 0)
  592. goto out_unlock;
  593. iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
  594. data->timestamp);
  595. out_unlock:
  596. mutex_unlock(&data->lock);
  597. iio_trigger_notify_done(indio_dev->trig);
  598. return IRQ_HANDLED;
  599. }
  600. static int fxas21002c_chip_init(struct fxas21002c_data *data)
  601. {
  602. struct device *dev = regmap_get_device(data->regmap);
  603. unsigned int chip_id;
  604. int ret;
  605. ret = regmap_field_read(data->regmap_fields[F_WHO_AM_I], &chip_id);
  606. if (ret < 0)
  607. return ret;
  608. if (chip_id != FXAS21002C_CHIP_ID_1 &&
  609. chip_id != FXAS21002C_CHIP_ID_2) {
  610. dev_err(dev, "chip id 0x%02x is not supported\n", chip_id);
  611. return -EINVAL;
  612. }
  613. data->chip_id = chip_id;
  614. ret = fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
  615. if (ret < 0)
  616. return ret;
  617. /* Set ODR to 200HZ as default */
  618. ret = fxas21002c_odr_set(data, 200);
  619. if (ret < 0)
  620. dev_err(dev, "failed to set ODR: %d\n", ret);
  621. return ret;
  622. }
  623. static int fxas21002c_data_rdy_trigger_set_state(struct iio_trigger *trig,
  624. bool state)
  625. {
  626. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  627. struct fxas21002c_data *data = iio_priv(indio_dev);
  628. return regmap_field_write(data->regmap_fields[F_INT_EN_DRDY], state);
  629. }
  630. static const struct iio_trigger_ops fxas21002c_trigger_ops = {
  631. .set_trigger_state = &fxas21002c_data_rdy_trigger_set_state,
  632. };
  633. static irqreturn_t fxas21002c_data_rdy_handler(int irq, void *private)
  634. {
  635. struct iio_dev *indio_dev = private;
  636. struct fxas21002c_data *data = iio_priv(indio_dev);
  637. data->timestamp = iio_get_time_ns(indio_dev);
  638. return IRQ_WAKE_THREAD;
  639. }
  640. static irqreturn_t fxas21002c_data_rdy_thread(int irq, void *private)
  641. {
  642. struct iio_dev *indio_dev = private;
  643. struct fxas21002c_data *data = iio_priv(indio_dev);
  644. unsigned int data_ready;
  645. int ret;
  646. ret = regmap_field_read(data->regmap_fields[F_SRC_DRDY], &data_ready);
  647. if (ret < 0)
  648. return IRQ_NONE;
  649. if (!data_ready)
  650. return IRQ_NONE;
  651. iio_trigger_poll_chained(data->dready_trig);
  652. return IRQ_HANDLED;
  653. }
  654. static int fxas21002c_trigger_probe(struct fxas21002c_data *data)
  655. {
  656. struct device *dev = regmap_get_device(data->regmap);
  657. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  658. struct device_node *np = indio_dev->dev.of_node;
  659. unsigned long irq_trig;
  660. bool irq_open_drain;
  661. int irq1;
  662. int ret;
  663. if (!data->irq)
  664. return 0;
  665. irq1 = of_irq_get_byname(np, "INT1");
  666. if (irq1 == data->irq) {
  667. dev_info(dev, "using interrupt line INT1\n");
  668. ret = regmap_field_write(data->regmap_fields[F_INT_CFG_DRDY],
  669. 1);
  670. if (ret < 0)
  671. return ret;
  672. }
  673. dev_info(dev, "using interrupt line INT2\n");
  674. irq_open_drain = of_property_read_bool(np, "drive-open-drain");
  675. data->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
  676. indio_dev->name,
  677. indio_dev->id);
  678. if (!data->dready_trig)
  679. return -ENOMEM;
  680. irq_trig = irqd_get_trigger_type(irq_get_irq_data(data->irq));
  681. if (irq_trig == IRQF_TRIGGER_RISING) {
  682. ret = regmap_field_write(data->regmap_fields[F_IPOL], 1);
  683. if (ret < 0)
  684. return ret;
  685. }
  686. if (irq_open_drain)
  687. irq_trig |= IRQF_SHARED;
  688. ret = devm_request_threaded_irq(dev, data->irq,
  689. fxas21002c_data_rdy_handler,
  690. fxas21002c_data_rdy_thread,
  691. irq_trig, "fxas21002c_data_ready",
  692. indio_dev);
  693. if (ret < 0)
  694. return ret;
  695. data->dready_trig->dev.parent = dev;
  696. data->dready_trig->ops = &fxas21002c_trigger_ops;
  697. iio_trigger_set_drvdata(data->dready_trig, indio_dev);
  698. return devm_iio_trigger_register(dev, data->dready_trig);
  699. }
  700. static int fxas21002c_power_enable(struct fxas21002c_data *data)
  701. {
  702. int ret;
  703. ret = regulator_enable(data->vdd);
  704. if (ret < 0)
  705. return ret;
  706. ret = regulator_enable(data->vddio);
  707. if (ret < 0) {
  708. regulator_disable(data->vdd);
  709. return ret;
  710. }
  711. return 0;
  712. }
  713. static void fxas21002c_power_disable(struct fxas21002c_data *data)
  714. {
  715. regulator_disable(data->vdd);
  716. regulator_disable(data->vddio);
  717. }
  718. static void fxas21002c_power_disable_action(void *_data)
  719. {
  720. struct fxas21002c_data *data = _data;
  721. fxas21002c_power_disable(data);
  722. }
  723. static int fxas21002c_regulators_get(struct fxas21002c_data *data)
  724. {
  725. struct device *dev = regmap_get_device(data->regmap);
  726. data->vdd = devm_regulator_get(dev->parent, "vdd");
  727. if (IS_ERR(data->vdd))
  728. return PTR_ERR(data->vdd);
  729. data->vddio = devm_regulator_get(dev->parent, "vddio");
  730. return PTR_ERR_OR_ZERO(data->vddio);
  731. }
  732. int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq,
  733. const char *name)
  734. {
  735. struct fxas21002c_data *data;
  736. struct iio_dev *indio_dev;
  737. struct regmap_field *f;
  738. int i;
  739. int ret;
  740. indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
  741. if (!indio_dev)
  742. return -ENOMEM;
  743. data = iio_priv(indio_dev);
  744. dev_set_drvdata(dev, indio_dev);
  745. data->irq = irq;
  746. data->regmap = regmap;
  747. for (i = 0; i < F_MAX_FIELDS; i++) {
  748. f = devm_regmap_field_alloc(dev, data->regmap,
  749. fxas21002c_reg_fields[i]);
  750. if (IS_ERR(f))
  751. return PTR_ERR(f);
  752. data->regmap_fields[i] = f;
  753. }
  754. mutex_init(&data->lock);
  755. ret = fxas21002c_regulators_get(data);
  756. if (ret < 0)
  757. return ret;
  758. ret = fxas21002c_power_enable(data);
  759. if (ret < 0)
  760. return ret;
  761. ret = devm_add_action_or_reset(dev, fxas21002c_power_disable_action,
  762. data);
  763. if (ret < 0)
  764. return ret;
  765. ret = fxas21002c_chip_init(data);
  766. if (ret < 0)
  767. return ret;
  768. indio_dev->channels = fxas21002c_channels;
  769. indio_dev->num_channels = ARRAY_SIZE(fxas21002c_channels);
  770. indio_dev->name = name;
  771. indio_dev->modes = INDIO_DIRECT_MODE;
  772. indio_dev->info = &fxas21002c_info;
  773. ret = fxas21002c_trigger_probe(data);
  774. if (ret < 0)
  775. return ret;
  776. ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
  777. fxas21002c_trigger_handler, NULL);
  778. if (ret < 0)
  779. return ret;
  780. ret = pm_runtime_set_active(dev);
  781. if (ret)
  782. return ret;
  783. pm_runtime_enable(dev);
  784. pm_runtime_set_autosuspend_delay(dev, 2000);
  785. pm_runtime_use_autosuspend(dev);
  786. ret = iio_device_register(indio_dev);
  787. if (ret < 0)
  788. goto pm_disable;
  789. return 0;
  790. pm_disable:
  791. pm_runtime_disable(dev);
  792. pm_runtime_set_suspended(dev);
  793. return ret;
  794. }
  795. EXPORT_SYMBOL_GPL(fxas21002c_core_probe);
  796. void fxas21002c_core_remove(struct device *dev)
  797. {
  798. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  799. iio_device_unregister(indio_dev);
  800. pm_runtime_disable(dev);
  801. pm_runtime_set_suspended(dev);
  802. }
  803. EXPORT_SYMBOL_GPL(fxas21002c_core_remove);
  804. static int __maybe_unused fxas21002c_suspend(struct device *dev)
  805. {
  806. struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
  807. fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
  808. fxas21002c_power_disable(data);
  809. return 0;
  810. }
  811. static int __maybe_unused fxas21002c_resume(struct device *dev)
  812. {
  813. struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
  814. int ret;
  815. ret = fxas21002c_power_enable(data);
  816. if (ret < 0)
  817. return ret;
  818. return fxas21002c_mode_set(data, data->prev_mode);
  819. }
  820. static int __maybe_unused fxas21002c_runtime_suspend(struct device *dev)
  821. {
  822. struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
  823. return fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
  824. }
  825. static int __maybe_unused fxas21002c_runtime_resume(struct device *dev)
  826. {
  827. struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
  828. return fxas21002c_mode_set(data, FXAS21002C_MODE_ACTIVE);
  829. }
  830. const struct dev_pm_ops fxas21002c_pm_ops = {
  831. SET_SYSTEM_SLEEP_PM_OPS(fxas21002c_suspend, fxas21002c_resume)
  832. SET_RUNTIME_PM_OPS(fxas21002c_runtime_suspend,
  833. fxas21002c_runtime_resume, NULL)
  834. };
  835. EXPORT_SYMBOL_GPL(fxas21002c_pm_ops);
  836. MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
  837. MODULE_LICENSE("GPL v2");
  838. MODULE_DESCRIPTION("FXAS21002C Gyro driver");