bmg160_core.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * BMG160 Gyro Sensor driver
  4. * Copyright (c) 2014, Intel Corporation.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/delay.h>
  9. #include <linux/slab.h>
  10. #include <linux/acpi.h>
  11. #include <linux/pm.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/iio/iio.h>
  14. #include <linux/iio/sysfs.h>
  15. #include <linux/iio/buffer.h>
  16. #include <linux/iio/trigger.h>
  17. #include <linux/iio/events.h>
  18. #include <linux/iio/trigger_consumer.h>
  19. #include <linux/iio/triggered_buffer.h>
  20. #include <linux/regmap.h>
  21. #include "bmg160.h"
  22. #define BMG160_IRQ_NAME "bmg160_event"
  23. #define BMG160_REG_CHIP_ID 0x00
  24. #define BMG160_CHIP_ID_VAL 0x0F
  25. #define BMG160_REG_PMU_LPW 0x11
  26. #define BMG160_MODE_NORMAL 0x00
  27. #define BMG160_MODE_DEEP_SUSPEND 0x20
  28. #define BMG160_MODE_SUSPEND 0x80
  29. #define BMG160_REG_RANGE 0x0F
  30. #define BMG160_RANGE_2000DPS 0
  31. #define BMG160_RANGE_1000DPS 1
  32. #define BMG160_RANGE_500DPS 2
  33. #define BMG160_RANGE_250DPS 3
  34. #define BMG160_RANGE_125DPS 4
  35. #define BMG160_REG_PMU_BW 0x10
  36. #define BMG160_NO_FILTER 0
  37. #define BMG160_DEF_BW 100
  38. #define BMG160_REG_PMU_BW_RES BIT(7)
  39. #define BMG160_GYRO_REG_RESET 0x14
  40. #define BMG160_GYRO_RESET_VAL 0xb6
  41. #define BMG160_REG_INT_MAP_0 0x17
  42. #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
  43. #define BMG160_REG_INT_MAP_1 0x18
  44. #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
  45. #define BMG160_REG_INT_RST_LATCH 0x21
  46. #define BMG160_INT_MODE_LATCH_RESET 0x80
  47. #define BMG160_INT_MODE_LATCH_INT 0x0F
  48. #define BMG160_INT_MODE_NON_LATCH_INT 0x00
  49. #define BMG160_REG_INT_EN_0 0x15
  50. #define BMG160_DATA_ENABLE_INT BIT(7)
  51. #define BMG160_REG_INT_EN_1 0x16
  52. #define BMG160_INT1_BIT_OD BIT(1)
  53. #define BMG160_REG_XOUT_L 0x02
  54. #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
  55. #define BMG160_REG_SLOPE_THRES 0x1B
  56. #define BMG160_SLOPE_THRES_MASK 0x0F
  57. #define BMG160_REG_MOTION_INTR 0x1C
  58. #define BMG160_INT_MOTION_X BIT(0)
  59. #define BMG160_INT_MOTION_Y BIT(1)
  60. #define BMG160_INT_MOTION_Z BIT(2)
  61. #define BMG160_ANY_DUR_MASK 0x30
  62. #define BMG160_ANY_DUR_SHIFT 4
  63. #define BMG160_REG_INT_STATUS_2 0x0B
  64. #define BMG160_ANY_MOTION_MASK 0x07
  65. #define BMG160_ANY_MOTION_BIT_X BIT(0)
  66. #define BMG160_ANY_MOTION_BIT_Y BIT(1)
  67. #define BMG160_ANY_MOTION_BIT_Z BIT(2)
  68. #define BMG160_REG_TEMP 0x08
  69. #define BMG160_TEMP_CENTER_VAL 23
  70. #define BMG160_MAX_STARTUP_TIME_MS 80
  71. #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
  72. struct bmg160_data {
  73. struct regmap *regmap;
  74. struct iio_trigger *dready_trig;
  75. struct iio_trigger *motion_trig;
  76. struct iio_mount_matrix orientation;
  77. struct mutex mutex;
  78. /* Ensure naturally aligned timestamp */
  79. struct {
  80. s16 chans[3];
  81. s64 timestamp __aligned(8);
  82. } scan;
  83. u32 dps_range;
  84. int ev_enable_state;
  85. int slope_thres;
  86. bool dready_trigger_on;
  87. bool motion_trigger_on;
  88. int irq;
  89. };
  90. enum bmg160_axis {
  91. AXIS_X,
  92. AXIS_Y,
  93. AXIS_Z,
  94. AXIS_MAX,
  95. };
  96. static const struct {
  97. int odr;
  98. int filter;
  99. int bw_bits;
  100. } bmg160_samp_freq_table[] = { {100, 32, 0x07},
  101. {200, 64, 0x06},
  102. {100, 12, 0x05},
  103. {200, 23, 0x04},
  104. {400, 47, 0x03},
  105. {1000, 116, 0x02},
  106. {2000, 230, 0x01} };
  107. static const struct {
  108. int scale;
  109. int dps_range;
  110. } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
  111. { 532, BMG160_RANGE_1000DPS},
  112. { 266, BMG160_RANGE_500DPS},
  113. { 133, BMG160_RANGE_250DPS},
  114. { 66, BMG160_RANGE_125DPS} };
  115. static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
  116. {
  117. struct device *dev = regmap_get_device(data->regmap);
  118. int ret;
  119. ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
  120. if (ret < 0) {
  121. dev_err(dev, "Error writing reg_pmu_lpw\n");
  122. return ret;
  123. }
  124. return 0;
  125. }
  126. static int bmg160_convert_freq_to_bit(int val)
  127. {
  128. int i;
  129. for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
  130. if (bmg160_samp_freq_table[i].odr == val)
  131. return bmg160_samp_freq_table[i].bw_bits;
  132. }
  133. return -EINVAL;
  134. }
  135. static int bmg160_set_bw(struct bmg160_data *data, int val)
  136. {
  137. struct device *dev = regmap_get_device(data->regmap);
  138. int ret;
  139. int bw_bits;
  140. bw_bits = bmg160_convert_freq_to_bit(val);
  141. if (bw_bits < 0)
  142. return bw_bits;
  143. ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
  144. if (ret < 0) {
  145. dev_err(dev, "Error writing reg_pmu_bw\n");
  146. return ret;
  147. }
  148. return 0;
  149. }
  150. static int bmg160_get_filter(struct bmg160_data *data, int *val)
  151. {
  152. struct device *dev = regmap_get_device(data->regmap);
  153. int ret;
  154. int i;
  155. unsigned int bw_bits;
  156. ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
  157. if (ret < 0) {
  158. dev_err(dev, "Error reading reg_pmu_bw\n");
  159. return ret;
  160. }
  161. /* Ignore the readonly reserved bit. */
  162. bw_bits &= ~BMG160_REG_PMU_BW_RES;
  163. for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
  164. if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
  165. break;
  166. }
  167. *val = bmg160_samp_freq_table[i].filter;
  168. return ret ? ret : IIO_VAL_INT;
  169. }
  170. static int bmg160_set_filter(struct bmg160_data *data, int val)
  171. {
  172. struct device *dev = regmap_get_device(data->regmap);
  173. int ret;
  174. int i;
  175. for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
  176. if (bmg160_samp_freq_table[i].filter == val)
  177. break;
  178. }
  179. ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
  180. bmg160_samp_freq_table[i].bw_bits);
  181. if (ret < 0) {
  182. dev_err(dev, "Error writing reg_pmu_bw\n");
  183. return ret;
  184. }
  185. return 0;
  186. }
  187. static int bmg160_chip_init(struct bmg160_data *data)
  188. {
  189. struct device *dev = regmap_get_device(data->regmap);
  190. int ret;
  191. unsigned int val;
  192. /*
  193. * Reset chip to get it in a known good state. A delay of 30ms after
  194. * reset is required according to the datasheet.
  195. */
  196. regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
  197. BMG160_GYRO_RESET_VAL);
  198. usleep_range(30000, 30700);
  199. ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
  200. if (ret < 0) {
  201. dev_err(dev, "Error reading reg_chip_id\n");
  202. return ret;
  203. }
  204. dev_dbg(dev, "Chip Id %x\n", val);
  205. if (val != BMG160_CHIP_ID_VAL) {
  206. dev_err(dev, "invalid chip %x\n", val);
  207. return -ENODEV;
  208. }
  209. ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
  210. if (ret < 0)
  211. return ret;
  212. /* Wait upto 500 ms to be ready after changing mode */
  213. usleep_range(500, 1000);
  214. /* Set Bandwidth */
  215. ret = bmg160_set_bw(data, BMG160_DEF_BW);
  216. if (ret < 0)
  217. return ret;
  218. /* Set Default Range */
  219. ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
  220. if (ret < 0) {
  221. dev_err(dev, "Error writing reg_range\n");
  222. return ret;
  223. }
  224. data->dps_range = BMG160_RANGE_500DPS;
  225. ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
  226. if (ret < 0) {
  227. dev_err(dev, "Error reading reg_slope_thres\n");
  228. return ret;
  229. }
  230. data->slope_thres = val;
  231. /* Set default interrupt mode */
  232. ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
  233. BMG160_INT1_BIT_OD, 0);
  234. if (ret < 0) {
  235. dev_err(dev, "Error updating bits in reg_int_en_1\n");
  236. return ret;
  237. }
  238. ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
  239. BMG160_INT_MODE_LATCH_INT |
  240. BMG160_INT_MODE_LATCH_RESET);
  241. if (ret < 0) {
  242. dev_err(dev,
  243. "Error writing reg_motion_intr\n");
  244. return ret;
  245. }
  246. return 0;
  247. }
  248. static int bmg160_set_power_state(struct bmg160_data *data, bool on)
  249. {
  250. #ifdef CONFIG_PM
  251. struct device *dev = regmap_get_device(data->regmap);
  252. int ret;
  253. if (on)
  254. ret = pm_runtime_get_sync(dev);
  255. else {
  256. pm_runtime_mark_last_busy(dev);
  257. ret = pm_runtime_put_autosuspend(dev);
  258. }
  259. if (ret < 0) {
  260. dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
  261. if (on)
  262. pm_runtime_put_noidle(dev);
  263. return ret;
  264. }
  265. #endif
  266. return 0;
  267. }
  268. static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
  269. bool status)
  270. {
  271. struct device *dev = regmap_get_device(data->regmap);
  272. int ret;
  273. /* Enable/Disable INT_MAP0 mapping */
  274. ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
  275. BMG160_INT_MAP_0_BIT_ANY,
  276. (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
  277. if (ret < 0) {
  278. dev_err(dev, "Error updating bits reg_int_map0\n");
  279. return ret;
  280. }
  281. /* Enable/Disable slope interrupts */
  282. if (status) {
  283. /* Update slope thres */
  284. ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
  285. data->slope_thres);
  286. if (ret < 0) {
  287. dev_err(dev, "Error writing reg_slope_thres\n");
  288. return ret;
  289. }
  290. ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
  291. BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
  292. BMG160_INT_MOTION_Z);
  293. if (ret < 0) {
  294. dev_err(dev, "Error writing reg_motion_intr\n");
  295. return ret;
  296. }
  297. /*
  298. * New data interrupt is always non-latched,
  299. * which will have higher priority, so no need
  300. * to set latched mode, we will be flooded anyway with INTR
  301. */
  302. if (!data->dready_trigger_on) {
  303. ret = regmap_write(data->regmap,
  304. BMG160_REG_INT_RST_LATCH,
  305. BMG160_INT_MODE_LATCH_INT |
  306. BMG160_INT_MODE_LATCH_RESET);
  307. if (ret < 0) {
  308. dev_err(dev, "Error writing reg_rst_latch\n");
  309. return ret;
  310. }
  311. }
  312. ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
  313. BMG160_DATA_ENABLE_INT);
  314. } else {
  315. ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
  316. }
  317. if (ret < 0) {
  318. dev_err(dev, "Error writing reg_int_en0\n");
  319. return ret;
  320. }
  321. return 0;
  322. }
  323. static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
  324. bool status)
  325. {
  326. struct device *dev = regmap_get_device(data->regmap);
  327. int ret;
  328. /* Enable/Disable INT_MAP1 mapping */
  329. ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
  330. BMG160_INT_MAP_1_BIT_NEW_DATA,
  331. (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
  332. if (ret < 0) {
  333. dev_err(dev, "Error updating bits in reg_int_map1\n");
  334. return ret;
  335. }
  336. if (status) {
  337. ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
  338. BMG160_INT_MODE_NON_LATCH_INT |
  339. BMG160_INT_MODE_LATCH_RESET);
  340. if (ret < 0) {
  341. dev_err(dev, "Error writing reg_rst_latch\n");
  342. return ret;
  343. }
  344. ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
  345. BMG160_DATA_ENABLE_INT);
  346. } else {
  347. /* Restore interrupt mode */
  348. ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
  349. BMG160_INT_MODE_LATCH_INT |
  350. BMG160_INT_MODE_LATCH_RESET);
  351. if (ret < 0) {
  352. dev_err(dev, "Error writing reg_rst_latch\n");
  353. return ret;
  354. }
  355. ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
  356. }
  357. if (ret < 0) {
  358. dev_err(dev, "Error writing reg_int_en0\n");
  359. return ret;
  360. }
  361. return 0;
  362. }
  363. static int bmg160_get_bw(struct bmg160_data *data, int *val)
  364. {
  365. struct device *dev = regmap_get_device(data->regmap);
  366. int i;
  367. unsigned int bw_bits;
  368. int ret;
  369. ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
  370. if (ret < 0) {
  371. dev_err(dev, "Error reading reg_pmu_bw\n");
  372. return ret;
  373. }
  374. /* Ignore the readonly reserved bit. */
  375. bw_bits &= ~BMG160_REG_PMU_BW_RES;
  376. for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
  377. if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
  378. *val = bmg160_samp_freq_table[i].odr;
  379. return IIO_VAL_INT;
  380. }
  381. }
  382. return -EINVAL;
  383. }
  384. static int bmg160_set_scale(struct bmg160_data *data, int val)
  385. {
  386. struct device *dev = regmap_get_device(data->regmap);
  387. int ret, i;
  388. for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
  389. if (bmg160_scale_table[i].scale == val) {
  390. ret = regmap_write(data->regmap, BMG160_REG_RANGE,
  391. bmg160_scale_table[i].dps_range);
  392. if (ret < 0) {
  393. dev_err(dev, "Error writing reg_range\n");
  394. return ret;
  395. }
  396. data->dps_range = bmg160_scale_table[i].dps_range;
  397. return 0;
  398. }
  399. }
  400. return -EINVAL;
  401. }
  402. static int bmg160_get_temp(struct bmg160_data *data, int *val)
  403. {
  404. struct device *dev = regmap_get_device(data->regmap);
  405. int ret;
  406. unsigned int raw_val;
  407. mutex_lock(&data->mutex);
  408. ret = bmg160_set_power_state(data, true);
  409. if (ret < 0) {
  410. mutex_unlock(&data->mutex);
  411. return ret;
  412. }
  413. ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
  414. if (ret < 0) {
  415. dev_err(dev, "Error reading reg_temp\n");
  416. bmg160_set_power_state(data, false);
  417. mutex_unlock(&data->mutex);
  418. return ret;
  419. }
  420. *val = sign_extend32(raw_val, 7);
  421. ret = bmg160_set_power_state(data, false);
  422. mutex_unlock(&data->mutex);
  423. if (ret < 0)
  424. return ret;
  425. return IIO_VAL_INT;
  426. }
  427. static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
  428. {
  429. struct device *dev = regmap_get_device(data->regmap);
  430. int ret;
  431. __le16 raw_val;
  432. mutex_lock(&data->mutex);
  433. ret = bmg160_set_power_state(data, true);
  434. if (ret < 0) {
  435. mutex_unlock(&data->mutex);
  436. return ret;
  437. }
  438. ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
  439. sizeof(raw_val));
  440. if (ret < 0) {
  441. dev_err(dev, "Error reading axis %d\n", axis);
  442. bmg160_set_power_state(data, false);
  443. mutex_unlock(&data->mutex);
  444. return ret;
  445. }
  446. *val = sign_extend32(le16_to_cpu(raw_val), 15);
  447. ret = bmg160_set_power_state(data, false);
  448. mutex_unlock(&data->mutex);
  449. if (ret < 0)
  450. return ret;
  451. return IIO_VAL_INT;
  452. }
  453. static int bmg160_read_raw(struct iio_dev *indio_dev,
  454. struct iio_chan_spec const *chan,
  455. int *val, int *val2, long mask)
  456. {
  457. struct bmg160_data *data = iio_priv(indio_dev);
  458. int ret;
  459. switch (mask) {
  460. case IIO_CHAN_INFO_RAW:
  461. switch (chan->type) {
  462. case IIO_TEMP:
  463. return bmg160_get_temp(data, val);
  464. case IIO_ANGL_VEL:
  465. if (iio_buffer_enabled(indio_dev))
  466. return -EBUSY;
  467. else
  468. return bmg160_get_axis(data, chan->scan_index,
  469. val);
  470. default:
  471. return -EINVAL;
  472. }
  473. case IIO_CHAN_INFO_OFFSET:
  474. if (chan->type == IIO_TEMP) {
  475. *val = BMG160_TEMP_CENTER_VAL;
  476. return IIO_VAL_INT;
  477. } else
  478. return -EINVAL;
  479. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  480. return bmg160_get_filter(data, val);
  481. case IIO_CHAN_INFO_SCALE:
  482. switch (chan->type) {
  483. case IIO_TEMP:
  484. *val = 500;
  485. return IIO_VAL_INT;
  486. case IIO_ANGL_VEL:
  487. {
  488. int i;
  489. for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
  490. if (bmg160_scale_table[i].dps_range ==
  491. data->dps_range) {
  492. *val = 0;
  493. *val2 = bmg160_scale_table[i].scale;
  494. return IIO_VAL_INT_PLUS_MICRO;
  495. }
  496. }
  497. return -EINVAL;
  498. }
  499. default:
  500. return -EINVAL;
  501. }
  502. case IIO_CHAN_INFO_SAMP_FREQ:
  503. *val2 = 0;
  504. mutex_lock(&data->mutex);
  505. ret = bmg160_get_bw(data, val);
  506. mutex_unlock(&data->mutex);
  507. return ret;
  508. default:
  509. return -EINVAL;
  510. }
  511. }
  512. static int bmg160_write_raw(struct iio_dev *indio_dev,
  513. struct iio_chan_spec const *chan,
  514. int val, int val2, long mask)
  515. {
  516. struct bmg160_data *data = iio_priv(indio_dev);
  517. int ret;
  518. switch (mask) {
  519. case IIO_CHAN_INFO_SAMP_FREQ:
  520. mutex_lock(&data->mutex);
  521. /*
  522. * Section 4.2 of spec
  523. * In suspend mode, the only supported operations are reading
  524. * registers as well as writing to the (0x14) softreset
  525. * register. Since we will be in suspend mode by default, change
  526. * mode to power on for other writes.
  527. */
  528. ret = bmg160_set_power_state(data, true);
  529. if (ret < 0) {
  530. mutex_unlock(&data->mutex);
  531. return ret;
  532. }
  533. ret = bmg160_set_bw(data, val);
  534. if (ret < 0) {
  535. bmg160_set_power_state(data, false);
  536. mutex_unlock(&data->mutex);
  537. return ret;
  538. }
  539. ret = bmg160_set_power_state(data, false);
  540. mutex_unlock(&data->mutex);
  541. return ret;
  542. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  543. if (val2)
  544. return -EINVAL;
  545. mutex_lock(&data->mutex);
  546. ret = bmg160_set_power_state(data, true);
  547. if (ret < 0) {
  548. bmg160_set_power_state(data, false);
  549. mutex_unlock(&data->mutex);
  550. return ret;
  551. }
  552. ret = bmg160_set_filter(data, val);
  553. if (ret < 0) {
  554. bmg160_set_power_state(data, false);
  555. mutex_unlock(&data->mutex);
  556. return ret;
  557. }
  558. ret = bmg160_set_power_state(data, false);
  559. mutex_unlock(&data->mutex);
  560. return ret;
  561. case IIO_CHAN_INFO_SCALE:
  562. if (val)
  563. return -EINVAL;
  564. mutex_lock(&data->mutex);
  565. /* Refer to comments above for the suspend mode ops */
  566. ret = bmg160_set_power_state(data, true);
  567. if (ret < 0) {
  568. mutex_unlock(&data->mutex);
  569. return ret;
  570. }
  571. ret = bmg160_set_scale(data, val2);
  572. if (ret < 0) {
  573. bmg160_set_power_state(data, false);
  574. mutex_unlock(&data->mutex);
  575. return ret;
  576. }
  577. ret = bmg160_set_power_state(data, false);
  578. mutex_unlock(&data->mutex);
  579. return ret;
  580. default:
  581. return -EINVAL;
  582. }
  583. return -EINVAL;
  584. }
  585. static int bmg160_read_event(struct iio_dev *indio_dev,
  586. const struct iio_chan_spec *chan,
  587. enum iio_event_type type,
  588. enum iio_event_direction dir,
  589. enum iio_event_info info,
  590. int *val, int *val2)
  591. {
  592. struct bmg160_data *data = iio_priv(indio_dev);
  593. *val2 = 0;
  594. switch (info) {
  595. case IIO_EV_INFO_VALUE:
  596. *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
  597. break;
  598. default:
  599. return -EINVAL;
  600. }
  601. return IIO_VAL_INT;
  602. }
  603. static int bmg160_write_event(struct iio_dev *indio_dev,
  604. const struct iio_chan_spec *chan,
  605. enum iio_event_type type,
  606. enum iio_event_direction dir,
  607. enum iio_event_info info,
  608. int val, int val2)
  609. {
  610. struct bmg160_data *data = iio_priv(indio_dev);
  611. switch (info) {
  612. case IIO_EV_INFO_VALUE:
  613. if (data->ev_enable_state)
  614. return -EBUSY;
  615. data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
  616. data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
  617. break;
  618. default:
  619. return -EINVAL;
  620. }
  621. return 0;
  622. }
  623. static int bmg160_read_event_config(struct iio_dev *indio_dev,
  624. const struct iio_chan_spec *chan,
  625. enum iio_event_type type,
  626. enum iio_event_direction dir)
  627. {
  628. struct bmg160_data *data = iio_priv(indio_dev);
  629. return data->ev_enable_state;
  630. }
  631. static int bmg160_write_event_config(struct iio_dev *indio_dev,
  632. const struct iio_chan_spec *chan,
  633. enum iio_event_type type,
  634. enum iio_event_direction dir,
  635. int state)
  636. {
  637. struct bmg160_data *data = iio_priv(indio_dev);
  638. int ret;
  639. if (state && data->ev_enable_state)
  640. return 0;
  641. mutex_lock(&data->mutex);
  642. if (!state && data->motion_trigger_on) {
  643. data->ev_enable_state = 0;
  644. mutex_unlock(&data->mutex);
  645. return 0;
  646. }
  647. /*
  648. * We will expect the enable and disable to do operation in
  649. * in reverse order. This will happen here anyway as our
  650. * resume operation uses sync mode runtime pm calls, the
  651. * suspend operation will be delayed by autosuspend delay
  652. * So the disable operation will still happen in reverse of
  653. * enable operation. When runtime pm is disabled the mode
  654. * is always on so sequence doesn't matter
  655. */
  656. ret = bmg160_set_power_state(data, state);
  657. if (ret < 0) {
  658. mutex_unlock(&data->mutex);
  659. return ret;
  660. }
  661. ret = bmg160_setup_any_motion_interrupt(data, state);
  662. if (ret < 0) {
  663. bmg160_set_power_state(data, false);
  664. mutex_unlock(&data->mutex);
  665. return ret;
  666. }
  667. data->ev_enable_state = state;
  668. mutex_unlock(&data->mutex);
  669. return 0;
  670. }
  671. static const struct iio_mount_matrix *
  672. bmg160_get_mount_matrix(const struct iio_dev *indio_dev,
  673. const struct iio_chan_spec *chan)
  674. {
  675. struct bmg160_data *data = iio_priv(indio_dev);
  676. return &data->orientation;
  677. }
  678. static const struct iio_chan_spec_ext_info bmg160_ext_info[] = {
  679. IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix),
  680. { }
  681. };
  682. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
  683. static IIO_CONST_ATTR(in_anglvel_scale_available,
  684. "0.001065 0.000532 0.000266 0.000133 0.000066");
  685. static struct attribute *bmg160_attributes[] = {
  686. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  687. &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
  688. NULL,
  689. };
  690. static const struct attribute_group bmg160_attrs_group = {
  691. .attrs = bmg160_attributes,
  692. };
  693. static const struct iio_event_spec bmg160_event = {
  694. .type = IIO_EV_TYPE_ROC,
  695. .dir = IIO_EV_DIR_EITHER,
  696. .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
  697. BIT(IIO_EV_INFO_ENABLE)
  698. };
  699. #define BMG160_CHANNEL(_axis) { \
  700. .type = IIO_ANGL_VEL, \
  701. .modified = 1, \
  702. .channel2 = IIO_MOD_##_axis, \
  703. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  704. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  705. BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  706. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
  707. .scan_index = AXIS_##_axis, \
  708. .scan_type = { \
  709. .sign = 's', \
  710. .realbits = 16, \
  711. .storagebits = 16, \
  712. .endianness = IIO_LE, \
  713. }, \
  714. .ext_info = bmg160_ext_info, \
  715. .event_spec = &bmg160_event, \
  716. .num_event_specs = 1 \
  717. }
  718. static const struct iio_chan_spec bmg160_channels[] = {
  719. {
  720. .type = IIO_TEMP,
  721. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  722. BIT(IIO_CHAN_INFO_SCALE) |
  723. BIT(IIO_CHAN_INFO_OFFSET),
  724. .scan_index = -1,
  725. },
  726. BMG160_CHANNEL(X),
  727. BMG160_CHANNEL(Y),
  728. BMG160_CHANNEL(Z),
  729. IIO_CHAN_SOFT_TIMESTAMP(3),
  730. };
  731. static const struct iio_info bmg160_info = {
  732. .attrs = &bmg160_attrs_group,
  733. .read_raw = bmg160_read_raw,
  734. .write_raw = bmg160_write_raw,
  735. .read_event_value = bmg160_read_event,
  736. .write_event_value = bmg160_write_event,
  737. .write_event_config = bmg160_write_event_config,
  738. .read_event_config = bmg160_read_event_config,
  739. };
  740. static const unsigned long bmg160_accel_scan_masks[] = {
  741. BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
  742. 0};
  743. static irqreturn_t bmg160_trigger_handler(int irq, void *p)
  744. {
  745. struct iio_poll_func *pf = p;
  746. struct iio_dev *indio_dev = pf->indio_dev;
  747. struct bmg160_data *data = iio_priv(indio_dev);
  748. int ret;
  749. mutex_lock(&data->mutex);
  750. ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
  751. data->scan.chans, AXIS_MAX * 2);
  752. mutex_unlock(&data->mutex);
  753. if (ret < 0)
  754. goto err;
  755. iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
  756. pf->timestamp);
  757. err:
  758. iio_trigger_notify_done(indio_dev->trig);
  759. return IRQ_HANDLED;
  760. }
  761. static int bmg160_trig_try_reen(struct iio_trigger *trig)
  762. {
  763. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  764. struct bmg160_data *data = iio_priv(indio_dev);
  765. struct device *dev = regmap_get_device(data->regmap);
  766. int ret;
  767. /* new data interrupts don't need ack */
  768. if (data->dready_trigger_on)
  769. return 0;
  770. /* Set latched mode interrupt and clear any latched interrupt */
  771. ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
  772. BMG160_INT_MODE_LATCH_INT |
  773. BMG160_INT_MODE_LATCH_RESET);
  774. if (ret < 0) {
  775. dev_err(dev, "Error writing reg_rst_latch\n");
  776. return ret;
  777. }
  778. return 0;
  779. }
  780. static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
  781. bool state)
  782. {
  783. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  784. struct bmg160_data *data = iio_priv(indio_dev);
  785. int ret;
  786. mutex_lock(&data->mutex);
  787. if (!state && data->ev_enable_state && data->motion_trigger_on) {
  788. data->motion_trigger_on = false;
  789. mutex_unlock(&data->mutex);
  790. return 0;
  791. }
  792. /*
  793. * Refer to comment in bmg160_write_event_config for
  794. * enable/disable operation order
  795. */
  796. ret = bmg160_set_power_state(data, state);
  797. if (ret < 0) {
  798. mutex_unlock(&data->mutex);
  799. return ret;
  800. }
  801. if (data->motion_trig == trig)
  802. ret = bmg160_setup_any_motion_interrupt(data, state);
  803. else
  804. ret = bmg160_setup_new_data_interrupt(data, state);
  805. if (ret < 0) {
  806. bmg160_set_power_state(data, false);
  807. mutex_unlock(&data->mutex);
  808. return ret;
  809. }
  810. if (data->motion_trig == trig)
  811. data->motion_trigger_on = state;
  812. else
  813. data->dready_trigger_on = state;
  814. mutex_unlock(&data->mutex);
  815. return 0;
  816. }
  817. static const struct iio_trigger_ops bmg160_trigger_ops = {
  818. .set_trigger_state = bmg160_data_rdy_trigger_set_state,
  819. .try_reenable = bmg160_trig_try_reen,
  820. };
  821. static irqreturn_t bmg160_event_handler(int irq, void *private)
  822. {
  823. struct iio_dev *indio_dev = private;
  824. struct bmg160_data *data = iio_priv(indio_dev);
  825. struct device *dev = regmap_get_device(data->regmap);
  826. int ret;
  827. int dir;
  828. unsigned int val;
  829. ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
  830. if (ret < 0) {
  831. dev_err(dev, "Error reading reg_int_status2\n");
  832. goto ack_intr_status;
  833. }
  834. if (val & 0x08)
  835. dir = IIO_EV_DIR_RISING;
  836. else
  837. dir = IIO_EV_DIR_FALLING;
  838. if (val & BMG160_ANY_MOTION_BIT_X)
  839. iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
  840. 0,
  841. IIO_MOD_X,
  842. IIO_EV_TYPE_ROC,
  843. dir),
  844. iio_get_time_ns(indio_dev));
  845. if (val & BMG160_ANY_MOTION_BIT_Y)
  846. iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
  847. 0,
  848. IIO_MOD_Y,
  849. IIO_EV_TYPE_ROC,
  850. dir),
  851. iio_get_time_ns(indio_dev));
  852. if (val & BMG160_ANY_MOTION_BIT_Z)
  853. iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
  854. 0,
  855. IIO_MOD_Z,
  856. IIO_EV_TYPE_ROC,
  857. dir),
  858. iio_get_time_ns(indio_dev));
  859. ack_intr_status:
  860. if (!data->dready_trigger_on) {
  861. ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
  862. BMG160_INT_MODE_LATCH_INT |
  863. BMG160_INT_MODE_LATCH_RESET);
  864. if (ret < 0)
  865. dev_err(dev, "Error writing reg_rst_latch\n");
  866. }
  867. return IRQ_HANDLED;
  868. }
  869. static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
  870. {
  871. struct iio_dev *indio_dev = private;
  872. struct bmg160_data *data = iio_priv(indio_dev);
  873. if (data->dready_trigger_on)
  874. iio_trigger_poll(data->dready_trig);
  875. else if (data->motion_trigger_on)
  876. iio_trigger_poll(data->motion_trig);
  877. if (data->ev_enable_state)
  878. return IRQ_WAKE_THREAD;
  879. else
  880. return IRQ_HANDLED;
  881. }
  882. static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
  883. {
  884. struct bmg160_data *data = iio_priv(indio_dev);
  885. return bmg160_set_power_state(data, true);
  886. }
  887. static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
  888. {
  889. struct bmg160_data *data = iio_priv(indio_dev);
  890. return bmg160_set_power_state(data, false);
  891. }
  892. static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
  893. .preenable = bmg160_buffer_preenable,
  894. .postdisable = bmg160_buffer_postdisable,
  895. };
  896. static const char *bmg160_match_acpi_device(struct device *dev)
  897. {
  898. const struct acpi_device_id *id;
  899. id = acpi_match_device(dev->driver->acpi_match_table, dev);
  900. if (!id)
  901. return NULL;
  902. return dev_name(dev);
  903. }
  904. int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
  905. const char *name)
  906. {
  907. struct bmg160_data *data;
  908. struct iio_dev *indio_dev;
  909. int ret;
  910. indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
  911. if (!indio_dev)
  912. return -ENOMEM;
  913. data = iio_priv(indio_dev);
  914. dev_set_drvdata(dev, indio_dev);
  915. data->irq = irq;
  916. data->regmap = regmap;
  917. ret = iio_read_mount_matrix(dev, "mount-matrix",
  918. &data->orientation);
  919. if (ret)
  920. return ret;
  921. ret = bmg160_chip_init(data);
  922. if (ret < 0)
  923. return ret;
  924. mutex_init(&data->mutex);
  925. if (ACPI_HANDLE(dev))
  926. name = bmg160_match_acpi_device(dev);
  927. indio_dev->channels = bmg160_channels;
  928. indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
  929. indio_dev->name = name;
  930. indio_dev->available_scan_masks = bmg160_accel_scan_masks;
  931. indio_dev->modes = INDIO_DIRECT_MODE;
  932. indio_dev->info = &bmg160_info;
  933. if (data->irq > 0) {
  934. ret = devm_request_threaded_irq(dev,
  935. data->irq,
  936. bmg160_data_rdy_trig_poll,
  937. bmg160_event_handler,
  938. IRQF_TRIGGER_RISING,
  939. BMG160_IRQ_NAME,
  940. indio_dev);
  941. if (ret)
  942. return ret;
  943. data->dready_trig = devm_iio_trigger_alloc(dev,
  944. "%s-dev%d",
  945. indio_dev->name,
  946. indio_dev->id);
  947. if (!data->dready_trig)
  948. return -ENOMEM;
  949. data->motion_trig = devm_iio_trigger_alloc(dev,
  950. "%s-any-motion-dev%d",
  951. indio_dev->name,
  952. indio_dev->id);
  953. if (!data->motion_trig)
  954. return -ENOMEM;
  955. data->dready_trig->dev.parent = dev;
  956. data->dready_trig->ops = &bmg160_trigger_ops;
  957. iio_trigger_set_drvdata(data->dready_trig, indio_dev);
  958. ret = iio_trigger_register(data->dready_trig);
  959. if (ret)
  960. return ret;
  961. data->motion_trig->dev.parent = dev;
  962. data->motion_trig->ops = &bmg160_trigger_ops;
  963. iio_trigger_set_drvdata(data->motion_trig, indio_dev);
  964. ret = iio_trigger_register(data->motion_trig);
  965. if (ret) {
  966. data->motion_trig = NULL;
  967. goto err_trigger_unregister;
  968. }
  969. }
  970. ret = iio_triggered_buffer_setup(indio_dev,
  971. iio_pollfunc_store_time,
  972. bmg160_trigger_handler,
  973. &bmg160_buffer_setup_ops);
  974. if (ret < 0) {
  975. dev_err(dev,
  976. "iio triggered buffer setup failed\n");
  977. goto err_trigger_unregister;
  978. }
  979. ret = pm_runtime_set_active(dev);
  980. if (ret)
  981. goto err_buffer_cleanup;
  982. pm_runtime_enable(dev);
  983. pm_runtime_set_autosuspend_delay(dev,
  984. BMG160_AUTO_SUSPEND_DELAY_MS);
  985. pm_runtime_use_autosuspend(dev);
  986. ret = iio_device_register(indio_dev);
  987. if (ret < 0) {
  988. dev_err(dev, "unable to register iio device\n");
  989. goto err_pm_cleanup;
  990. }
  991. return 0;
  992. err_pm_cleanup:
  993. pm_runtime_dont_use_autosuspend(dev);
  994. pm_runtime_disable(dev);
  995. err_buffer_cleanup:
  996. iio_triggered_buffer_cleanup(indio_dev);
  997. err_trigger_unregister:
  998. if (data->dready_trig)
  999. iio_trigger_unregister(data->dready_trig);
  1000. if (data->motion_trig)
  1001. iio_trigger_unregister(data->motion_trig);
  1002. return ret;
  1003. }
  1004. EXPORT_SYMBOL_GPL(bmg160_core_probe);
  1005. void bmg160_core_remove(struct device *dev)
  1006. {
  1007. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1008. struct bmg160_data *data = iio_priv(indio_dev);
  1009. iio_device_unregister(indio_dev);
  1010. pm_runtime_disable(dev);
  1011. pm_runtime_set_suspended(dev);
  1012. pm_runtime_put_noidle(dev);
  1013. iio_triggered_buffer_cleanup(indio_dev);
  1014. if (data->dready_trig) {
  1015. iio_trigger_unregister(data->dready_trig);
  1016. iio_trigger_unregister(data->motion_trig);
  1017. }
  1018. mutex_lock(&data->mutex);
  1019. bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
  1020. mutex_unlock(&data->mutex);
  1021. }
  1022. EXPORT_SYMBOL_GPL(bmg160_core_remove);
  1023. #ifdef CONFIG_PM_SLEEP
  1024. static int bmg160_suspend(struct device *dev)
  1025. {
  1026. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1027. struct bmg160_data *data = iio_priv(indio_dev);
  1028. mutex_lock(&data->mutex);
  1029. bmg160_set_mode(data, BMG160_MODE_SUSPEND);
  1030. mutex_unlock(&data->mutex);
  1031. return 0;
  1032. }
  1033. static int bmg160_resume(struct device *dev)
  1034. {
  1035. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1036. struct bmg160_data *data = iio_priv(indio_dev);
  1037. mutex_lock(&data->mutex);
  1038. if (data->dready_trigger_on || data->motion_trigger_on ||
  1039. data->ev_enable_state)
  1040. bmg160_set_mode(data, BMG160_MODE_NORMAL);
  1041. mutex_unlock(&data->mutex);
  1042. return 0;
  1043. }
  1044. #endif
  1045. #ifdef CONFIG_PM
  1046. static int bmg160_runtime_suspend(struct device *dev)
  1047. {
  1048. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1049. struct bmg160_data *data = iio_priv(indio_dev);
  1050. int ret;
  1051. ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
  1052. if (ret < 0) {
  1053. dev_err(dev, "set mode failed\n");
  1054. return -EAGAIN;
  1055. }
  1056. return 0;
  1057. }
  1058. static int bmg160_runtime_resume(struct device *dev)
  1059. {
  1060. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1061. struct bmg160_data *data = iio_priv(indio_dev);
  1062. int ret;
  1063. ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
  1064. if (ret < 0)
  1065. return ret;
  1066. msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
  1067. return 0;
  1068. }
  1069. #endif
  1070. const struct dev_pm_ops bmg160_pm_ops = {
  1071. SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
  1072. SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
  1073. bmg160_runtime_resume, NULL)
  1074. };
  1075. EXPORT_SYMBOL_GPL(bmg160_pm_ops);
  1076. MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
  1077. MODULE_LICENSE("GPL v2");
  1078. MODULE_DESCRIPTION("BMG160 Gyro driver");