via82cxxx.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * VIA IDE driver for Linux. Supported southbridges:
  4. *
  5. * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
  6. * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
  7. * vt8235, vt8237, vt8237a
  8. *
  9. * Copyright (c) 2000-2002 Vojtech Pavlik
  10. * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
  11. *
  12. * Based on the work of:
  13. * Michel Aubry
  14. * Jeff Garzik
  15. * Andre Hedrick
  16. *
  17. * Documentation:
  18. * Obsolete device documentation publicly available from via.com.tw
  19. * Current device documentation available under NDA only
  20. */
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/slab.h>
  24. #include <linux/pci.h>
  25. #include <linux/init.h>
  26. #include <linux/ide.h>
  27. #include <linux/dmi.h>
  28. #ifdef CONFIG_PPC_CHRP
  29. #include <asm/processor.h>
  30. #endif
  31. #define DRV_NAME "via82cxxx"
  32. #define VIA_IDE_ENABLE 0x40
  33. #define VIA_IDE_CONFIG 0x41
  34. #define VIA_FIFO_CONFIG 0x43
  35. #define VIA_MISC_1 0x44
  36. #define VIA_MISC_2 0x45
  37. #define VIA_MISC_3 0x46
  38. #define VIA_DRIVE_TIMING 0x48
  39. #define VIA_8BIT_TIMING 0x4e
  40. #define VIA_ADDRESS_SETUP 0x4c
  41. #define VIA_UDMA_TIMING 0x50
  42. #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
  43. #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
  44. #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
  45. #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
  46. #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
  47. #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
  48. #define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
  49. enum {
  50. VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
  51. };
  52. /*
  53. * VIA SouthBridge chips.
  54. */
  55. static struct via_isa_bridge {
  56. char *name;
  57. u16 id;
  58. u8 rev_min;
  59. u8 rev_max;
  60. u8 udma_mask;
  61. u8 flags;
  62. } via_isa_bridges[] = {
  63. { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  64. { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  65. { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  66. { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  67. { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  68. { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  69. { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
  70. { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  71. { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  72. { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  73. { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  74. { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  75. { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
  76. { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
  77. { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
  78. { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
  79. { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
  80. { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
  81. { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
  82. { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
  83. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
  84. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
  85. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
  86. { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
  87. { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
  88. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
  89. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
  90. { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  91. { NULL }
  92. };
  93. static unsigned int via_clock;
  94. static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
  95. struct via82cxxx_dev
  96. {
  97. struct via_isa_bridge *via_config;
  98. unsigned int via_80w;
  99. };
  100. /**
  101. * via_set_speed - write timing registers
  102. * @dev: PCI device
  103. * @dn: device
  104. * @timing: IDE timing data to use
  105. *
  106. * via_set_speed writes timing values to the chipset registers
  107. */
  108. static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
  109. {
  110. struct pci_dev *dev = to_pci_dev(hwif->dev);
  111. struct ide_host *host = pci_get_drvdata(dev);
  112. struct via82cxxx_dev *vdev = host->host_priv;
  113. u8 t;
  114. if (~vdev->via_config->flags & VIA_BAD_AST) {
  115. pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
  116. t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
  117. pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
  118. }
  119. pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
  120. ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
  121. pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
  122. ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
  123. switch (vdev->via_config->udma_mask) {
  124. case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
  125. case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
  126. case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
  127. case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
  128. }
  129. /* Set UDMA unless device is not UDMA capable */
  130. if (vdev->via_config->udma_mask) {
  131. u8 udma_etc;
  132. pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);
  133. /* clear transfer mode bit */
  134. udma_etc &= ~0x20;
  135. if (timing->udma) {
  136. /* preserve 80-wire cable detection bit */
  137. udma_etc &= 0x10;
  138. udma_etc |= t;
  139. }
  140. pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
  141. }
  142. }
  143. /**
  144. * via_set_drive - configure transfer mode
  145. * @hwif: port
  146. * @drive: Drive to set up
  147. *
  148. * via_set_drive() computes timing values configures the chipset to
  149. * a desired transfer mode. It also can be called by upper layers.
  150. */
  151. static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
  152. {
  153. ide_drive_t *peer = ide_get_pair_dev(drive);
  154. struct ide_host *host = dev_get_drvdata(hwif->dev);
  155. struct via82cxxx_dev *vdev = host->host_priv;
  156. struct ide_timing t, p;
  157. unsigned int T, UT;
  158. const u8 speed = drive->dma_mode;
  159. T = 1000000000 / via_clock;
  160. switch (vdev->via_config->udma_mask) {
  161. case ATA_UDMA2: UT = T; break;
  162. case ATA_UDMA4: UT = T/2; break;
  163. case ATA_UDMA5: UT = T/3; break;
  164. case ATA_UDMA6: UT = T/4; break;
  165. default: UT = T;
  166. }
  167. ide_timing_compute(drive, speed, &t, T, UT);
  168. if (peer) {
  169. ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
  170. ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
  171. }
  172. via_set_speed(hwif, drive->dn, &t);
  173. }
  174. /**
  175. * via_set_pio_mode - set host controller for PIO mode
  176. * @hwif: port
  177. * @drive: drive
  178. *
  179. * A callback from the upper layers for PIO-only tuning.
  180. */
  181. static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  182. {
  183. drive->dma_mode = drive->pio_mode;
  184. via_set_drive(hwif, drive);
  185. }
  186. static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
  187. {
  188. struct via_isa_bridge *via_config;
  189. for (via_config = via_isa_bridges;
  190. via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
  191. if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
  192. !!(via_config->flags & VIA_BAD_ID),
  193. via_config->id, NULL))) {
  194. if ((*isa)->revision >= via_config->rev_min &&
  195. (*isa)->revision <= via_config->rev_max)
  196. break;
  197. pci_dev_put(*isa);
  198. }
  199. return via_config;
  200. }
  201. /*
  202. * Check and handle 80-wire cable presence
  203. */
  204. static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
  205. {
  206. int i;
  207. switch (vdev->via_config->udma_mask) {
  208. case ATA_UDMA4:
  209. for (i = 24; i >= 0; i -= 8)
  210. if (((u >> (i & 16)) & 8) &&
  211. ((u >> i) & 0x20) &&
  212. (((u >> i) & 7) < 2)) {
  213. /*
  214. * 2x PCI clock and
  215. * UDMA w/ < 3T/cycle
  216. */
  217. vdev->via_80w |= (1 << (1 - (i >> 4)));
  218. }
  219. break;
  220. case ATA_UDMA5:
  221. for (i = 24; i >= 0; i -= 8)
  222. if (((u >> i) & 0x10) ||
  223. (((u >> i) & 0x20) &&
  224. (((u >> i) & 7) < 4))) {
  225. /* BIOS 80-wire bit or
  226. * UDMA w/ < 60ns/cycle
  227. */
  228. vdev->via_80w |= (1 << (1 - (i >> 4)));
  229. }
  230. break;
  231. case ATA_UDMA6:
  232. for (i = 24; i >= 0; i -= 8)
  233. if (((u >> i) & 0x10) ||
  234. (((u >> i) & 0x20) &&
  235. (((u >> i) & 7) < 6))) {
  236. /* BIOS 80-wire bit or
  237. * UDMA w/ < 60ns/cycle
  238. */
  239. vdev->via_80w |= (1 << (1 - (i >> 4)));
  240. }
  241. break;
  242. }
  243. }
  244. /**
  245. * init_chipset_via82cxxx - initialization handler
  246. * @dev: PCI device
  247. *
  248. * The initialization callback. Here we determine the IDE chip type
  249. * and initialize its drive independent registers.
  250. */
  251. static int init_chipset_via82cxxx(struct pci_dev *dev)
  252. {
  253. struct ide_host *host = pci_get_drvdata(dev);
  254. struct via82cxxx_dev *vdev = host->host_priv;
  255. struct via_isa_bridge *via_config = vdev->via_config;
  256. u8 t, v;
  257. u32 u;
  258. /*
  259. * Detect cable and configure Clk66
  260. */
  261. pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
  262. via_cable_detect(vdev, u);
  263. if (via_config->udma_mask == ATA_UDMA4) {
  264. /* Enable Clk66 */
  265. pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
  266. } else if (via_config->flags & VIA_BAD_CLK66) {
  267. /* Would cause trouble on 596a and 686 */
  268. pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
  269. }
  270. /*
  271. * Check whether interfaces are enabled.
  272. */
  273. pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
  274. /*
  275. * Set up FIFO sizes and thresholds.
  276. */
  277. pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
  278. /* Disable PREQ# till DDACK# */
  279. if (via_config->flags & VIA_BAD_PREQ) {
  280. /* Would crash on 586b rev 41 */
  281. t &= 0x7f;
  282. }
  283. /* Fix FIFO split between channels */
  284. if (via_config->flags & VIA_SET_FIFO) {
  285. t &= (t & 0x9f);
  286. switch (v & 3) {
  287. case 2: t |= 0x00; break; /* 16 on primary */
  288. case 1: t |= 0x60; break; /* 16 on secondary */
  289. case 3: t |= 0x20; break; /* 8 pri 8 sec */
  290. }
  291. }
  292. pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
  293. return 0;
  294. }
  295. /*
  296. * Cable special cases
  297. */
  298. static const struct dmi_system_id cable_dmi_table[] = {
  299. {
  300. .ident = "Acer Ferrari 3400",
  301. .matches = {
  302. DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
  303. DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
  304. },
  305. },
  306. { }
  307. };
  308. static int via_cable_override(struct pci_dev *pdev)
  309. {
  310. /* Systems by DMI */
  311. if (dmi_check_system(cable_dmi_table))
  312. return 1;
  313. /* Arima W730-K8/Targa Visionary 811/... */
  314. if (pdev->subsystem_vendor == 0x161F &&
  315. pdev->subsystem_device == 0x2032)
  316. return 1;
  317. return 0;
  318. }
  319. static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
  320. {
  321. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  322. struct ide_host *host = pci_get_drvdata(pdev);
  323. struct via82cxxx_dev *vdev = host->host_priv;
  324. if (via_cable_override(pdev))
  325. return ATA_CBL_PATA40_SHORT;
  326. if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
  327. return ATA_CBL_SATA;
  328. if ((vdev->via_80w >> hwif->channel) & 1)
  329. return ATA_CBL_PATA80;
  330. else
  331. return ATA_CBL_PATA40;
  332. }
  333. static const struct ide_port_ops via_port_ops = {
  334. .set_pio_mode = via_set_pio_mode,
  335. .set_dma_mode = via_set_drive,
  336. .cable_detect = via82cxxx_cable_detect,
  337. };
  338. static const struct ide_port_info via82cxxx_chipset = {
  339. .name = DRV_NAME,
  340. .init_chipset = init_chipset_via82cxxx,
  341. .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
  342. .port_ops = &via_port_ops,
  343. .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
  344. IDE_HFLAG_POST_SET_MODE |
  345. IDE_HFLAG_IO_32BIT,
  346. .pio_mask = ATA_PIO5,
  347. .swdma_mask = ATA_SWDMA2,
  348. .mwdma_mask = ATA_MWDMA2,
  349. };
  350. static int via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  351. {
  352. struct pci_dev *isa = NULL;
  353. struct via_isa_bridge *via_config;
  354. struct via82cxxx_dev *vdev;
  355. int rc;
  356. u8 idx = id->driver_data;
  357. struct ide_port_info d;
  358. d = via82cxxx_chipset;
  359. /*
  360. * Find the ISA bridge and check we know what it is.
  361. */
  362. via_config = via_config_find(&isa);
  363. /*
  364. * Print the boot message.
  365. */
  366. printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
  367. pci_name(dev), via_config->name, isa->revision,
  368. via_config->udma_mask ? "U" : "MW",
  369. via_dma[via_config->udma_mask ?
  370. (fls(via_config->udma_mask) - 1) : 0]);
  371. pci_dev_put(isa);
  372. /*
  373. * Determine system bus clock.
  374. */
  375. via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
  376. switch (via_clock) {
  377. case 33000: via_clock = 33333; break;
  378. case 37000: via_clock = 37500; break;
  379. case 41000: via_clock = 41666; break;
  380. }
  381. if (via_clock < 20000 || via_clock > 50000) {
  382. printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
  383. "impossible (%d), using 33 MHz instead.\n", via_clock);
  384. via_clock = 33333;
  385. }
  386. if (idx == 1)
  387. d.enablebits[1].reg = d.enablebits[0].reg = 0;
  388. else
  389. d.host_flags |= IDE_HFLAG_NO_AUTODMA;
  390. if (idx == VIA_IDFLAG_SINGLE)
  391. d.host_flags |= IDE_HFLAG_SINGLE;
  392. if ((via_config->flags & VIA_NO_UNMASK) == 0)
  393. d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
  394. d.udma_mask = via_config->udma_mask;
  395. vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
  396. if (!vdev) {
  397. printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
  398. pci_name(dev));
  399. return -ENOMEM;
  400. }
  401. vdev->via_config = via_config;
  402. rc = ide_pci_init_one(dev, &d, vdev);
  403. if (rc)
  404. kfree(vdev);
  405. return rc;
  406. }
  407. static void via_remove(struct pci_dev *dev)
  408. {
  409. struct ide_host *host = pci_get_drvdata(dev);
  410. struct via82cxxx_dev *vdev = host->host_priv;
  411. ide_pci_remove(dev);
  412. kfree(vdev);
  413. }
  414. static const struct pci_device_id via_pci_tbl[] = {
  415. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
  416. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
  417. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
  418. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
  419. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
  420. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
  421. { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
  422. { 0, },
  423. };
  424. MODULE_DEVICE_TABLE(pci, via_pci_tbl);
  425. static struct pci_driver via_pci_driver = {
  426. .name = "VIA_IDE",
  427. .id_table = via_pci_tbl,
  428. .probe = via_init_one,
  429. .remove = via_remove,
  430. .suspend = ide_pci_suspend,
  431. .resume = ide_pci_resume,
  432. };
  433. static int __init via_ide_init(void)
  434. {
  435. return ide_pci_register_driver(&via_pci_driver);
  436. }
  437. static void __exit via_ide_exit(void)
  438. {
  439. pci_unregister_driver(&via_pci_driver);
  440. }
  441. module_init(via_ide_init);
  442. module_exit(via_ide_exit);
  443. MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
  444. MODULE_DESCRIPTION("PCI driver module for VIA IDE");
  445. MODULE_LICENSE("GPL");