tx4939ide.c 17 KB

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  1. /*
  2. * TX4939 internal IDE driver
  3. * Based on RBTX49xx patch from CELF patch archive.
  4. *
  5. * This file is subject to the terms and conditions of the GNU General Public
  6. * License. See the file "COPYING" in the main directory of this archive
  7. * for more details.
  8. *
  9. * (C) Copyright TOSHIBA CORPORATION 2005-2007
  10. */
  11. #include <linux/module.h>
  12. #include <linux/types.h>
  13. #include <linux/ide.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/io.h>
  18. #include <linux/scatterlist.h>
  19. #include <asm/ide.h>
  20. #define MODNAME "tx4939ide"
  21. /* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
  22. #define TX4939IDE_Data 0x000
  23. #define TX4939IDE_Error_Feature 0x001
  24. #define TX4939IDE_Sec 0x002
  25. #define TX4939IDE_LBA0 0x003
  26. #define TX4939IDE_LBA1 0x004
  27. #define TX4939IDE_LBA2 0x005
  28. #define TX4939IDE_DevHead 0x006
  29. #define TX4939IDE_Stat_Cmd 0x007
  30. #define TX4939IDE_AltStat_DevCtl 0x402
  31. /* H/W DMA Registers */
  32. #define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */
  33. #define TX4939IDE_DMA_Stat 0x802 /* 8-bit */
  34. #define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */
  35. /* ATA100 CORE Registers (16-bit) */
  36. #define TX4939IDE_Sys_Ctl 0xc00
  37. #define TX4939IDE_Xfer_Cnt_1 0xc08
  38. #define TX4939IDE_Xfer_Cnt_2 0xc0a
  39. #define TX4939IDE_Sec_Cnt 0xc10
  40. #define TX4939IDE_Start_Lo_Addr 0xc18
  41. #define TX4939IDE_Start_Up_Addr 0xc20
  42. #define TX4939IDE_Add_Ctl 0xc28
  43. #define TX4939IDE_Lo_Burst_Cnt 0xc30
  44. #define TX4939IDE_Up_Burst_Cnt 0xc38
  45. #define TX4939IDE_PIO_Addr 0xc88
  46. #define TX4939IDE_H_Rst_Tim 0xc90
  47. #define TX4939IDE_Int_Ctl 0xc98
  48. #define TX4939IDE_Pkt_Cmd 0xcb8
  49. #define TX4939IDE_Bxfer_Cnt_Hi 0xcc0
  50. #define TX4939IDE_Bxfer_Cnt_Lo 0xcc8
  51. #define TX4939IDE_Dev_TErr 0xcd0
  52. #define TX4939IDE_Pkt_Xfer_Ctl 0xcd8
  53. #define TX4939IDE_Start_TAddr 0xce0
  54. /* bits for Int_Ctl */
  55. #define TX4939IDE_INT_ADDRERR 0x80
  56. #define TX4939IDE_INT_REACHMUL 0x40
  57. #define TX4939IDE_INT_DEVTIMING 0x20
  58. #define TX4939IDE_INT_UDMATERM 0x10
  59. #define TX4939IDE_INT_TIMER 0x08
  60. #define TX4939IDE_INT_BUSERR 0x04
  61. #define TX4939IDE_INT_XFEREND 0x02
  62. #define TX4939IDE_INT_HOST 0x01
  63. #define TX4939IDE_IGNORE_INTS \
  64. (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
  65. TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
  66. TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
  67. #ifdef __BIG_ENDIAN
  68. #define tx4939ide_swizzlel(a) ((a) ^ 4)
  69. #define tx4939ide_swizzlew(a) ((a) ^ 6)
  70. #define tx4939ide_swizzleb(a) ((a) ^ 7)
  71. #else
  72. #define tx4939ide_swizzlel(a) (a)
  73. #define tx4939ide_swizzlew(a) (a)
  74. #define tx4939ide_swizzleb(a) (a)
  75. #endif
  76. static u16 tx4939ide_readw(void __iomem *base, u32 reg)
  77. {
  78. return __raw_readw(base + tx4939ide_swizzlew(reg));
  79. }
  80. static u8 tx4939ide_readb(void __iomem *base, u32 reg)
  81. {
  82. return __raw_readb(base + tx4939ide_swizzleb(reg));
  83. }
  84. static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
  85. {
  86. __raw_writel(val, base + tx4939ide_swizzlel(reg));
  87. }
  88. static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
  89. {
  90. __raw_writew(val, base + tx4939ide_swizzlew(reg));
  91. }
  92. static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
  93. {
  94. __raw_writeb(val, base + tx4939ide_swizzleb(reg));
  95. }
  96. #define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
  97. static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  98. {
  99. int is_slave = drive->dn;
  100. u32 mask, val;
  101. const u8 pio = drive->pio_mode - XFER_PIO_0;
  102. u8 safe = pio;
  103. ide_drive_t *pair;
  104. pair = ide_get_pair_dev(drive);
  105. if (pair)
  106. safe = min_t(u8, safe, pair->pio_mode - XFER_PIO_0);
  107. /*
  108. * Update Command Transfer Mode for master/slave and Data
  109. * Transfer Mode for this drive.
  110. */
  111. mask = is_slave ? 0x07f00000 : 0x000007f0;
  112. val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
  113. hwif->select_data = (hwif->select_data & ~mask) | val;
  114. /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
  115. }
  116. static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  117. {
  118. u32 mask, val;
  119. const u8 mode = drive->dma_mode;
  120. /* Update Data Transfer Mode for this drive. */
  121. if (mode >= XFER_UDMA_0)
  122. val = mode - XFER_UDMA_0 + 8;
  123. else
  124. val = mode - XFER_MW_DMA_0 + 5;
  125. if (drive->dn) {
  126. mask = 0x00f00000;
  127. val <<= 20;
  128. } else {
  129. mask = 0x000000f0;
  130. val <<= 4;
  131. }
  132. hwif->select_data = (hwif->select_data & ~mask) | val;
  133. /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
  134. }
  135. static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
  136. {
  137. void __iomem *base = TX4939IDE_BASE(hwif);
  138. u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
  139. if (ctl & TX4939IDE_INT_BUSERR) {
  140. /* reset FIFO */
  141. u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
  142. tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
  143. /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
  144. ndelay(270);
  145. tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
  146. }
  147. if (ctl & (TX4939IDE_INT_ADDRERR |
  148. TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
  149. pr_err("%s: Error interrupt %#x (%s%s%s )\n",
  150. hwif->name, ctl,
  151. ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
  152. ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
  153. ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
  154. return ctl;
  155. }
  156. static void tx4939ide_clear_irq(ide_drive_t *drive)
  157. {
  158. ide_hwif_t *hwif;
  159. void __iomem *base;
  160. u16 ctl;
  161. /*
  162. * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
  163. * for DMA case.
  164. */
  165. if (drive->waiting_for_dma)
  166. return;
  167. hwif = drive->hwif;
  168. base = TX4939IDE_BASE(hwif);
  169. ctl = tx4939ide_check_error_ints(hwif);
  170. tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
  171. }
  172. static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
  173. {
  174. void __iomem *base = TX4939IDE_BASE(hwif);
  175. return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
  176. ATA_CBL_PATA40 : ATA_CBL_PATA80;
  177. }
  178. #ifdef __BIG_ENDIAN
  179. static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
  180. {
  181. ide_hwif_t *hwif = drive->hwif;
  182. u8 unit = drive->dn;
  183. void __iomem *base = TX4939IDE_BASE(hwif);
  184. u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
  185. if (on)
  186. dma_stat |= (1 << (5 + unit));
  187. else
  188. dma_stat &= ~(1 << (5 + unit));
  189. tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
  190. }
  191. #else
  192. #define tx4939ide_dma_host_set ide_dma_host_set
  193. #endif
  194. static u8 tx4939ide_clear_dma_status(void __iomem *base)
  195. {
  196. u8 dma_stat;
  197. /* read DMA status for INTR & ERROR flags */
  198. dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
  199. /* clear INTR & ERROR flags */
  200. tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
  201. TX4939IDE_DMA_Stat);
  202. /* recover intmask cleared by writing to bit2 of DMA_Stat */
  203. tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
  204. return dma_stat;
  205. }
  206. #ifdef __BIG_ENDIAN
  207. /* custom ide_build_dmatable to handle swapped layout */
  208. static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
  209. {
  210. ide_hwif_t *hwif = drive->hwif;
  211. u32 *table = (u32 *)hwif->dmatable_cpu;
  212. unsigned int count = 0;
  213. int i;
  214. struct scatterlist *sg;
  215. for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
  216. u32 cur_addr, cur_len, bcount;
  217. cur_addr = sg_dma_address(sg);
  218. cur_len = sg_dma_len(sg);
  219. /*
  220. * Fill in the DMA table, without crossing any 64kB boundaries.
  221. */
  222. while (cur_len) {
  223. if (count++ >= PRD_ENTRIES)
  224. goto use_pio_instead;
  225. bcount = 0x10000 - (cur_addr & 0xffff);
  226. if (bcount > cur_len)
  227. bcount = cur_len;
  228. /*
  229. * This workaround for zero count seems required.
  230. * (standard ide_build_dmatable does it too)
  231. */
  232. if (bcount == 0x10000)
  233. bcount = 0x8000;
  234. *table++ = bcount & 0xffff;
  235. *table++ = cur_addr;
  236. cur_addr += bcount;
  237. cur_len -= bcount;
  238. }
  239. }
  240. if (count) {
  241. *(table - 2) |= 0x80000000;
  242. return count;
  243. }
  244. use_pio_instead:
  245. printk(KERN_ERR "%s: %s\n", drive->name,
  246. count ? "DMA table too small" : "empty DMA table?");
  247. return 0; /* revert to PIO for this request */
  248. }
  249. #else
  250. #define tx4939ide_build_dmatable ide_build_dmatable
  251. #endif
  252. static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
  253. {
  254. ide_hwif_t *hwif = drive->hwif;
  255. void __iomem *base = TX4939IDE_BASE(hwif);
  256. u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
  257. /* fall back to PIO! */
  258. if (tx4939ide_build_dmatable(drive, cmd) == 0)
  259. return 1;
  260. /* PRD table */
  261. tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
  262. /* specify r/w */
  263. tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);
  264. /* clear INTR & ERROR flags */
  265. tx4939ide_clear_dma_status(base);
  266. tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
  267. TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
  268. tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt);
  269. return 0;
  270. }
  271. static int tx4939ide_dma_end(ide_drive_t *drive)
  272. {
  273. ide_hwif_t *hwif = drive->hwif;
  274. u8 dma_stat, dma_cmd;
  275. void __iomem *base = TX4939IDE_BASE(hwif);
  276. u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
  277. /* get DMA command mode */
  278. dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
  279. /* stop DMA */
  280. tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
  281. /* read and clear the INTR & ERROR bits */
  282. dma_stat = tx4939ide_clear_dma_status(base);
  283. #define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)
  284. /* verify good DMA status */
  285. if ((dma_stat & CHECK_DMA_MASK) == 0 &&
  286. (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
  287. (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
  288. /* INT_IDE lost... bug? */
  289. return 0;
  290. return ((dma_stat & CHECK_DMA_MASK) !=
  291. ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
  292. }
  293. /* returns 1 if DMA IRQ issued, 0 otherwise */
  294. static int tx4939ide_dma_test_irq(ide_drive_t *drive)
  295. {
  296. ide_hwif_t *hwif = drive->hwif;
  297. void __iomem *base = TX4939IDE_BASE(hwif);
  298. u16 ctl, ide_int;
  299. u8 dma_stat, stat;
  300. int found = 0;
  301. ctl = tx4939ide_check_error_ints(hwif);
  302. ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
  303. switch (ide_int) {
  304. case TX4939IDE_INT_HOST:
  305. /* On error, XFEREND might not be asserted. */
  306. stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
  307. if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
  308. found = 1;
  309. else
  310. /* Wait for XFEREND (Mask HOST and unmask XFEREND) */
  311. ctl &= ~TX4939IDE_INT_XFEREND << 8;
  312. ctl |= ide_int << 8;
  313. break;
  314. case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
  315. dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
  316. if (!(dma_stat & ATA_DMA_INTR))
  317. pr_warn("%s: weird interrupt status. "
  318. "DMA_Stat %#02x int_ctl %#04x\n",
  319. hwif->name, dma_stat, ctl);
  320. found = 1;
  321. break;
  322. }
  323. /*
  324. * Do not clear XFEREND, HOST now. They will be cleared by
  325. * clearing bit2 of DMA_Stat.
  326. */
  327. ctl &= ~ide_int;
  328. tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
  329. return found;
  330. }
  331. #ifdef __BIG_ENDIAN
  332. static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
  333. {
  334. void __iomem *base = TX4939IDE_BASE(hwif);
  335. return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
  336. }
  337. #else
  338. #define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
  339. #endif
  340. static void tx4939ide_init_hwif(ide_hwif_t *hwif)
  341. {
  342. void __iomem *base = TX4939IDE_BASE(hwif);
  343. /* Soft Reset */
  344. tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
  345. /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
  346. ndelay(450);
  347. tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
  348. /* mask some interrupts and clear all interrupts */
  349. tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
  350. TX4939IDE_Int_Ctl);
  351. tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
  352. tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
  353. }
  354. static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
  355. {
  356. hwif->dma_base =
  357. hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
  358. /*
  359. * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
  360. * for big endian.
  361. */
  362. return ide_allocate_dma_engine(hwif);
  363. }
  364. static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
  365. {
  366. ide_hwif_t *hwif = drive->hwif;
  367. void __iomem *base = TX4939IDE_BASE(hwif);
  368. u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
  369. /*
  370. * Fix ATA100 CORE System Control Register. (The write to the
  371. * Device/Head register may write wrong data to the System
  372. * Control Register)
  373. * While Sys_Ctl is written here, dev_select() is not needed.
  374. */
  375. tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
  376. }
  377. static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf,
  378. u8 valid)
  379. {
  380. ide_tf_load(drive, tf, valid);
  381. if (valid & IDE_VALID_DEVICE)
  382. tx4939ide_tf_load_fixup(drive);
  383. }
  384. #ifdef __BIG_ENDIAN
  385. /* custom iops (independent from SWAP_IO_SPACE) */
  386. static void tx4939ide_input_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
  387. void *buf, unsigned int len)
  388. {
  389. unsigned long port = drive->hwif->io_ports.data_addr;
  390. unsigned short *ptr = buf;
  391. unsigned int count = (len + 1) / 2;
  392. while (count--)
  393. *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
  394. __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
  395. }
  396. static void tx4939ide_output_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
  397. void *buf, unsigned int len)
  398. {
  399. unsigned long port = drive->hwif->io_ports.data_addr;
  400. unsigned short *ptr = buf;
  401. unsigned int count = (len + 1) / 2;
  402. while (count--) {
  403. __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
  404. ptr++;
  405. }
  406. __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
  407. }
  408. static const struct ide_tp_ops tx4939ide_tp_ops = {
  409. .exec_command = ide_exec_command,
  410. .read_status = ide_read_status,
  411. .read_altstatus = ide_read_altstatus,
  412. .write_devctl = ide_write_devctl,
  413. .dev_select = ide_dev_select,
  414. .tf_load = tx4939ide_tf_load,
  415. .tf_read = ide_tf_read,
  416. .input_data = tx4939ide_input_data_swap,
  417. .output_data = tx4939ide_output_data_swap,
  418. };
  419. #else /* __LITTLE_ENDIAN */
  420. static const struct ide_tp_ops tx4939ide_tp_ops = {
  421. .exec_command = ide_exec_command,
  422. .read_status = ide_read_status,
  423. .read_altstatus = ide_read_altstatus,
  424. .write_devctl = ide_write_devctl,
  425. .dev_select = ide_dev_select,
  426. .tf_load = tx4939ide_tf_load,
  427. .tf_read = ide_tf_read,
  428. .input_data = ide_input_data,
  429. .output_data = ide_output_data,
  430. };
  431. #endif /* __LITTLE_ENDIAN */
  432. static const struct ide_port_ops tx4939ide_port_ops = {
  433. .set_pio_mode = tx4939ide_set_pio_mode,
  434. .set_dma_mode = tx4939ide_set_dma_mode,
  435. .clear_irq = tx4939ide_clear_irq,
  436. .cable_detect = tx4939ide_cable_detect,
  437. };
  438. static const struct ide_dma_ops tx4939ide_dma_ops = {
  439. .dma_host_set = tx4939ide_dma_host_set,
  440. .dma_setup = tx4939ide_dma_setup,
  441. .dma_start = ide_dma_start,
  442. .dma_end = tx4939ide_dma_end,
  443. .dma_test_irq = tx4939ide_dma_test_irq,
  444. .dma_lost_irq = ide_dma_lost_irq,
  445. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  446. .dma_sff_read_status = tx4939ide_dma_sff_read_status,
  447. };
  448. static const struct ide_port_info tx4939ide_port_info __initconst = {
  449. .init_hwif = tx4939ide_init_hwif,
  450. .init_dma = tx4939ide_init_dma,
  451. .port_ops = &tx4939ide_port_ops,
  452. .dma_ops = &tx4939ide_dma_ops,
  453. .tp_ops = &tx4939ide_tp_ops,
  454. .host_flags = IDE_HFLAG_MMIO,
  455. .pio_mask = ATA_PIO4,
  456. .mwdma_mask = ATA_MWDMA2,
  457. .udma_mask = ATA_UDMA5,
  458. .chipset = ide_generic,
  459. };
  460. static int __init tx4939ide_probe(struct platform_device *pdev)
  461. {
  462. struct ide_hw hw, *hws[] = { &hw };
  463. struct ide_host *host;
  464. struct resource *res;
  465. int irq, ret;
  466. unsigned long mapbase;
  467. irq = platform_get_irq(pdev, 0);
  468. if (irq < 0)
  469. return -ENODEV;
  470. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  471. if (!res)
  472. return -ENODEV;
  473. if (!devm_request_mem_region(&pdev->dev, res->start,
  474. resource_size(res), MODNAME))
  475. return -EBUSY;
  476. mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
  477. resource_size(res));
  478. if (!mapbase)
  479. return -EBUSY;
  480. memset(&hw, 0, sizeof(hw));
  481. hw.io_ports.data_addr =
  482. mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
  483. hw.io_ports.error_addr =
  484. mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
  485. hw.io_ports.nsect_addr =
  486. mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
  487. hw.io_ports.lbal_addr =
  488. mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
  489. hw.io_ports.lbam_addr =
  490. mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
  491. hw.io_ports.lbah_addr =
  492. mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
  493. hw.io_ports.device_addr =
  494. mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
  495. hw.io_ports.command_addr =
  496. mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
  497. hw.io_ports.ctl_addr =
  498. mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
  499. hw.irq = irq;
  500. hw.dev = &pdev->dev;
  501. pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
  502. host = ide_host_alloc(&tx4939ide_port_info, hws, 1);
  503. if (!host)
  504. return -ENOMEM;
  505. /* use extra_base for base address of the all registers */
  506. host->ports[0]->extra_base = mapbase;
  507. ret = ide_host_register(host, &tx4939ide_port_info, hws);
  508. if (ret) {
  509. ide_host_free(host);
  510. return ret;
  511. }
  512. platform_set_drvdata(pdev, host);
  513. return 0;
  514. }
  515. static int __exit tx4939ide_remove(struct platform_device *pdev)
  516. {
  517. struct ide_host *host = platform_get_drvdata(pdev);
  518. ide_host_remove(host);
  519. return 0;
  520. }
  521. #ifdef CONFIG_PM
  522. static int tx4939ide_resume(struct platform_device *dev)
  523. {
  524. struct ide_host *host = platform_get_drvdata(dev);
  525. ide_hwif_t *hwif = host->ports[0];
  526. tx4939ide_init_hwif(hwif);
  527. return 0;
  528. }
  529. #else
  530. #define tx4939ide_resume NULL
  531. #endif
  532. static struct platform_driver tx4939ide_driver = {
  533. .driver = {
  534. .name = MODNAME,
  535. },
  536. .remove = __exit_p(tx4939ide_remove),
  537. .resume = tx4939ide_resume,
  538. };
  539. module_platform_driver_probe(tx4939ide_driver, tx4939ide_probe);
  540. MODULE_DESCRIPTION("TX4939 internal IDE driver");
  541. MODULE_LICENSE("GPL");
  542. MODULE_ALIAS("platform:tx4939ide");