trm290.c 11 KB

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  1. /*
  2. * Copyright (c) 1997-1998 Mark Lord
  3. * Copyright (c) 2007 MontaVista Software, Inc. <source@mvista.com>
  4. *
  5. * May be copied or modified under the terms of the GNU General Public License
  6. *
  7. * June 22, 2004 - get rid of check_region
  8. * - Jesper Juhl
  9. *
  10. */
  11. /*
  12. * This module provides support for the bus-master IDE DMA function
  13. * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
  14. * including a "Precision Instruments" board. The TRM290 pre-dates
  15. * the sff-8038 standard (ide-dma.c) by a few months, and differs
  16. * significantly enough to warrant separate routines for some functions,
  17. * while re-using others from ide-dma.c.
  18. *
  19. * EXPERIMENTAL! It works for me (a sample of one).
  20. *
  21. * Works reliably for me in DMA mode (READs only),
  22. * DMA WRITEs are disabled by default (see #define below);
  23. *
  24. * DMA is not enabled automatically for this chipset,
  25. * but can be turned on manually (with "hdparm -d1") at run time.
  26. *
  27. * I need volunteers with "spare" drives for further testing
  28. * and development, and maybe to help figure out the peculiarities.
  29. * Even knowing the registers (below), some things behave strangely.
  30. */
  31. #define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
  32. /*
  33. * TRM-290 PCI-IDE2 Bus Master Chip
  34. * ================================
  35. * The configuration registers are addressed in normal I/O port space
  36. * and are used as follows:
  37. *
  38. * trm290_base depends on jumper settings, and is probed for by ide-dma.c
  39. *
  40. * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
  41. * bit7 must always be written as "1"
  42. * bits6-2 undefined
  43. * bit1 1=legacy_compatible_mode, 0=native_pci_mode
  44. * bit0 1=test_mode, 0=normal(default)
  45. *
  46. * trm290_base+2 when READ: status register (byte, read-only)
  47. * bits7-2 undefined
  48. * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
  49. * bit0 channel0 interrupt status 0=none, 1=asserted
  50. *
  51. * trm290_base+3 Interrupt mask register
  52. * bits7-5 undefined
  53. * bit4 legacy_header: 1=present, 0=absent
  54. * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
  55. * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
  56. * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
  57. * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
  58. *
  59. * trm290_base+1 "CPR" Config Pointer Register (byte)
  60. * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
  61. * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
  62. * bit5 0=enabled master burst access (default), 1=disable (write only)
  63. * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
  64. * bit3 0=primary IDE channel, 1=secondary IDE channel
  65. * bits2-0 register index for accesses through CDR port
  66. *
  67. * trm290_base+0 "CDR" Config Data Register (word)
  68. * two sets of seven config registers,
  69. * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
  70. * each index defined below:
  71. *
  72. * Index-0 Base address register for command block (word)
  73. * defaults: 0x1f0 for primary, 0x170 for secondary
  74. *
  75. * Index-1 general config register (byte)
  76. * bit7 1=DMA enable, 0=DMA disable
  77. * bit6 1=activate IDE_RESET, 0=no action (default)
  78. * bit5 1=enable IORDY, 0=disable IORDY (default)
  79. * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
  80. * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
  81. * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
  82. * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
  83. * bit0 enable_io_ports: 1=enable(default), 0=disable
  84. *
  85. * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
  86. * bits7-0 bits7-0 of readahead count
  87. *
  88. * Index-3 read-ahead config register (byte, write only)
  89. * bit7 1=enable_readahead, 0=disable_readahead(default)
  90. * bit6 1=clear_FIFO, 0=no_action
  91. * bit5 undefined
  92. * bit4 mode4 timing control: 1=enable, 0=disable(default)
  93. * bit3 undefined
  94. * bit2 undefined
  95. * bits1-0 bits9-8 of read-ahead count
  96. *
  97. * Index-4 base address register for control block (word)
  98. * defaults: 0x3f6 for primary, 0x376 for secondary
  99. *
  100. * Index-5 data port timings (shared by both drives) (byte)
  101. * standard PCI "clk" (clock) counts, default value = 0xf5
  102. *
  103. * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
  104. * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
  105. * 011=4clk, 100=5clk, 101=6clk,
  106. * 110=8clk, 111=12clk
  107. * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
  108. * 011=5clk, 100=6clk, 101=8clk,
  109. * 110=12clk, 111=16clk
  110. *
  111. * Index-6 command/control port timings (shared by both drives) (byte)
  112. * same layout as Index-5, default value = 0xde
  113. *
  114. * Suggested CDR programming for PIO mode0 (600ns):
  115. * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
  116. * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
  117. *
  118. * Suggested CDR programming for PIO mode3 (180ns):
  119. * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
  120. * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
  121. *
  122. * Suggested CDR programming for PIO mode4 (120ns):
  123. * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
  124. * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
  125. *
  126. */
  127. #include <linux/types.h>
  128. #include <linux/module.h>
  129. #include <linux/kernel.h>
  130. #include <linux/ioport.h>
  131. #include <linux/interrupt.h>
  132. #include <linux/blkdev.h>
  133. #include <linux/init.h>
  134. #include <linux/pci.h>
  135. #include <linux/ide.h>
  136. #include <asm/io.h>
  137. #define DRV_NAME "trm290"
  138. static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
  139. {
  140. ide_hwif_t *hwif = drive->hwif;
  141. u16 reg = 0;
  142. unsigned long flags;
  143. /* select PIO or DMA */
  144. reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
  145. local_irq_save(flags);
  146. if (reg != hwif->select_data) {
  147. hwif->select_data = reg;
  148. /* set PIO/DMA */
  149. outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
  150. outw(reg & 0xff, hwif->config_data);
  151. }
  152. /* enable IRQ if not probing */
  153. if (drive->dev_flags & IDE_DFLAG_PRESENT) {
  154. reg = inw(hwif->config_data + 3);
  155. reg &= 0x13;
  156. reg &= ~(1 << hwif->channel);
  157. outw(reg, hwif->config_data + 3);
  158. }
  159. local_irq_restore(flags);
  160. }
  161. static void trm290_dev_select(ide_drive_t *drive)
  162. {
  163. trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
  164. outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
  165. }
  166. static int trm290_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
  167. {
  168. if (cmd->tf_flags & IDE_TFLAG_WRITE) {
  169. #ifdef TRM290_NO_DMA_WRITES
  170. /* always use PIO for writes */
  171. return 1;
  172. #endif
  173. }
  174. return 0;
  175. }
  176. static int trm290_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
  177. {
  178. ide_hwif_t *hwif = drive->hwif;
  179. unsigned int count, rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 1 : 2;
  180. count = ide_build_dmatable(drive, cmd);
  181. if (count == 0)
  182. /* try PIO instead of DMA */
  183. return 1;
  184. outl(hwif->dmatable_dma | rw, hwif->dma_base);
  185. /* start DMA */
  186. outw(count * 2 - 1, hwif->dma_base + 2);
  187. return 0;
  188. }
  189. static void trm290_dma_start(ide_drive_t *drive)
  190. {
  191. trm290_prepare_drive(drive, 1);
  192. }
  193. static int trm290_dma_end(ide_drive_t *drive)
  194. {
  195. u16 status = inw(drive->hwif->dma_base + 2);
  196. trm290_prepare_drive(drive, 0);
  197. return status != 0x00ff;
  198. }
  199. static int trm290_dma_test_irq(ide_drive_t *drive)
  200. {
  201. u16 status = inw(drive->hwif->dma_base + 2);
  202. return status == 0x00ff;
  203. }
  204. static void trm290_dma_host_set(ide_drive_t *drive, int on)
  205. {
  206. }
  207. static void init_hwif_trm290(ide_hwif_t *hwif)
  208. {
  209. struct pci_dev *dev = to_pci_dev(hwif->dev);
  210. unsigned int cfg_base = pci_resource_start(dev, 4);
  211. unsigned long flags;
  212. u8 reg = 0;
  213. if ((dev->class & 5) && cfg_base)
  214. printk(KERN_INFO DRV_NAME " %s: chip", pci_name(dev));
  215. else {
  216. cfg_base = 0x3df0;
  217. printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev));
  218. }
  219. printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
  220. hwif->config_data = cfg_base;
  221. hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);
  222. printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
  223. hwif->name, hwif->dma_base, hwif->dma_base + 3);
  224. if (ide_allocate_dma_engine(hwif))
  225. return;
  226. local_irq_save(flags);
  227. /* put config reg into first byte of hwif->select_data */
  228. outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
  229. /* select PIO as default */
  230. hwif->select_data = 0x21;
  231. outb(hwif->select_data, hwif->config_data);
  232. /* get IRQ info */
  233. reg = inb(hwif->config_data + 3);
  234. /* mask IRQs for both ports */
  235. reg = (reg & 0x10) | 0x03;
  236. outb(reg, hwif->config_data + 3);
  237. local_irq_restore(flags);
  238. if (reg & 0x10)
  239. /* legacy mode */
  240. hwif->irq = hwif->channel ? 15 : 14;
  241. #if 1
  242. {
  243. /*
  244. * My trm290-based card doesn't seem to work with all possible values
  245. * for the control basereg, so this kludge ensures that we use only
  246. * values that are known to work. Ugh. -ml
  247. */
  248. u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
  249. static u16 next_offset = 0;
  250. u8 old_mask;
  251. outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
  252. old = inw(hwif->config_data);
  253. old &= ~1;
  254. old_mask = inb(old + 2);
  255. if (old != compat && old_mask == 0xff) {
  256. /* leave lower 10 bits untouched */
  257. compat += (next_offset += 0x400);
  258. hwif->io_ports.ctl_addr = compat + 2;
  259. outw(compat | 1, hwif->config_data);
  260. new = inw(hwif->config_data);
  261. printk(KERN_INFO "%s: control basereg workaround: "
  262. "old=0x%04x, new=0x%04x\n",
  263. hwif->name, old, new & ~1);
  264. }
  265. }
  266. #endif
  267. }
  268. static const struct ide_tp_ops trm290_tp_ops = {
  269. .exec_command = ide_exec_command,
  270. .read_status = ide_read_status,
  271. .read_altstatus = ide_read_altstatus,
  272. .write_devctl = ide_write_devctl,
  273. .dev_select = trm290_dev_select,
  274. .tf_load = ide_tf_load,
  275. .tf_read = ide_tf_read,
  276. .input_data = ide_input_data,
  277. .output_data = ide_output_data,
  278. };
  279. static const struct ide_dma_ops trm290_dma_ops = {
  280. .dma_host_set = trm290_dma_host_set,
  281. .dma_setup = trm290_dma_setup,
  282. .dma_start = trm290_dma_start,
  283. .dma_end = trm290_dma_end,
  284. .dma_test_irq = trm290_dma_test_irq,
  285. .dma_lost_irq = ide_dma_lost_irq,
  286. .dma_check = trm290_dma_check,
  287. };
  288. static const struct ide_port_info trm290_chipset = {
  289. .name = DRV_NAME,
  290. .init_hwif = init_hwif_trm290,
  291. .tp_ops = &trm290_tp_ops,
  292. .dma_ops = &trm290_dma_ops,
  293. .host_flags = IDE_HFLAG_TRM290 |
  294. IDE_HFLAG_NO_ATAPI_DMA |
  295. #if 0 /* play it safe for now */
  296. IDE_HFLAG_TRUST_BIOS_FOR_DMA |
  297. #endif
  298. IDE_HFLAG_NO_AUTODMA |
  299. IDE_HFLAG_NO_LBA48,
  300. };
  301. static int trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  302. {
  303. return ide_pci_init_one(dev, &trm290_chipset, NULL);
  304. }
  305. static const struct pci_device_id trm290_pci_tbl[] = {
  306. { PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
  307. { 0, },
  308. };
  309. MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
  310. static struct pci_driver trm290_pci_driver = {
  311. .name = "TRM290_IDE",
  312. .id_table = trm290_pci_tbl,
  313. .probe = trm290_init_one,
  314. .remove = ide_pci_remove,
  315. };
  316. static int __init trm290_ide_init(void)
  317. {
  318. return ide_pci_register_driver(&trm290_pci_driver);
  319. }
  320. static void __exit trm290_ide_exit(void)
  321. {
  322. pci_unregister_driver(&trm290_pci_driver);
  323. }
  324. module_init(trm290_ide_init);
  325. module_exit(trm290_ide_exit);
  326. MODULE_AUTHOR("Mark Lord");
  327. MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
  328. MODULE_LICENSE("GPL");