pmac.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Support for IDE interfaces on PowerMacs.
  4. *
  5. * These IDE interfaces are memory-mapped and have a DBDMA channel
  6. * for doing DMA.
  7. *
  8. * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
  9. * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
  10. *
  11. * Some code taken from drivers/ide/ide-dma.c:
  12. *
  13. * Copyright (c) 1995-1998 Mark Lord
  14. *
  15. * TODO: - Use pre-calculated (kauai) timing tables all the time and
  16. * get rid of the "rounded" tables used previously, so we have the
  17. * same table format for all controllers and can then just have one
  18. * big table
  19. */
  20. #include <linux/types.h>
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include <linux/ide.h>
  25. #include <linux/notifier.h>
  26. #include <linux/module.h>
  27. #include <linux/reboot.h>
  28. #include <linux/pci.h>
  29. #include <linux/adb.h>
  30. #include <linux/pmu.h>
  31. #include <linux/scatterlist.h>
  32. #include <linux/slab.h>
  33. #include <asm/prom.h>
  34. #include <asm/io.h>
  35. #include <asm/dbdma.h>
  36. #include <asm/ide.h>
  37. #include <asm/machdep.h>
  38. #include <asm/pmac_feature.h>
  39. #include <asm/sections.h>
  40. #include <asm/irq.h>
  41. #include <asm/mediabay.h>
  42. #define DRV_NAME "ide-pmac"
  43. #undef IDE_PMAC_DEBUG
  44. #define DMA_WAIT_TIMEOUT 50
  45. typedef struct pmac_ide_hwif {
  46. unsigned long regbase;
  47. int irq;
  48. int kind;
  49. int aapl_bus_id;
  50. unsigned broken_dma : 1;
  51. unsigned broken_dma_warn : 1;
  52. struct device_node* node;
  53. struct macio_dev *mdev;
  54. u32 timings[4];
  55. volatile u32 __iomem * *kauai_fcr;
  56. ide_hwif_t *hwif;
  57. /* Those fields are duplicating what is in hwif. We currently
  58. * can't use the hwif ones because of some assumptions that are
  59. * beeing done by the generic code about the kind of dma controller
  60. * and format of the dma table. This will have to be fixed though.
  61. */
  62. volatile struct dbdma_regs __iomem * dma_regs;
  63. struct dbdma_cmd* dma_table_cpu;
  64. } pmac_ide_hwif_t;
  65. enum {
  66. controller_ohare, /* OHare based */
  67. controller_heathrow, /* Heathrow/Paddington */
  68. controller_kl_ata3, /* KeyLargo ATA-3 */
  69. controller_kl_ata4, /* KeyLargo ATA-4 */
  70. controller_un_ata6, /* UniNorth2 ATA-6 */
  71. controller_k2_ata6, /* K2 ATA-6 */
  72. controller_sh_ata6, /* Shasta ATA-6 */
  73. };
  74. static const char* model_name[] = {
  75. "OHare ATA", /* OHare based */
  76. "Heathrow ATA", /* Heathrow/Paddington */
  77. "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
  78. "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
  79. "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
  80. "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
  81. "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
  82. };
  83. /*
  84. * Extra registers, both 32-bit little-endian
  85. */
  86. #define IDE_TIMING_CONFIG 0x200
  87. #define IDE_INTERRUPT 0x300
  88. /* Kauai (U2) ATA has different register setup */
  89. #define IDE_KAUAI_PIO_CONFIG 0x200
  90. #define IDE_KAUAI_ULTRA_CONFIG 0x210
  91. #define IDE_KAUAI_POLL_CONFIG 0x220
  92. /*
  93. * Timing configuration register definitions
  94. */
  95. /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
  96. #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
  97. #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
  98. #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
  99. #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
  100. /* 133Mhz cell, found in shasta.
  101. * See comments about 100 Mhz Uninorth 2...
  102. * Note that PIO_MASK and MDMA_MASK seem to overlap
  103. */
  104. #define TR_133_PIOREG_PIO_MASK 0xff000fff
  105. #define TR_133_PIOREG_MDMA_MASK 0x00fff800
  106. #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
  107. #define TR_133_UDMAREG_UDMA_EN 0x00000001
  108. /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
  109. * this one yet, it appears as a pci device (106b/0033) on uninorth
  110. * internal PCI bus and it's clock is controlled like gem or fw. It
  111. * appears to be an evolution of keylargo ATA4 with a timing register
  112. * extended to 2 32bits registers and a similar DBDMA channel. Other
  113. * registers seem to exist but I can't tell much about them.
  114. *
  115. * So far, I'm using pre-calculated tables for this extracted from
  116. * the values used by the MacOS X driver.
  117. *
  118. * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
  119. * register controls the UDMA timings. At least, it seems bit 0
  120. * of this one enables UDMA vs. MDMA, and bits 4..7 are the
  121. * cycle time in units of 10ns. Bits 8..15 are used by I don't
  122. * know their meaning yet
  123. */
  124. #define TR_100_PIOREG_PIO_MASK 0xff000fff
  125. #define TR_100_PIOREG_MDMA_MASK 0x00fff000
  126. #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
  127. #define TR_100_UDMAREG_UDMA_EN 0x00000001
  128. /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
  129. * 40 connector cable and to 4 on 80 connector one.
  130. * Clock unit is 15ns (66Mhz)
  131. *
  132. * 3 Values can be programmed:
  133. * - Write data setup, which appears to match the cycle time. They
  134. * also call it DIOW setup.
  135. * - Ready to pause time (from spec)
  136. * - Address setup. That one is weird. I don't see where exactly
  137. * it fits in UDMA cycles, I got it's name from an obscure piece
  138. * of commented out code in Darwin. They leave it to 0, we do as
  139. * well, despite a comment that would lead to think it has a
  140. * min value of 45ns.
  141. * Apple also add 60ns to the write data setup (or cycle time ?) on
  142. * reads.
  143. */
  144. #define TR_66_UDMA_MASK 0xfff00000
  145. #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
  146. #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
  147. #define TR_66_UDMA_ADDRSETUP_SHIFT 29
  148. #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
  149. #define TR_66_UDMA_RDY2PAUS_SHIFT 25
  150. #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
  151. #define TR_66_UDMA_WRDATASETUP_SHIFT 21
  152. #define TR_66_MDMA_MASK 0x000ffc00
  153. #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
  154. #define TR_66_MDMA_RECOVERY_SHIFT 15
  155. #define TR_66_MDMA_ACCESS_MASK 0x00007c00
  156. #define TR_66_MDMA_ACCESS_SHIFT 10
  157. #define TR_66_PIO_MASK 0x000003ff
  158. #define TR_66_PIO_RECOVERY_MASK 0x000003e0
  159. #define TR_66_PIO_RECOVERY_SHIFT 5
  160. #define TR_66_PIO_ACCESS_MASK 0x0000001f
  161. #define TR_66_PIO_ACCESS_SHIFT 0
  162. /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
  163. * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
  164. *
  165. * The access time and recovery time can be programmed. Some older
  166. * Darwin code base limit OHare to 150ns cycle time. I decided to do
  167. * the same here fore safety against broken old hardware ;)
  168. * The HalfTick bit, when set, adds half a clock (15ns) to the access
  169. * time and removes one from recovery. It's not supported on KeyLargo
  170. * implementation afaik. The E bit appears to be set for PIO mode 0 and
  171. * is used to reach long timings used in this mode.
  172. */
  173. #define TR_33_MDMA_MASK 0x003ff800
  174. #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
  175. #define TR_33_MDMA_RECOVERY_SHIFT 16
  176. #define TR_33_MDMA_ACCESS_MASK 0x0000f800
  177. #define TR_33_MDMA_ACCESS_SHIFT 11
  178. #define TR_33_MDMA_HALFTICK 0x00200000
  179. #define TR_33_PIO_MASK 0x000007ff
  180. #define TR_33_PIO_E 0x00000400
  181. #define TR_33_PIO_RECOVERY_MASK 0x000003e0
  182. #define TR_33_PIO_RECOVERY_SHIFT 5
  183. #define TR_33_PIO_ACCESS_MASK 0x0000001f
  184. #define TR_33_PIO_ACCESS_SHIFT 0
  185. /*
  186. * Interrupt register definitions
  187. */
  188. #define IDE_INTR_DMA 0x80000000
  189. #define IDE_INTR_DEVICE 0x40000000
  190. /*
  191. * FCR Register on Kauai. Not sure what bit 0x4 is ...
  192. */
  193. #define KAUAI_FCR_UATA_MAGIC 0x00000004
  194. #define KAUAI_FCR_UATA_RESET_N 0x00000002
  195. #define KAUAI_FCR_UATA_ENABLE 0x00000001
  196. /* Rounded Multiword DMA timings
  197. *
  198. * I gave up finding a generic formula for all controller
  199. * types and instead, built tables based on timing values
  200. * used by Apple in Darwin's implementation.
  201. */
  202. struct mdma_timings_t {
  203. int accessTime;
  204. int recoveryTime;
  205. int cycleTime;
  206. };
  207. struct mdma_timings_t mdma_timings_33[] =
  208. {
  209. { 240, 240, 480 },
  210. { 180, 180, 360 },
  211. { 135, 135, 270 },
  212. { 120, 120, 240 },
  213. { 105, 105, 210 },
  214. { 90, 90, 180 },
  215. { 75, 75, 150 },
  216. { 75, 45, 120 },
  217. { 0, 0, 0 }
  218. };
  219. struct mdma_timings_t mdma_timings_33k[] =
  220. {
  221. { 240, 240, 480 },
  222. { 180, 180, 360 },
  223. { 150, 150, 300 },
  224. { 120, 120, 240 },
  225. { 90, 120, 210 },
  226. { 90, 90, 180 },
  227. { 90, 60, 150 },
  228. { 90, 30, 120 },
  229. { 0, 0, 0 }
  230. };
  231. struct mdma_timings_t mdma_timings_66[] =
  232. {
  233. { 240, 240, 480 },
  234. { 180, 180, 360 },
  235. { 135, 135, 270 },
  236. { 120, 120, 240 },
  237. { 105, 105, 210 },
  238. { 90, 90, 180 },
  239. { 90, 75, 165 },
  240. { 75, 45, 120 },
  241. { 0, 0, 0 }
  242. };
  243. /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
  244. struct {
  245. int addrSetup; /* ??? */
  246. int rdy2pause;
  247. int wrDataSetup;
  248. } kl66_udma_timings[] =
  249. {
  250. { 0, 180, 120 }, /* Mode 0 */
  251. { 0, 150, 90 }, /* 1 */
  252. { 0, 120, 60 }, /* 2 */
  253. { 0, 90, 45 }, /* 3 */
  254. { 0, 90, 30 } /* 4 */
  255. };
  256. /* UniNorth 2 ATA/100 timings */
  257. struct kauai_timing {
  258. int cycle_time;
  259. u32 timing_reg;
  260. };
  261. static struct kauai_timing kauai_pio_timings[] =
  262. {
  263. { 930 , 0x08000fff },
  264. { 600 , 0x08000a92 },
  265. { 383 , 0x0800060f },
  266. { 360 , 0x08000492 },
  267. { 330 , 0x0800048f },
  268. { 300 , 0x080003cf },
  269. { 270 , 0x080003cc },
  270. { 240 , 0x0800038b },
  271. { 239 , 0x0800030c },
  272. { 180 , 0x05000249 },
  273. { 120 , 0x04000148 },
  274. { 0 , 0 },
  275. };
  276. static struct kauai_timing kauai_mdma_timings[] =
  277. {
  278. { 1260 , 0x00fff000 },
  279. { 480 , 0x00618000 },
  280. { 360 , 0x00492000 },
  281. { 270 , 0x0038e000 },
  282. { 240 , 0x0030c000 },
  283. { 210 , 0x002cb000 },
  284. { 180 , 0x00249000 },
  285. { 150 , 0x00209000 },
  286. { 120 , 0x00148000 },
  287. { 0 , 0 },
  288. };
  289. static struct kauai_timing kauai_udma_timings[] =
  290. {
  291. { 120 , 0x000070c0 },
  292. { 90 , 0x00005d80 },
  293. { 60 , 0x00004a60 },
  294. { 45 , 0x00003a50 },
  295. { 30 , 0x00002a30 },
  296. { 20 , 0x00002921 },
  297. { 0 , 0 },
  298. };
  299. static struct kauai_timing shasta_pio_timings[] =
  300. {
  301. { 930 , 0x08000fff },
  302. { 600 , 0x0A000c97 },
  303. { 383 , 0x07000712 },
  304. { 360 , 0x040003cd },
  305. { 330 , 0x040003cd },
  306. { 300 , 0x040003cd },
  307. { 270 , 0x040003cd },
  308. { 240 , 0x040003cd },
  309. { 239 , 0x040003cd },
  310. { 180 , 0x0400028b },
  311. { 120 , 0x0400010a },
  312. { 0 , 0 },
  313. };
  314. static struct kauai_timing shasta_mdma_timings[] =
  315. {
  316. { 1260 , 0x00fff000 },
  317. { 480 , 0x00820800 },
  318. { 360 , 0x00820800 },
  319. { 270 , 0x00820800 },
  320. { 240 , 0x00820800 },
  321. { 210 , 0x00820800 },
  322. { 180 , 0x00820800 },
  323. { 150 , 0x0028b000 },
  324. { 120 , 0x001ca000 },
  325. { 0 , 0 },
  326. };
  327. static struct kauai_timing shasta_udma133_timings[] =
  328. {
  329. { 120 , 0x00035901, },
  330. { 90 , 0x000348b1, },
  331. { 60 , 0x00033881, },
  332. { 45 , 0x00033861, },
  333. { 30 , 0x00033841, },
  334. { 20 , 0x00033031, },
  335. { 15 , 0x00033021, },
  336. { 0 , 0 },
  337. };
  338. static inline u32
  339. kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
  340. {
  341. int i;
  342. for (i=0; table[i].cycle_time; i++)
  343. if (cycle_time > table[i+1].cycle_time)
  344. return table[i].timing_reg;
  345. BUG();
  346. return 0;
  347. }
  348. /* allow up to 256 DBDMA commands per xfer */
  349. #define MAX_DCMDS 256
  350. /*
  351. * Wait 1s for disk to answer on IDE bus after a hard reset
  352. * of the device (via GPIO/FCR).
  353. *
  354. * Some devices seem to "pollute" the bus even after dropping
  355. * the BSY bit (typically some combo drives slave on the UDMA
  356. * bus) after a hard reset. Since we hard reset all drives on
  357. * KeyLargo ATA66, we have to keep that delay around. I may end
  358. * up not hard resetting anymore on these and keep the delay only
  359. * for older interfaces instead (we have to reset when coming
  360. * from MacOS...) --BenH.
  361. */
  362. #define IDE_WAKEUP_DELAY (1*HZ)
  363. static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
  364. #define PMAC_IDE_REG(x) \
  365. ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
  366. /*
  367. * Apply the timings of the proper unit (master/slave) to the shared
  368. * timing register when selecting that unit. This version is for
  369. * ASICs with a single timing register
  370. */
  371. static void pmac_ide_apply_timings(ide_drive_t *drive)
  372. {
  373. ide_hwif_t *hwif = drive->hwif;
  374. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  375. if (drive->dn & 1)
  376. writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
  377. else
  378. writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
  379. (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
  380. }
  381. /*
  382. * Apply the timings of the proper unit (master/slave) to the shared
  383. * timing register when selecting that unit. This version is for
  384. * ASICs with a dual timing register (Kauai)
  385. */
  386. static void pmac_ide_kauai_apply_timings(ide_drive_t *drive)
  387. {
  388. ide_hwif_t *hwif = drive->hwif;
  389. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  390. if (drive->dn & 1) {
  391. writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
  392. writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
  393. } else {
  394. writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
  395. writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
  396. }
  397. (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
  398. }
  399. /*
  400. * Force an update of controller timing values for a given drive
  401. */
  402. static void
  403. pmac_ide_do_update_timings(ide_drive_t *drive)
  404. {
  405. ide_hwif_t *hwif = drive->hwif;
  406. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  407. if (pmif->kind == controller_sh_ata6 ||
  408. pmif->kind == controller_un_ata6 ||
  409. pmif->kind == controller_k2_ata6)
  410. pmac_ide_kauai_apply_timings(drive);
  411. else
  412. pmac_ide_apply_timings(drive);
  413. }
  414. static void pmac_dev_select(ide_drive_t *drive)
  415. {
  416. pmac_ide_apply_timings(drive);
  417. writeb(drive->select | ATA_DEVICE_OBS,
  418. (void __iomem *)drive->hwif->io_ports.device_addr);
  419. }
  420. static void pmac_kauai_dev_select(ide_drive_t *drive)
  421. {
  422. pmac_ide_kauai_apply_timings(drive);
  423. writeb(drive->select | ATA_DEVICE_OBS,
  424. (void __iomem *)drive->hwif->io_ports.device_addr);
  425. }
  426. static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
  427. {
  428. writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
  429. (void)readl((void __iomem *)(hwif->io_ports.data_addr
  430. + IDE_TIMING_CONFIG));
  431. }
  432. static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
  433. {
  434. writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
  435. (void)readl((void __iomem *)(hwif->io_ports.data_addr
  436. + IDE_TIMING_CONFIG));
  437. }
  438. /*
  439. * Old tuning functions (called on hdparm -p), sets up drive PIO timings
  440. */
  441. static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  442. {
  443. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  444. const u8 pio = drive->pio_mode - XFER_PIO_0;
  445. struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
  446. u32 *timings, t;
  447. unsigned accessTicks, recTicks;
  448. unsigned accessTime, recTime;
  449. unsigned int cycle_time;
  450. /* which drive is it ? */
  451. timings = &pmif->timings[drive->dn & 1];
  452. t = *timings;
  453. cycle_time = ide_pio_cycle_time(drive, pio);
  454. switch (pmif->kind) {
  455. case controller_sh_ata6: {
  456. /* 133Mhz cell */
  457. u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
  458. t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
  459. break;
  460. }
  461. case controller_un_ata6:
  462. case controller_k2_ata6: {
  463. /* 100Mhz cell */
  464. u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
  465. t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
  466. break;
  467. }
  468. case controller_kl_ata4:
  469. /* 66Mhz cell */
  470. recTime = cycle_time - tim->active - tim->setup;
  471. recTime = max(recTime, 150U);
  472. accessTime = tim->active;
  473. accessTime = max(accessTime, 150U);
  474. accessTicks = SYSCLK_TICKS_66(accessTime);
  475. accessTicks = min(accessTicks, 0x1fU);
  476. recTicks = SYSCLK_TICKS_66(recTime);
  477. recTicks = min(recTicks, 0x1fU);
  478. t = (t & ~TR_66_PIO_MASK) |
  479. (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
  480. (recTicks << TR_66_PIO_RECOVERY_SHIFT);
  481. break;
  482. default: {
  483. /* 33Mhz cell */
  484. int ebit = 0;
  485. recTime = cycle_time - tim->active - tim->setup;
  486. recTime = max(recTime, 150U);
  487. accessTime = tim->active;
  488. accessTime = max(accessTime, 150U);
  489. accessTicks = SYSCLK_TICKS(accessTime);
  490. accessTicks = min(accessTicks, 0x1fU);
  491. accessTicks = max(accessTicks, 4U);
  492. recTicks = SYSCLK_TICKS(recTime);
  493. recTicks = min(recTicks, 0x1fU);
  494. recTicks = max(recTicks, 5U) - 4;
  495. if (recTicks > 9) {
  496. recTicks--; /* guess, but it's only for PIO0, so... */
  497. ebit = 1;
  498. }
  499. t = (t & ~TR_33_PIO_MASK) |
  500. (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
  501. (recTicks << TR_33_PIO_RECOVERY_SHIFT);
  502. if (ebit)
  503. t |= TR_33_PIO_E;
  504. break;
  505. }
  506. }
  507. #ifdef IDE_PMAC_DEBUG
  508. printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
  509. drive->name, pio, *timings);
  510. #endif
  511. *timings = t;
  512. pmac_ide_do_update_timings(drive);
  513. }
  514. /*
  515. * Calculate KeyLargo ATA/66 UDMA timings
  516. */
  517. static int
  518. set_timings_udma_ata4(u32 *timings, u8 speed)
  519. {
  520. unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
  521. if (speed > XFER_UDMA_4)
  522. return 1;
  523. rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
  524. wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
  525. addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
  526. *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
  527. (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
  528. (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
  529. (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
  530. TR_66_UDMA_EN;
  531. #ifdef IDE_PMAC_DEBUG
  532. printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
  533. speed & 0xf, *timings);
  534. #endif
  535. return 0;
  536. }
  537. /*
  538. * Calculate Kauai ATA/100 UDMA timings
  539. */
  540. static int
  541. set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
  542. {
  543. struct ide_timing *t = ide_timing_find_mode(speed);
  544. u32 tr;
  545. if (speed > XFER_UDMA_5 || t == NULL)
  546. return 1;
  547. tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
  548. *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
  549. *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
  550. return 0;
  551. }
  552. /*
  553. * Calculate Shasta ATA/133 UDMA timings
  554. */
  555. static int
  556. set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
  557. {
  558. struct ide_timing *t = ide_timing_find_mode(speed);
  559. u32 tr;
  560. if (speed > XFER_UDMA_6 || t == NULL)
  561. return 1;
  562. tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
  563. *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
  564. *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
  565. return 0;
  566. }
  567. /*
  568. * Calculate MDMA timings for all cells
  569. */
  570. static void
  571. set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
  572. u8 speed)
  573. {
  574. u16 *id = drive->id;
  575. int cycleTime, accessTime = 0, recTime = 0;
  576. unsigned accessTicks, recTicks;
  577. struct mdma_timings_t* tm = NULL;
  578. int i;
  579. /* Get default cycle time for mode */
  580. switch(speed & 0xf) {
  581. case 0: cycleTime = 480; break;
  582. case 1: cycleTime = 150; break;
  583. case 2: cycleTime = 120; break;
  584. default:
  585. BUG();
  586. break;
  587. }
  588. /* Check if drive provides explicit DMA cycle time */
  589. if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
  590. cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
  591. /* OHare limits according to some old Apple sources */
  592. if ((intf_type == controller_ohare) && (cycleTime < 150))
  593. cycleTime = 150;
  594. /* Get the proper timing array for this controller */
  595. switch(intf_type) {
  596. case controller_sh_ata6:
  597. case controller_un_ata6:
  598. case controller_k2_ata6:
  599. break;
  600. case controller_kl_ata4:
  601. tm = mdma_timings_66;
  602. break;
  603. case controller_kl_ata3:
  604. tm = mdma_timings_33k;
  605. break;
  606. default:
  607. tm = mdma_timings_33;
  608. break;
  609. }
  610. if (tm != NULL) {
  611. /* Lookup matching access & recovery times */
  612. i = -1;
  613. for (;;) {
  614. if (tm[i+1].cycleTime < cycleTime)
  615. break;
  616. i++;
  617. }
  618. cycleTime = tm[i].cycleTime;
  619. accessTime = tm[i].accessTime;
  620. recTime = tm[i].recoveryTime;
  621. #ifdef IDE_PMAC_DEBUG
  622. printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
  623. drive->name, cycleTime, accessTime, recTime);
  624. #endif
  625. }
  626. switch(intf_type) {
  627. case controller_sh_ata6: {
  628. /* 133Mhz cell */
  629. u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
  630. *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
  631. *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
  632. }
  633. break;
  634. case controller_un_ata6:
  635. case controller_k2_ata6: {
  636. /* 100Mhz cell */
  637. u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
  638. *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
  639. *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
  640. }
  641. break;
  642. case controller_kl_ata4:
  643. /* 66Mhz cell */
  644. accessTicks = SYSCLK_TICKS_66(accessTime);
  645. accessTicks = min(accessTicks, 0x1fU);
  646. accessTicks = max(accessTicks, 0x1U);
  647. recTicks = SYSCLK_TICKS_66(recTime);
  648. recTicks = min(recTicks, 0x1fU);
  649. recTicks = max(recTicks, 0x3U);
  650. /* Clear out mdma bits and disable udma */
  651. *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
  652. (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
  653. (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
  654. break;
  655. case controller_kl_ata3:
  656. /* 33Mhz cell on KeyLargo */
  657. accessTicks = SYSCLK_TICKS(accessTime);
  658. accessTicks = max(accessTicks, 1U);
  659. accessTicks = min(accessTicks, 0x1fU);
  660. accessTime = accessTicks * IDE_SYSCLK_NS;
  661. recTicks = SYSCLK_TICKS(recTime);
  662. recTicks = max(recTicks, 1U);
  663. recTicks = min(recTicks, 0x1fU);
  664. *timings = ((*timings) & ~TR_33_MDMA_MASK) |
  665. (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
  666. (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
  667. break;
  668. default: {
  669. /* 33Mhz cell on others */
  670. int halfTick = 0;
  671. int origAccessTime = accessTime;
  672. int origRecTime = recTime;
  673. accessTicks = SYSCLK_TICKS(accessTime);
  674. accessTicks = max(accessTicks, 1U);
  675. accessTicks = min(accessTicks, 0x1fU);
  676. accessTime = accessTicks * IDE_SYSCLK_NS;
  677. recTicks = SYSCLK_TICKS(recTime);
  678. recTicks = max(recTicks, 2U) - 1;
  679. recTicks = min(recTicks, 0x1fU);
  680. recTime = (recTicks + 1) * IDE_SYSCLK_NS;
  681. if ((accessTicks > 1) &&
  682. ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
  683. ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
  684. halfTick = 1;
  685. accessTicks--;
  686. }
  687. *timings = ((*timings) & ~TR_33_MDMA_MASK) |
  688. (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
  689. (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
  690. if (halfTick)
  691. *timings |= TR_33_MDMA_HALFTICK;
  692. }
  693. }
  694. #ifdef IDE_PMAC_DEBUG
  695. printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
  696. drive->name, speed & 0xf, *timings);
  697. #endif
  698. }
  699. static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  700. {
  701. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  702. int ret = 0;
  703. u32 *timings, *timings2, tl[2];
  704. u8 unit = drive->dn & 1;
  705. const u8 speed = drive->dma_mode;
  706. timings = &pmif->timings[unit];
  707. timings2 = &pmif->timings[unit+2];
  708. /* Copy timings to local image */
  709. tl[0] = *timings;
  710. tl[1] = *timings2;
  711. if (speed >= XFER_UDMA_0) {
  712. if (pmif->kind == controller_kl_ata4)
  713. ret = set_timings_udma_ata4(&tl[0], speed);
  714. else if (pmif->kind == controller_un_ata6
  715. || pmif->kind == controller_k2_ata6)
  716. ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
  717. else if (pmif->kind == controller_sh_ata6)
  718. ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
  719. else
  720. ret = -1;
  721. } else
  722. set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
  723. if (ret)
  724. return;
  725. /* Apply timings to controller */
  726. *timings = tl[0];
  727. *timings2 = tl[1];
  728. pmac_ide_do_update_timings(drive);
  729. }
  730. /*
  731. * Blast some well known "safe" values to the timing registers at init or
  732. * wakeup from sleep time, before we do real calculation
  733. */
  734. static void
  735. sanitize_timings(pmac_ide_hwif_t *pmif)
  736. {
  737. unsigned int value, value2 = 0;
  738. switch(pmif->kind) {
  739. case controller_sh_ata6:
  740. value = 0x0a820c97;
  741. value2 = 0x00033031;
  742. break;
  743. case controller_un_ata6:
  744. case controller_k2_ata6:
  745. value = 0x08618a92;
  746. value2 = 0x00002921;
  747. break;
  748. case controller_kl_ata4:
  749. value = 0x0008438c;
  750. break;
  751. case controller_kl_ata3:
  752. value = 0x00084526;
  753. break;
  754. case controller_heathrow:
  755. case controller_ohare:
  756. default:
  757. value = 0x00074526;
  758. break;
  759. }
  760. pmif->timings[0] = pmif->timings[1] = value;
  761. pmif->timings[2] = pmif->timings[3] = value2;
  762. }
  763. static int on_media_bay(pmac_ide_hwif_t *pmif)
  764. {
  765. return pmif->mdev && pmif->mdev->media_bay != NULL;
  766. }
  767. /* Suspend call back, should be called after the child devices
  768. * have actually been suspended
  769. */
  770. static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
  771. {
  772. /* We clear the timings */
  773. pmif->timings[0] = 0;
  774. pmif->timings[1] = 0;
  775. disable_irq(pmif->irq);
  776. /* The media bay will handle itself just fine */
  777. if (on_media_bay(pmif))
  778. return 0;
  779. /* Kauai has bus control FCRs directly here */
  780. if (pmif->kauai_fcr) {
  781. u32 fcr = readl(pmif->kauai_fcr);
  782. fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
  783. writel(fcr, pmif->kauai_fcr);
  784. }
  785. /* Disable the bus on older machines and the cell on kauai */
  786. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
  787. 0);
  788. return 0;
  789. }
  790. /* Resume call back, should be called before the child devices
  791. * are resumed
  792. */
  793. static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
  794. {
  795. /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
  796. if (!on_media_bay(pmif)) {
  797. ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
  798. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
  799. msleep(10);
  800. ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
  801. /* Kauai has it different */
  802. if (pmif->kauai_fcr) {
  803. u32 fcr = readl(pmif->kauai_fcr);
  804. fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
  805. writel(fcr, pmif->kauai_fcr);
  806. }
  807. msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
  808. }
  809. /* Sanitize drive timings */
  810. sanitize_timings(pmif);
  811. enable_irq(pmif->irq);
  812. return 0;
  813. }
  814. static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
  815. {
  816. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  817. struct device_node *np = pmif->node;
  818. const char *cable = of_get_property(np, "cable-type", NULL);
  819. struct device_node *root = of_find_node_by_path("/");
  820. const char *model = of_get_property(root, "model", NULL);
  821. of_node_put(root);
  822. /* Get cable type from device-tree. */
  823. if (cable && !strncmp(cable, "80-", 3)) {
  824. /* Some drives fail to detect 80c cable in PowerBook */
  825. /* These machine use proprietary short IDE cable anyway */
  826. if (!strncmp(model, "PowerBook", 9))
  827. return ATA_CBL_PATA40_SHORT;
  828. else
  829. return ATA_CBL_PATA80;
  830. }
  831. /*
  832. * G5's seem to have incorrect cable type in device-tree.
  833. * Let's assume they have a 80 conductor cable, this seem
  834. * to be always the case unless the user mucked around.
  835. */
  836. if (of_device_is_compatible(np, "K2-UATA") ||
  837. of_device_is_compatible(np, "shasta-ata"))
  838. return ATA_CBL_PATA80;
  839. return ATA_CBL_PATA40;
  840. }
  841. static void pmac_ide_init_dev(ide_drive_t *drive)
  842. {
  843. ide_hwif_t *hwif = drive->hwif;
  844. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  845. if (on_media_bay(pmif)) {
  846. if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
  847. drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
  848. return;
  849. }
  850. drive->dev_flags |= IDE_DFLAG_NOPROBE;
  851. }
  852. }
  853. static const struct ide_tp_ops pmac_tp_ops = {
  854. .exec_command = pmac_exec_command,
  855. .read_status = ide_read_status,
  856. .read_altstatus = ide_read_altstatus,
  857. .write_devctl = pmac_write_devctl,
  858. .dev_select = pmac_dev_select,
  859. .tf_load = ide_tf_load,
  860. .tf_read = ide_tf_read,
  861. .input_data = ide_input_data,
  862. .output_data = ide_output_data,
  863. };
  864. static const struct ide_tp_ops pmac_ata6_tp_ops = {
  865. .exec_command = pmac_exec_command,
  866. .read_status = ide_read_status,
  867. .read_altstatus = ide_read_altstatus,
  868. .write_devctl = pmac_write_devctl,
  869. .dev_select = pmac_kauai_dev_select,
  870. .tf_load = ide_tf_load,
  871. .tf_read = ide_tf_read,
  872. .input_data = ide_input_data,
  873. .output_data = ide_output_data,
  874. };
  875. static const struct ide_port_ops pmac_ide_ata4_port_ops = {
  876. .init_dev = pmac_ide_init_dev,
  877. .set_pio_mode = pmac_ide_set_pio_mode,
  878. .set_dma_mode = pmac_ide_set_dma_mode,
  879. .cable_detect = pmac_ide_cable_detect,
  880. };
  881. static const struct ide_port_ops pmac_ide_port_ops = {
  882. .init_dev = pmac_ide_init_dev,
  883. .set_pio_mode = pmac_ide_set_pio_mode,
  884. .set_dma_mode = pmac_ide_set_dma_mode,
  885. };
  886. static const struct ide_dma_ops pmac_dma_ops;
  887. static const struct ide_port_info pmac_port_info = {
  888. .name = DRV_NAME,
  889. .init_dma = pmac_ide_init_dma,
  890. .chipset = ide_pmac,
  891. .tp_ops = &pmac_tp_ops,
  892. .port_ops = &pmac_ide_port_ops,
  893. .dma_ops = &pmac_dma_ops,
  894. .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
  895. IDE_HFLAG_POST_SET_MODE |
  896. IDE_HFLAG_MMIO |
  897. IDE_HFLAG_UNMASK_IRQS,
  898. .pio_mask = ATA_PIO4,
  899. .mwdma_mask = ATA_MWDMA2,
  900. };
  901. /*
  902. * Setup, register & probe an IDE channel driven by this driver, this is
  903. * called by one of the 2 probe functions (macio or PCI).
  904. */
  905. static int pmac_ide_setup_device(pmac_ide_hwif_t *pmif, struct ide_hw *hw)
  906. {
  907. struct device_node *np = pmif->node;
  908. const int *bidp;
  909. struct ide_host *host;
  910. struct ide_hw *hws[] = { hw };
  911. struct ide_port_info d = pmac_port_info;
  912. int rc;
  913. pmif->broken_dma = pmif->broken_dma_warn = 0;
  914. if (of_device_is_compatible(np, "shasta-ata")) {
  915. pmif->kind = controller_sh_ata6;
  916. d.tp_ops = &pmac_ata6_tp_ops;
  917. d.port_ops = &pmac_ide_ata4_port_ops;
  918. d.udma_mask = ATA_UDMA6;
  919. } else if (of_device_is_compatible(np, "kauai-ata")) {
  920. pmif->kind = controller_un_ata6;
  921. d.tp_ops = &pmac_ata6_tp_ops;
  922. d.port_ops = &pmac_ide_ata4_port_ops;
  923. d.udma_mask = ATA_UDMA5;
  924. } else if (of_device_is_compatible(np, "K2-UATA")) {
  925. pmif->kind = controller_k2_ata6;
  926. d.tp_ops = &pmac_ata6_tp_ops;
  927. d.port_ops = &pmac_ide_ata4_port_ops;
  928. d.udma_mask = ATA_UDMA5;
  929. } else if (of_device_is_compatible(np, "keylargo-ata")) {
  930. if (of_node_name_eq(np, "ata-4")) {
  931. pmif->kind = controller_kl_ata4;
  932. d.port_ops = &pmac_ide_ata4_port_ops;
  933. d.udma_mask = ATA_UDMA4;
  934. } else
  935. pmif->kind = controller_kl_ata3;
  936. } else if (of_device_is_compatible(np, "heathrow-ata")) {
  937. pmif->kind = controller_heathrow;
  938. } else {
  939. pmif->kind = controller_ohare;
  940. pmif->broken_dma = 1;
  941. }
  942. bidp = of_get_property(np, "AAPL,bus-id", NULL);
  943. pmif->aapl_bus_id = bidp ? *bidp : 0;
  944. /* On Kauai-type controllers, we make sure the FCR is correct */
  945. if (pmif->kauai_fcr)
  946. writel(KAUAI_FCR_UATA_MAGIC |
  947. KAUAI_FCR_UATA_RESET_N |
  948. KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
  949. /* Make sure we have sane timings */
  950. sanitize_timings(pmif);
  951. /* If we are on a media bay, wait for it to settle and lock it */
  952. if (pmif->mdev)
  953. lock_media_bay(pmif->mdev->media_bay);
  954. host = ide_host_alloc(&d, hws, 1);
  955. if (host == NULL) {
  956. rc = -ENOMEM;
  957. goto bail;
  958. }
  959. pmif->hwif = host->ports[0];
  960. if (on_media_bay(pmif)) {
  961. /* Fixup bus ID for media bay */
  962. if (!bidp)
  963. pmif->aapl_bus_id = 1;
  964. } else if (pmif->kind == controller_ohare) {
  965. /* The code below is having trouble on some ohare machines
  966. * (timing related ?). Until I can put my hand on one of these
  967. * units, I keep the old way
  968. */
  969. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
  970. } else {
  971. /* This is necessary to enable IDE when net-booting */
  972. ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
  973. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
  974. msleep(10);
  975. ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
  976. msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
  977. }
  978. printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
  979. "bus ID %d%s, irq %d\n", model_name[pmif->kind],
  980. pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
  981. on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
  982. rc = ide_host_register(host, &d, hws);
  983. if (rc)
  984. pmif->hwif = NULL;
  985. if (pmif->mdev)
  986. unlock_media_bay(pmif->mdev->media_bay);
  987. bail:
  988. if (rc && host)
  989. ide_host_free(host);
  990. return rc;
  991. }
  992. static void pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
  993. {
  994. int i;
  995. for (i = 0; i < 8; ++i)
  996. hw->io_ports_array[i] = base + i * 0x10;
  997. hw->io_ports.ctl_addr = base + 0x160;
  998. }
  999. /*
  1000. * Attach to a macio probed interface
  1001. */
  1002. static int pmac_ide_macio_attach(struct macio_dev *mdev,
  1003. const struct of_device_id *match)
  1004. {
  1005. void __iomem *base;
  1006. unsigned long regbase;
  1007. pmac_ide_hwif_t *pmif;
  1008. int irq, rc;
  1009. struct ide_hw hw;
  1010. pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
  1011. if (pmif == NULL)
  1012. return -ENOMEM;
  1013. if (macio_resource_count(mdev) == 0) {
  1014. printk(KERN_WARNING "ide-pmac: no address for %pOF\n",
  1015. mdev->ofdev.dev.of_node);
  1016. rc = -ENXIO;
  1017. goto out_free_pmif;
  1018. }
  1019. /* Request memory resource for IO ports */
  1020. if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
  1021. printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
  1022. "%pOF!\n", mdev->ofdev.dev.of_node);
  1023. rc = -EBUSY;
  1024. goto out_free_pmif;
  1025. }
  1026. /* XXX This is bogus. Should be fixed in the registry by checking
  1027. * the kind of host interrupt controller, a bit like gatwick
  1028. * fixes in irq.c. That works well enough for the single case
  1029. * where that happens though...
  1030. */
  1031. if (macio_irq_count(mdev) == 0) {
  1032. printk(KERN_WARNING "ide-pmac: no intrs for device %pOF, using "
  1033. "13\n", mdev->ofdev.dev.of_node);
  1034. irq = irq_create_mapping(NULL, 13);
  1035. } else
  1036. irq = macio_irq(mdev, 0);
  1037. base = ioremap(macio_resource_start(mdev, 0), 0x400);
  1038. regbase = (unsigned long) base;
  1039. pmif->mdev = mdev;
  1040. pmif->node = mdev->ofdev.dev.of_node;
  1041. pmif->regbase = regbase;
  1042. pmif->irq = irq;
  1043. pmif->kauai_fcr = NULL;
  1044. if (macio_resource_count(mdev) >= 2) {
  1045. if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
  1046. printk(KERN_WARNING "ide-pmac: can't request DMA "
  1047. "resource for %pOF!\n",
  1048. mdev->ofdev.dev.of_node);
  1049. else
  1050. pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
  1051. } else
  1052. pmif->dma_regs = NULL;
  1053. dev_set_drvdata(&mdev->ofdev.dev, pmif);
  1054. memset(&hw, 0, sizeof(hw));
  1055. pmac_ide_init_ports(&hw, pmif->regbase);
  1056. hw.irq = irq;
  1057. hw.dev = &mdev->bus->pdev->dev;
  1058. hw.parent = &mdev->ofdev.dev;
  1059. rc = pmac_ide_setup_device(pmif, &hw);
  1060. if (rc != 0) {
  1061. /* The inteface is released to the common IDE layer */
  1062. dev_set_drvdata(&mdev->ofdev.dev, NULL);
  1063. iounmap(base);
  1064. if (pmif->dma_regs) {
  1065. iounmap(pmif->dma_regs);
  1066. macio_release_resource(mdev, 1);
  1067. }
  1068. macio_release_resource(mdev, 0);
  1069. kfree(pmif);
  1070. }
  1071. return rc;
  1072. out_free_pmif:
  1073. kfree(pmif);
  1074. return rc;
  1075. }
  1076. static int
  1077. pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
  1078. {
  1079. pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
  1080. int rc = 0;
  1081. if (mesg.event != mdev->ofdev.dev.power.power_state.event
  1082. && (mesg.event & PM_EVENT_SLEEP)) {
  1083. rc = pmac_ide_do_suspend(pmif);
  1084. if (rc == 0)
  1085. mdev->ofdev.dev.power.power_state = mesg;
  1086. }
  1087. return rc;
  1088. }
  1089. static int
  1090. pmac_ide_macio_resume(struct macio_dev *mdev)
  1091. {
  1092. pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
  1093. int rc = 0;
  1094. if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
  1095. rc = pmac_ide_do_resume(pmif);
  1096. if (rc == 0)
  1097. mdev->ofdev.dev.power.power_state = PMSG_ON;
  1098. }
  1099. return rc;
  1100. }
  1101. /*
  1102. * Attach to a PCI probed interface
  1103. */
  1104. static int pmac_ide_pci_attach(struct pci_dev *pdev,
  1105. const struct pci_device_id *id)
  1106. {
  1107. struct device_node *np;
  1108. pmac_ide_hwif_t *pmif;
  1109. void __iomem *base;
  1110. unsigned long rbase, rlen;
  1111. int rc;
  1112. struct ide_hw hw;
  1113. np = pci_device_to_OF_node(pdev);
  1114. if (np == NULL) {
  1115. printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
  1116. return -ENODEV;
  1117. }
  1118. pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
  1119. if (pmif == NULL)
  1120. return -ENOMEM;
  1121. if (pci_enable_device(pdev)) {
  1122. printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
  1123. "%pOF\n", np);
  1124. rc = -ENXIO;
  1125. goto out_free_pmif;
  1126. }
  1127. pci_set_master(pdev);
  1128. if (pci_request_regions(pdev, "Kauai ATA")) {
  1129. printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
  1130. "%pOF\n", np);
  1131. rc = -ENXIO;
  1132. goto out_free_pmif;
  1133. }
  1134. pmif->mdev = NULL;
  1135. pmif->node = np;
  1136. rbase = pci_resource_start(pdev, 0);
  1137. rlen = pci_resource_len(pdev, 0);
  1138. base = ioremap(rbase, rlen);
  1139. pmif->regbase = (unsigned long) base + 0x2000;
  1140. pmif->dma_regs = base + 0x1000;
  1141. pmif->kauai_fcr = base;
  1142. pmif->irq = pdev->irq;
  1143. pci_set_drvdata(pdev, pmif);
  1144. memset(&hw, 0, sizeof(hw));
  1145. pmac_ide_init_ports(&hw, pmif->regbase);
  1146. hw.irq = pdev->irq;
  1147. hw.dev = &pdev->dev;
  1148. rc = pmac_ide_setup_device(pmif, &hw);
  1149. if (rc != 0) {
  1150. /* The inteface is released to the common IDE layer */
  1151. iounmap(base);
  1152. pci_release_regions(pdev);
  1153. kfree(pmif);
  1154. }
  1155. return rc;
  1156. out_free_pmif:
  1157. kfree(pmif);
  1158. return rc;
  1159. }
  1160. static int
  1161. pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
  1162. {
  1163. pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
  1164. int rc = 0;
  1165. if (mesg.event != pdev->dev.power.power_state.event
  1166. && (mesg.event & PM_EVENT_SLEEP)) {
  1167. rc = pmac_ide_do_suspend(pmif);
  1168. if (rc == 0)
  1169. pdev->dev.power.power_state = mesg;
  1170. }
  1171. return rc;
  1172. }
  1173. static int
  1174. pmac_ide_pci_resume(struct pci_dev *pdev)
  1175. {
  1176. pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
  1177. int rc = 0;
  1178. if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
  1179. rc = pmac_ide_do_resume(pmif);
  1180. if (rc == 0)
  1181. pdev->dev.power.power_state = PMSG_ON;
  1182. }
  1183. return rc;
  1184. }
  1185. #ifdef CONFIG_PMAC_MEDIABAY
  1186. static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
  1187. {
  1188. pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
  1189. switch(mb_state) {
  1190. case MB_CD:
  1191. if (!pmif->hwif->present)
  1192. ide_port_scan(pmif->hwif);
  1193. break;
  1194. default:
  1195. if (pmif->hwif->present)
  1196. ide_port_unregister_devices(pmif->hwif);
  1197. }
  1198. }
  1199. #endif /* CONFIG_PMAC_MEDIABAY */
  1200. static struct of_device_id pmac_ide_macio_match[] =
  1201. {
  1202. {
  1203. .name = "IDE",
  1204. },
  1205. {
  1206. .name = "ATA",
  1207. },
  1208. {
  1209. .type = "ide",
  1210. },
  1211. {
  1212. .type = "ata",
  1213. },
  1214. {},
  1215. };
  1216. static struct macio_driver pmac_ide_macio_driver =
  1217. {
  1218. .driver = {
  1219. .name = "ide-pmac",
  1220. .owner = THIS_MODULE,
  1221. .of_match_table = pmac_ide_macio_match,
  1222. },
  1223. .probe = pmac_ide_macio_attach,
  1224. .suspend = pmac_ide_macio_suspend,
  1225. .resume = pmac_ide_macio_resume,
  1226. #ifdef CONFIG_PMAC_MEDIABAY
  1227. .mediabay_event = pmac_ide_macio_mb_event,
  1228. #endif
  1229. };
  1230. static const struct pci_device_id pmac_ide_pci_match[] = {
  1231. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
  1232. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
  1233. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
  1234. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
  1235. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
  1236. {},
  1237. };
  1238. static struct pci_driver pmac_ide_pci_driver = {
  1239. .name = "ide-pmac",
  1240. .id_table = pmac_ide_pci_match,
  1241. .probe = pmac_ide_pci_attach,
  1242. .suspend = pmac_ide_pci_suspend,
  1243. .resume = pmac_ide_pci_resume,
  1244. };
  1245. MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
  1246. int __init pmac_ide_probe(void)
  1247. {
  1248. int error;
  1249. if (!machine_is(powermac))
  1250. return -ENODEV;
  1251. #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
  1252. error = pci_register_driver(&pmac_ide_pci_driver);
  1253. if (error)
  1254. goto out;
  1255. error = macio_register_driver(&pmac_ide_macio_driver);
  1256. if (error) {
  1257. pci_unregister_driver(&pmac_ide_pci_driver);
  1258. goto out;
  1259. }
  1260. #else
  1261. error = macio_register_driver(&pmac_ide_macio_driver);
  1262. if (error)
  1263. goto out;
  1264. error = pci_register_driver(&pmac_ide_pci_driver);
  1265. if (error) {
  1266. macio_unregister_driver(&pmac_ide_macio_driver);
  1267. goto out;
  1268. }
  1269. #endif
  1270. out:
  1271. return error;
  1272. }
  1273. /*
  1274. * pmac_ide_build_dmatable builds the DBDMA command list
  1275. * for a transfer and sets the DBDMA channel to point to it.
  1276. */
  1277. static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
  1278. {
  1279. ide_hwif_t *hwif = drive->hwif;
  1280. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1281. struct dbdma_cmd *table;
  1282. volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
  1283. struct scatterlist *sg;
  1284. int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
  1285. int i = cmd->sg_nents, count = 0;
  1286. /* DMA table is already aligned */
  1287. table = (struct dbdma_cmd *) pmif->dma_table_cpu;
  1288. /* Make sure DMA controller is stopped (necessary ?) */
  1289. writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
  1290. while (readl(&dma->status) & RUN)
  1291. udelay(1);
  1292. /* Build DBDMA commands list */
  1293. sg = hwif->sg_table;
  1294. while (i && sg_dma_len(sg)) {
  1295. u32 cur_addr;
  1296. u32 cur_len;
  1297. cur_addr = sg_dma_address(sg);
  1298. cur_len = sg_dma_len(sg);
  1299. if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
  1300. if (pmif->broken_dma_warn == 0) {
  1301. printk(KERN_WARNING "%s: DMA on non aligned address, "
  1302. "switching to PIO on Ohare chipset\n", drive->name);
  1303. pmif->broken_dma_warn = 1;
  1304. }
  1305. return 0;
  1306. }
  1307. while (cur_len) {
  1308. unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
  1309. if (count++ >= MAX_DCMDS) {
  1310. printk(KERN_WARNING "%s: DMA table too small\n",
  1311. drive->name);
  1312. return 0;
  1313. }
  1314. table->command = cpu_to_le16(wr? OUTPUT_MORE: INPUT_MORE);
  1315. table->req_count = cpu_to_le16(tc);
  1316. table->phy_addr = cpu_to_le32(cur_addr);
  1317. table->cmd_dep = 0;
  1318. table->xfer_status = 0;
  1319. table->res_count = 0;
  1320. cur_addr += tc;
  1321. cur_len -= tc;
  1322. ++table;
  1323. }
  1324. sg = sg_next(sg);
  1325. i--;
  1326. }
  1327. /* convert the last command to an input/output last command */
  1328. if (count) {
  1329. table[-1].command = cpu_to_le16(wr? OUTPUT_LAST: INPUT_LAST);
  1330. /* add the stop command to the end of the list */
  1331. memset(table, 0, sizeof(struct dbdma_cmd));
  1332. table->command = cpu_to_le16(DBDMA_STOP);
  1333. mb();
  1334. writel(hwif->dmatable_dma, &dma->cmdptr);
  1335. return 1;
  1336. }
  1337. printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
  1338. return 0; /* revert to PIO for this request */
  1339. }
  1340. /*
  1341. * Prepare a DMA transfer. We build the DMA table, adjust the timings for
  1342. * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
  1343. */
  1344. static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
  1345. {
  1346. ide_hwif_t *hwif = drive->hwif;
  1347. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1348. u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
  1349. u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
  1350. if (pmac_ide_build_dmatable(drive, cmd) == 0)
  1351. return 1;
  1352. /* Apple adds 60ns to wrDataSetup on reads */
  1353. if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
  1354. writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
  1355. PMAC_IDE_REG(IDE_TIMING_CONFIG));
  1356. (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
  1357. }
  1358. return 0;
  1359. }
  1360. /*
  1361. * Kick the DMA controller into life after the DMA command has been issued
  1362. * to the drive.
  1363. */
  1364. static void
  1365. pmac_ide_dma_start(ide_drive_t *drive)
  1366. {
  1367. ide_hwif_t *hwif = drive->hwif;
  1368. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1369. volatile struct dbdma_regs __iomem *dma;
  1370. dma = pmif->dma_regs;
  1371. writel((RUN << 16) | RUN, &dma->control);
  1372. /* Make sure it gets to the controller right now */
  1373. (void)readl(&dma->control);
  1374. }
  1375. /*
  1376. * After a DMA transfer, make sure the controller is stopped
  1377. */
  1378. static int
  1379. pmac_ide_dma_end (ide_drive_t *drive)
  1380. {
  1381. ide_hwif_t *hwif = drive->hwif;
  1382. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1383. volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
  1384. u32 dstat;
  1385. dstat = readl(&dma->status);
  1386. writel(((RUN|WAKE|DEAD) << 16), &dma->control);
  1387. /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
  1388. * in theory, but with ATAPI decices doing buffer underruns, that would
  1389. * cause us to disable DMA, which isn't what we want
  1390. */
  1391. return (dstat & (RUN|DEAD)) != RUN;
  1392. }
  1393. /*
  1394. * Check out that the interrupt we got was for us. We can't always know this
  1395. * for sure with those Apple interfaces (well, we could on the recent ones but
  1396. * that's not implemented yet), on the other hand, we don't have shared interrupts
  1397. * so it's not really a problem
  1398. */
  1399. static int
  1400. pmac_ide_dma_test_irq (ide_drive_t *drive)
  1401. {
  1402. ide_hwif_t *hwif = drive->hwif;
  1403. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1404. volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
  1405. unsigned long status, timeout;
  1406. /* We have to things to deal with here:
  1407. *
  1408. * - The dbdma won't stop if the command was started
  1409. * but completed with an error without transferring all
  1410. * datas. This happens when bad blocks are met during
  1411. * a multi-block transfer.
  1412. *
  1413. * - The dbdma fifo hasn't yet finished flushing to
  1414. * to system memory when the disk interrupt occurs.
  1415. *
  1416. */
  1417. /* If ACTIVE is cleared, the STOP command have passed and
  1418. * transfer is complete.
  1419. */
  1420. status = readl(&dma->status);
  1421. if (!(status & ACTIVE))
  1422. return 1;
  1423. /* If dbdma didn't execute the STOP command yet, the
  1424. * active bit is still set. We consider that we aren't
  1425. * sharing interrupts (which is hopefully the case with
  1426. * those controllers) and so we just try to flush the
  1427. * channel for pending data in the fifo
  1428. */
  1429. udelay(1);
  1430. writel((FLUSH << 16) | FLUSH, &dma->control);
  1431. timeout = 0;
  1432. for (;;) {
  1433. udelay(1);
  1434. status = readl(&dma->status);
  1435. if ((status & FLUSH) == 0)
  1436. break;
  1437. if (++timeout > 100) {
  1438. printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
  1439. hwif->index);
  1440. break;
  1441. }
  1442. }
  1443. return 1;
  1444. }
  1445. static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
  1446. {
  1447. }
  1448. static void
  1449. pmac_ide_dma_lost_irq (ide_drive_t *drive)
  1450. {
  1451. ide_hwif_t *hwif = drive->hwif;
  1452. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1453. volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
  1454. unsigned long status = readl(&dma->status);
  1455. printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
  1456. }
  1457. static const struct ide_dma_ops pmac_dma_ops = {
  1458. .dma_host_set = pmac_ide_dma_host_set,
  1459. .dma_setup = pmac_ide_dma_setup,
  1460. .dma_start = pmac_ide_dma_start,
  1461. .dma_end = pmac_ide_dma_end,
  1462. .dma_test_irq = pmac_ide_dma_test_irq,
  1463. .dma_lost_irq = pmac_ide_dma_lost_irq,
  1464. };
  1465. /*
  1466. * Allocate the data structures needed for using DMA with an interface
  1467. * and fill the proper list of functions pointers
  1468. */
  1469. static int pmac_ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
  1470. {
  1471. pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
  1472. struct pci_dev *dev = to_pci_dev(hwif->dev);
  1473. /* We won't need pci_dev if we switch to generic consistent
  1474. * DMA routines ...
  1475. */
  1476. if (dev == NULL || pmif->dma_regs == 0)
  1477. return -ENODEV;
  1478. /*
  1479. * Allocate space for the DBDMA commands.
  1480. * The +2 is +1 for the stop command and +1 to allow for
  1481. * aligning the start address to a multiple of 16 bytes.
  1482. */
  1483. pmif->dma_table_cpu = dma_alloc_coherent(&dev->dev,
  1484. (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
  1485. &hwif->dmatable_dma, GFP_KERNEL);
  1486. if (pmif->dma_table_cpu == NULL) {
  1487. printk(KERN_ERR "%s: unable to allocate DMA command list\n",
  1488. hwif->name);
  1489. return -ENOMEM;
  1490. }
  1491. hwif->sg_max_nents = MAX_DCMDS;
  1492. return 0;
  1493. }
  1494. module_init(pmac_ide_probe);
  1495. MODULE_LICENSE("GPL");