pdc202xx_old.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
  4. * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
  5. * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
  6. *
  7. * Portions Copyright (C) 1999 Promise Technology, Inc.
  8. * Author: Frank Tiernan (frankt@promise.com)
  9. * Released under terms of General Public License
  10. */
  11. #include <linux/types.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/delay.h>
  15. #include <linux/blkdev.h>
  16. #include <linux/pci.h>
  17. #include <linux/init.h>
  18. #include <linux/ide.h>
  19. #include <asm/io.h>
  20. #define DRV_NAME "pdc202xx_old"
  21. static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  22. {
  23. struct pci_dev *dev = to_pci_dev(hwif->dev);
  24. u8 drive_pci = 0x60 + (drive->dn << 2);
  25. const u8 speed = drive->dma_mode;
  26. u8 AP = 0, BP = 0, CP = 0;
  27. u8 TA = 0, TB = 0, TC = 0;
  28. pci_read_config_byte(dev, drive_pci, &AP);
  29. pci_read_config_byte(dev, drive_pci + 1, &BP);
  30. pci_read_config_byte(dev, drive_pci + 2, &CP);
  31. switch(speed) {
  32. case XFER_UDMA_5:
  33. case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
  34. case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
  35. case XFER_UDMA_3:
  36. case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
  37. case XFER_UDMA_0:
  38. case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
  39. case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
  40. case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
  41. case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
  42. case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
  43. case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
  44. case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
  45. case XFER_PIO_0:
  46. default: TA = 0x09; TB = 0x13; break;
  47. }
  48. if (speed < XFER_SW_DMA_0) {
  49. /*
  50. * preserve SYNC_INT / ERDDY_EN bits while clearing
  51. * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
  52. */
  53. AP &= ~0x3f;
  54. if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
  55. AP |= 0x20; /* set IORDY_EN bit */
  56. if (drive->media == ide_disk)
  57. AP |= 0x10; /* set Prefetch_EN bit */
  58. /* clear PB[4:0] bits of register B */
  59. BP &= ~0x1f;
  60. pci_write_config_byte(dev, drive_pci, AP | TA);
  61. pci_write_config_byte(dev, drive_pci + 1, BP | TB);
  62. } else {
  63. /* clear MB[2:0] bits of register B */
  64. BP &= ~0xe0;
  65. /* clear MC[3:0] bits of register C */
  66. CP &= ~0x0f;
  67. pci_write_config_byte(dev, drive_pci + 1, BP | TB);
  68. pci_write_config_byte(dev, drive_pci + 2, CP | TC);
  69. }
  70. }
  71. static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  72. {
  73. drive->dma_mode = drive->pio_mode;
  74. pdc202xx_set_mode(hwif, drive);
  75. }
  76. static int pdc202xx_test_irq(ide_hwif_t *hwif)
  77. {
  78. struct pci_dev *dev = to_pci_dev(hwif->dev);
  79. unsigned long high_16 = pci_resource_start(dev, 4);
  80. u8 sc1d = inb(high_16 + 0x1d);
  81. if (hwif->channel) {
  82. /*
  83. * bit 7: error, bit 6: interrupting,
  84. * bit 5: FIFO full, bit 4: FIFO empty
  85. */
  86. return (sc1d & 0x40) ? 1 : 0;
  87. } else {
  88. /*
  89. * bit 3: error, bit 2: interrupting,
  90. * bit 1: FIFO full, bit 0: FIFO empty
  91. */
  92. return (sc1d & 0x04) ? 1 : 0;
  93. }
  94. }
  95. static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
  96. {
  97. struct pci_dev *dev = to_pci_dev(hwif->dev);
  98. u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
  99. pci_read_config_word(dev, 0x50, &CIS);
  100. return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
  101. }
  102. /*
  103. * Set the control register to use the 66MHz system
  104. * clock for UDMA 3/4/5 mode operation when necessary.
  105. *
  106. * FIXME: this register is shared by both channels, some locking is needed
  107. *
  108. * It may also be possible to leave the 66MHz clock on
  109. * and readjust the timing parameters.
  110. */
  111. static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
  112. {
  113. unsigned long clock_reg = hwif->extra_base + 0x01;
  114. u8 clock = inb(clock_reg);
  115. outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
  116. }
  117. static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
  118. {
  119. unsigned long clock_reg = hwif->extra_base + 0x01;
  120. u8 clock = inb(clock_reg);
  121. outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
  122. }
  123. static void pdc2026x_init_hwif(ide_hwif_t *hwif)
  124. {
  125. pdc_old_disable_66MHz_clock(hwif);
  126. }
  127. static void pdc202xx_dma_start(ide_drive_t *drive)
  128. {
  129. if (drive->current_speed > XFER_UDMA_2)
  130. pdc_old_enable_66MHz_clock(drive->hwif);
  131. if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
  132. ide_hwif_t *hwif = drive->hwif;
  133. struct request *rq = hwif->rq;
  134. unsigned long high_16 = hwif->extra_base - 16;
  135. unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
  136. u32 word_count = 0;
  137. u8 clock = inb(high_16 + 0x11);
  138. outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
  139. word_count = (blk_rq_sectors(rq) << 8);
  140. word_count = (rq_data_dir(rq) == READ) ?
  141. word_count | 0x05000000 :
  142. word_count | 0x06000000;
  143. outl(word_count, atapi_reg);
  144. }
  145. ide_dma_start(drive);
  146. }
  147. static int pdc202xx_dma_end(ide_drive_t *drive)
  148. {
  149. if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
  150. ide_hwif_t *hwif = drive->hwif;
  151. unsigned long high_16 = hwif->extra_base - 16;
  152. unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
  153. u8 clock = 0;
  154. outl(0, atapi_reg); /* zero out extra */
  155. clock = inb(high_16 + 0x11);
  156. outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
  157. }
  158. if (drive->current_speed > XFER_UDMA_2)
  159. pdc_old_disable_66MHz_clock(drive->hwif);
  160. return ide_dma_end(drive);
  161. }
  162. static int init_chipset_pdc202xx(struct pci_dev *dev)
  163. {
  164. unsigned long dmabase = pci_resource_start(dev, 4);
  165. u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
  166. if (dmabase == 0)
  167. goto out;
  168. udma_speed_flag = inb(dmabase | 0x1f);
  169. primary_mode = inb(dmabase | 0x1a);
  170. secondary_mode = inb(dmabase | 0x1b);
  171. printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
  172. "Primary %s Mode " \
  173. "Secondary %s Mode.\n", pci_name(dev),
  174. (udma_speed_flag & 1) ? "EN" : "DIS",
  175. (primary_mode & 1) ? "MASTER" : "PCI",
  176. (secondary_mode & 1) ? "MASTER" : "PCI" );
  177. if (!(udma_speed_flag & 1)) {
  178. printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
  179. pci_name(dev), udma_speed_flag,
  180. (udma_speed_flag|1));
  181. outb(udma_speed_flag | 1, dmabase | 0x1f);
  182. printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
  183. }
  184. out:
  185. return 0;
  186. }
  187. static void pdc202ata4_fixup_irq(struct pci_dev *dev, const char *name)
  188. {
  189. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
  190. u8 irq = 0, irq2 = 0;
  191. pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  192. /* 0xbc */
  193. pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
  194. if (irq != irq2) {
  195. pci_write_config_byte(dev,
  196. (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
  197. printk(KERN_INFO "%s %s: PCI config space interrupt "
  198. "mirror fixed\n", name, pci_name(dev));
  199. }
  200. }
  201. }
  202. #define IDE_HFLAGS_PDC202XX \
  203. (IDE_HFLAG_ERROR_STOPS_FIFO | \
  204. IDE_HFLAG_OFF_BOARD)
  205. static const struct ide_port_ops pdc20246_port_ops = {
  206. .set_pio_mode = pdc202xx_set_pio_mode,
  207. .set_dma_mode = pdc202xx_set_mode,
  208. .test_irq = pdc202xx_test_irq,
  209. };
  210. static const struct ide_port_ops pdc2026x_port_ops = {
  211. .set_pio_mode = pdc202xx_set_pio_mode,
  212. .set_dma_mode = pdc202xx_set_mode,
  213. .test_irq = pdc202xx_test_irq,
  214. .cable_detect = pdc2026x_cable_detect,
  215. };
  216. static const struct ide_dma_ops pdc2026x_dma_ops = {
  217. .dma_host_set = ide_dma_host_set,
  218. .dma_setup = ide_dma_setup,
  219. .dma_start = pdc202xx_dma_start,
  220. .dma_end = pdc202xx_dma_end,
  221. .dma_test_irq = ide_dma_test_irq,
  222. .dma_lost_irq = ide_dma_lost_irq,
  223. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  224. .dma_sff_read_status = ide_dma_sff_read_status,
  225. };
  226. #define DECLARE_PDC2026X_DEV(udma, sectors) \
  227. { \
  228. .name = DRV_NAME, \
  229. .init_chipset = init_chipset_pdc202xx, \
  230. .init_hwif = pdc2026x_init_hwif, \
  231. .port_ops = &pdc2026x_port_ops, \
  232. .dma_ops = &pdc2026x_dma_ops, \
  233. .host_flags = IDE_HFLAGS_PDC202XX, \
  234. .pio_mask = ATA_PIO4, \
  235. .mwdma_mask = ATA_MWDMA2, \
  236. .udma_mask = udma, \
  237. .max_sectors = sectors, \
  238. }
  239. static const struct ide_port_info pdc202xx_chipsets[] = {
  240. { /* 0: PDC20246 */
  241. .name = DRV_NAME,
  242. .init_chipset = init_chipset_pdc202xx,
  243. .port_ops = &pdc20246_port_ops,
  244. .dma_ops = &sff_dma_ops,
  245. .host_flags = IDE_HFLAGS_PDC202XX,
  246. .pio_mask = ATA_PIO4,
  247. .mwdma_mask = ATA_MWDMA2,
  248. .udma_mask = ATA_UDMA2,
  249. },
  250. /* 1: PDC2026{2,3} */
  251. DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
  252. /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
  253. DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
  254. };
  255. /**
  256. * pdc202xx_init_one - called when a PDC202xx is found
  257. * @dev: the pdc202xx device
  258. * @id: the matching pci id
  259. *
  260. * Called when the PCI registration layer (or the IDE initialization)
  261. * finds a device matching our IDE device tables.
  262. */
  263. static int pdc202xx_init_one(struct pci_dev *dev,
  264. const struct pci_device_id *id)
  265. {
  266. const struct ide_port_info *d;
  267. u8 idx = id->driver_data;
  268. d = &pdc202xx_chipsets[idx];
  269. if (idx < 2)
  270. pdc202ata4_fixup_irq(dev, d->name);
  271. if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
  272. struct pci_dev *bridge = dev->bus->self;
  273. if (bridge &&
  274. bridge->vendor == PCI_VENDOR_ID_INTEL &&
  275. (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
  276. bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
  277. printk(KERN_INFO DRV_NAME " %s: skipping Promise "
  278. "PDC20265 attached to I2O RAID controller\n",
  279. pci_name(dev));
  280. return -ENODEV;
  281. }
  282. }
  283. return ide_pci_init_one(dev, d, NULL);
  284. }
  285. static const struct pci_device_id pdc202xx_pci_tbl[] = {
  286. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
  287. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
  288. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
  289. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
  290. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
  291. { 0, },
  292. };
  293. MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
  294. static struct pci_driver pdc202xx_pci_driver = {
  295. .name = "Promise_Old_IDE",
  296. .id_table = pdc202xx_pci_tbl,
  297. .probe = pdc202xx_init_one,
  298. .remove = ide_pci_remove,
  299. .suspend = ide_pci_suspend,
  300. .resume = ide_pci_resume,
  301. };
  302. static int __init pdc202xx_ide_init(void)
  303. {
  304. return ide_pci_register_driver(&pdc202xx_pci_driver);
  305. }
  306. static void __exit pdc202xx_ide_exit(void)
  307. {
  308. pci_unregister_driver(&pdc202xx_pci_driver);
  309. }
  310. module_init(pdc202xx_ide_init);
  311. module_exit(pdc202xx_ide_exit);
  312. MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
  313. MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
  314. MODULE_LICENSE("GPL");