palm_bk3710.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Palmchip bk3710 IDE controller
  4. *
  5. * Copyright (C) 2006 Texas Instruments.
  6. * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  7. *
  8. * ----------------------------------------------------------------------------
  9. *
  10. * ----------------------------------------------------------------------------
  11. */
  12. #include <linux/types.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ioport.h>
  16. #include <linux/ide.h>
  17. #include <linux/delay.h>
  18. #include <linux/init.h>
  19. #include <linux/clk.h>
  20. #include <linux/platform_device.h>
  21. /* Offset of the primary interface registers */
  22. #define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
  23. /* Primary Control Offset */
  24. #define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
  25. #define BK3710_BMICP 0x00
  26. #define BK3710_BMISP 0x02
  27. #define BK3710_BMIDTP 0x04
  28. #define BK3710_IDETIMP 0x40
  29. #define BK3710_IDESTATUS 0x47
  30. #define BK3710_UDMACTL 0x48
  31. #define BK3710_MISCCTL 0x50
  32. #define BK3710_REGSTB 0x54
  33. #define BK3710_REGRCVR 0x58
  34. #define BK3710_DATSTB 0x5C
  35. #define BK3710_DATRCVR 0x60
  36. #define BK3710_DMASTB 0x64
  37. #define BK3710_DMARCVR 0x68
  38. #define BK3710_UDMASTB 0x6C
  39. #define BK3710_UDMATRP 0x70
  40. #define BK3710_UDMAENV 0x74
  41. #define BK3710_IORDYTMP 0x78
  42. static unsigned ideclk_period; /* in nanoseconds */
  43. struct palm_bk3710_udmatiming {
  44. unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
  45. unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
  46. /* tENV is always a minimum of 20 nsec */
  47. };
  48. static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
  49. { 160, 240 / 2 }, /* UDMA Mode 0 */
  50. { 125, 160 / 2 }, /* UDMA Mode 1 */
  51. { 100, 120 / 2 }, /* UDMA Mode 2 */
  52. { 100, 90 / 2 }, /* UDMA Mode 3 */
  53. { 100, 60 / 2 }, /* UDMA Mode 4 */
  54. { 85, 40 / 2 }, /* UDMA Mode 5 */
  55. };
  56. static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
  57. unsigned int mode)
  58. {
  59. u8 tenv, trp, t0;
  60. u32 val32;
  61. u16 val16;
  62. /* DMA Data Setup */
  63. t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
  64. ideclk_period) - 1;
  65. tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
  66. trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
  67. ideclk_period) - 1;
  68. /* udmastb Ultra DMA Access Strobe Width */
  69. val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
  70. val32 |= (t0 << (dev ? 8 : 0));
  71. writel(val32, base + BK3710_UDMASTB);
  72. /* udmatrp Ultra DMA Ready to Pause Time */
  73. val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
  74. val32 |= (trp << (dev ? 8 : 0));
  75. writel(val32, base + BK3710_UDMATRP);
  76. /* udmaenv Ultra DMA envelop Time */
  77. val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
  78. val32 |= (tenv << (dev ? 8 : 0));
  79. writel(val32, base + BK3710_UDMAENV);
  80. /* Enable UDMA for Device */
  81. val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
  82. writew(val16, base + BK3710_UDMACTL);
  83. }
  84. static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
  85. unsigned short min_cycle,
  86. unsigned int mode)
  87. {
  88. u8 td, tkw, t0;
  89. u32 val32;
  90. u16 val16;
  91. struct ide_timing *t;
  92. int cycletime;
  93. t = ide_timing_find_mode(mode);
  94. cycletime = max_t(int, t->cycle, min_cycle);
  95. /* DMA Data Setup */
  96. t0 = DIV_ROUND_UP(cycletime, ideclk_period);
  97. td = DIV_ROUND_UP(t->active, ideclk_period);
  98. tkw = t0 - td - 1;
  99. td -= 1;
  100. val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
  101. val32 |= (td << (dev ? 8 : 0));
  102. writel(val32, base + BK3710_DMASTB);
  103. val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
  104. val32 |= (tkw << (dev ? 8 : 0));
  105. writel(val32, base + BK3710_DMARCVR);
  106. /* Disable UDMA for Device */
  107. val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
  108. writew(val16, base + BK3710_UDMACTL);
  109. }
  110. static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
  111. unsigned int dev, unsigned int cycletime,
  112. unsigned int mode)
  113. {
  114. u8 t2, t2i, t0;
  115. u32 val32;
  116. struct ide_timing *t;
  117. t = ide_timing_find_mode(XFER_PIO_0 + mode);
  118. /* PIO Data Setup */
  119. t0 = DIV_ROUND_UP(cycletime, ideclk_period);
  120. t2 = DIV_ROUND_UP(t->active, ideclk_period);
  121. t2i = t0 - t2 - 1;
  122. t2 -= 1;
  123. val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
  124. val32 |= (t2 << (dev ? 8 : 0));
  125. writel(val32, base + BK3710_DATSTB);
  126. val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
  127. val32 |= (t2i << (dev ? 8 : 0));
  128. writel(val32, base + BK3710_DATRCVR);
  129. if (mate) {
  130. u8 mode2 = mate->pio_mode - XFER_PIO_0;
  131. if (mode2 < mode)
  132. mode = mode2;
  133. }
  134. /* TASKFILE Setup */
  135. t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
  136. t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
  137. t2i = t0 - t2 - 1;
  138. t2 -= 1;
  139. val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
  140. val32 |= (t2 << (dev ? 8 : 0));
  141. writel(val32, base + BK3710_REGSTB);
  142. val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
  143. val32 |= (t2i << (dev ? 8 : 0));
  144. writel(val32, base + BK3710_REGRCVR);
  145. }
  146. static void palm_bk3710_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  147. {
  148. int is_slave = drive->dn & 1;
  149. void __iomem *base = (void __iomem *)hwif->dma_base;
  150. const u8 xferspeed = drive->dma_mode;
  151. if (xferspeed >= XFER_UDMA_0) {
  152. palm_bk3710_setudmamode(base, is_slave,
  153. xferspeed - XFER_UDMA_0);
  154. } else {
  155. palm_bk3710_setdmamode(base, is_slave,
  156. drive->id[ATA_ID_EIDE_DMA_MIN],
  157. xferspeed);
  158. }
  159. }
  160. static void palm_bk3710_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  161. {
  162. unsigned int cycle_time;
  163. int is_slave = drive->dn & 1;
  164. ide_drive_t *mate;
  165. void __iomem *base = (void __iomem *)hwif->dma_base;
  166. const u8 pio = drive->pio_mode - XFER_PIO_0;
  167. /*
  168. * Obtain the drive PIO data for tuning the Palm Chip registers
  169. */
  170. cycle_time = ide_pio_cycle_time(drive, pio);
  171. mate = ide_get_pair_dev(drive);
  172. palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
  173. }
  174. static void palm_bk3710_chipinit(void __iomem *base)
  175. {
  176. /*
  177. * REVISIT: the ATA reset signal needs to be managed through a
  178. * GPIO, which means it should come from platform_data. Until
  179. * we get and use such information, we have to trust that things
  180. * have been reset before we get here.
  181. */
  182. /*
  183. * Program the IDETIMP Register Value based on the following assumptions
  184. *
  185. * (ATA_IDETIMP_IDEEN , ENABLE ) |
  186. * (ATA_IDETIMP_PREPOST1 , DISABLE) |
  187. * (ATA_IDETIMP_PREPOST0 , DISABLE) |
  188. *
  189. * DM6446 silicon rev 2.1 and earlier have no observed net benefit
  190. * from enabling prefetch/postwrite.
  191. */
  192. writew(BIT(15), base + BK3710_IDETIMP);
  193. /*
  194. * UDMACTL Ultra-ATA DMA Control
  195. * (ATA_UDMACTL_UDMAP1 , 0 ) |
  196. * (ATA_UDMACTL_UDMAP0 , 0 )
  197. *
  198. */
  199. writew(0, base + BK3710_UDMACTL);
  200. /*
  201. * MISCCTL Miscellaneous Conrol Register
  202. * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
  203. * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
  204. * (ATA_MISCCTL_TIMORIDE , 1)
  205. */
  206. writel(0x001, base + BK3710_MISCCTL);
  207. /*
  208. * IORDYTMP IORDY Timer for Primary Register
  209. * (ATA_IORDYTMP_IORDYTMP , 0xffff )
  210. */
  211. writel(0xFFFF, base + BK3710_IORDYTMP);
  212. /*
  213. * Configure BMISP Register
  214. * (ATA_BMISP_DMAEN1 , DISABLE ) |
  215. * (ATA_BMISP_DMAEN0 , DISABLE ) |
  216. * (ATA_BMISP_IORDYINT , CLEAR) |
  217. * (ATA_BMISP_INTRSTAT , CLEAR) |
  218. * (ATA_BMISP_DMAERROR , CLEAR)
  219. */
  220. writew(0, base + BK3710_BMISP);
  221. palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
  222. palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
  223. }
  224. static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
  225. {
  226. return ATA_CBL_PATA80;
  227. }
  228. static int palm_bk3710_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
  229. {
  230. printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
  231. if (ide_allocate_dma_engine(hwif))
  232. return -1;
  233. hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
  234. return 0;
  235. }
  236. static const struct ide_port_ops palm_bk3710_ports_ops = {
  237. .set_pio_mode = palm_bk3710_set_pio_mode,
  238. .set_dma_mode = palm_bk3710_set_dma_mode,
  239. .cable_detect = palm_bk3710_cable_detect,
  240. };
  241. static struct ide_port_info palm_bk3710_port_info __initdata = {
  242. .init_dma = palm_bk3710_init_dma,
  243. .port_ops = &palm_bk3710_ports_ops,
  244. .dma_ops = &sff_dma_ops,
  245. .host_flags = IDE_HFLAG_MMIO,
  246. .pio_mask = ATA_PIO4,
  247. .mwdma_mask = ATA_MWDMA2,
  248. .chipset = ide_palm3710,
  249. };
  250. static int __init palm_bk3710_probe(struct platform_device *pdev)
  251. {
  252. struct clk *clk;
  253. struct resource *mem, *irq;
  254. void __iomem *base;
  255. unsigned long rate, mem_size;
  256. int i, rc;
  257. struct ide_hw hw, *hws[] = { &hw };
  258. clk = clk_get(&pdev->dev, NULL);
  259. if (IS_ERR(clk))
  260. return -ENODEV;
  261. clk_enable(clk);
  262. rate = clk_get_rate(clk);
  263. if (!rate)
  264. return -EINVAL;
  265. /* NOTE: round *down* to meet minimum timings; we count in clocks */
  266. ideclk_period = 1000000000UL / rate;
  267. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  268. if (mem == NULL) {
  269. printk(KERN_ERR "failed to get memory region resource\n");
  270. return -ENODEV;
  271. }
  272. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  273. if (irq == NULL) {
  274. printk(KERN_ERR "failed to get IRQ resource\n");
  275. return -ENODEV;
  276. }
  277. mem_size = resource_size(mem);
  278. if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) {
  279. printk(KERN_ERR "failed to request memory region\n");
  280. return -EBUSY;
  281. }
  282. base = ioremap(mem->start, mem_size);
  283. if (!base) {
  284. printk(KERN_ERR "failed to map IO memory\n");
  285. release_mem_region(mem->start, mem_size);
  286. return -ENOMEM;
  287. }
  288. /* Configure the Palm Chip controller */
  289. palm_bk3710_chipinit(base);
  290. memset(&hw, 0, sizeof(hw));
  291. for (i = 0; i < IDE_NR_PORTS - 2; i++)
  292. hw.io_ports_array[i] = (unsigned long)
  293. (base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
  294. hw.io_ports.ctl_addr = (unsigned long)
  295. (base + IDE_PALM_ATA_PRI_CTL_OFFSET);
  296. hw.irq = irq->start;
  297. hw.dev = &pdev->dev;
  298. palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
  299. ATA_UDMA5;
  300. /* Register the IDE interface with Linux */
  301. rc = ide_host_add(&palm_bk3710_port_info, hws, 1, NULL);
  302. if (rc)
  303. goto out;
  304. return 0;
  305. out:
  306. printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
  307. return rc;
  308. }
  309. /* work with hotplug and coldplug */
  310. MODULE_ALIAS("platform:palm_bk3710");
  311. static struct platform_driver platform_bk_driver = {
  312. .driver = {
  313. .name = "palm_bk3710",
  314. },
  315. };
  316. static int __init palm_bk3710_init(void)
  317. {
  318. return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
  319. }
  320. module_init(palm_bk3710_init);
  321. MODULE_LICENSE("GPL");