it821x.c 20 KB

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  1. /*
  2. * Copyright (C) 2004 Red Hat
  3. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  4. *
  5. * May be copied or modified under the terms of the GNU General Public License
  6. * Based in part on the ITE vendor provided SCSI driver.
  7. *
  8. * Documentation:
  9. * Datasheet is freely available, some other documents under NDA.
  10. *
  11. * The ITE8212 isn't exactly a standard IDE controller. It has two
  12. * modes. In pass through mode then it is an IDE controller. In its smart
  13. * mode its actually quite a capable hardware raid controller disguised
  14. * as an IDE controller. Smart mode only understands DMA read/write and
  15. * identify, none of the fancier commands apply. The IT8211 is identical
  16. * in other respects but lacks the raid mode.
  17. *
  18. * Errata:
  19. * o Rev 0x10 also requires master/slave hold the same DMA timings and
  20. * cannot do ATAPI MWDMA.
  21. * o The identify data for raid volumes lacks CHS info (technically ok)
  22. * but also fails to set the LBA28 and other bits. We fix these in
  23. * the IDE probe quirk code.
  24. * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
  25. * raid then the controller firmware dies
  26. * o Smart mode without RAID doesn't clear all the necessary identify
  27. * bits to reduce the command set to the one used
  28. *
  29. * This has a few impacts on the driver
  30. * - In pass through mode we do all the work you would expect
  31. * - In smart mode the clocking set up is done by the controller generally
  32. * but we must watch the other limits and filter.
  33. * - There are a few extra vendor commands that actually talk to the
  34. * controller but only work PIO with no IRQ.
  35. *
  36. * Vendor areas of the identify block in smart mode are used for the
  37. * timing and policy set up. Each HDD in raid mode also has a serial
  38. * block on the disk. The hardware extra commands are get/set chip status,
  39. * rebuild, get rebuild status.
  40. *
  41. * In Linux the driver supports pass through mode as if the device was
  42. * just another IDE controller. If the smart mode is running then
  43. * volumes are managed by the controller firmware and each IDE "disk"
  44. * is a raid volume. Even more cute - the controller can do automated
  45. * hotplug and rebuild.
  46. *
  47. * The pass through controller itself is a little demented. It has a
  48. * flaw that it has a single set of PIO/MWDMA timings per channel so
  49. * non UDMA devices restrict each others performance. It also has a
  50. * single clock source per channel so mixed UDMA100/133 performance
  51. * isn't perfect and we have to pick a clock. Thankfully none of this
  52. * matters in smart mode. ATAPI DMA is not currently supported.
  53. *
  54. * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
  55. *
  56. * TODO
  57. * - ATAPI UDMA is ok but not MWDMA it seems
  58. * - RAID configuration ioctls
  59. * - Move to libata once it grows up
  60. */
  61. #include <linux/types.h>
  62. #include <linux/module.h>
  63. #include <linux/slab.h>
  64. #include <linux/pci.h>
  65. #include <linux/ide.h>
  66. #include <linux/init.h>
  67. #define DRV_NAME "it821x"
  68. #define QUIRK_VORTEX86 1
  69. struct it821x_dev
  70. {
  71. unsigned int smart:1, /* Are we in smart raid mode */
  72. timing10:1; /* Rev 0x10 */
  73. u8 clock_mode; /* 0, ATA_50 or ATA_66 */
  74. u8 want[2][2]; /* Mode/Pri log for master slave */
  75. /* We need these for switching the clock when DMA goes on/off
  76. The high byte is the 66Mhz timing */
  77. u16 pio[2]; /* Cached PIO values */
  78. u16 mwdma[2]; /* Cached MWDMA values */
  79. u16 udma[2]; /* Cached UDMA values (per drive) */
  80. u16 quirks;
  81. };
  82. #define ATA_66 0
  83. #define ATA_50 1
  84. #define ATA_ANY 2
  85. #define UDMA_OFF 0
  86. #define MWDMA_OFF 0
  87. /*
  88. * We allow users to force the card into non raid mode without
  89. * flashing the alternative BIOS. This is also necessary right now
  90. * for embedded platforms that cannot run a PC BIOS but are using this
  91. * device.
  92. */
  93. static int it8212_noraid;
  94. /**
  95. * it821x_program - program the PIO/MWDMA registers
  96. * @drive: drive to tune
  97. * @timing: timing info
  98. *
  99. * Program the PIO/MWDMA timing for this channel according to the
  100. * current clock.
  101. */
  102. static void it821x_program(ide_drive_t *drive, u16 timing)
  103. {
  104. ide_hwif_t *hwif = drive->hwif;
  105. struct pci_dev *dev = to_pci_dev(hwif->dev);
  106. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  107. int channel = hwif->channel;
  108. u8 conf;
  109. /* Program PIO/MWDMA timing bits */
  110. if(itdev->clock_mode == ATA_66)
  111. conf = timing >> 8;
  112. else
  113. conf = timing & 0xFF;
  114. pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
  115. }
  116. /**
  117. * it821x_program_udma - program the UDMA registers
  118. * @drive: drive to tune
  119. * @timing: timing info
  120. *
  121. * Program the UDMA timing for this drive according to the
  122. * current clock.
  123. */
  124. static void it821x_program_udma(ide_drive_t *drive, u16 timing)
  125. {
  126. ide_hwif_t *hwif = drive->hwif;
  127. struct pci_dev *dev = to_pci_dev(hwif->dev);
  128. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  129. int channel = hwif->channel;
  130. u8 unit = drive->dn & 1, conf;
  131. /* Program UDMA timing bits */
  132. if(itdev->clock_mode == ATA_66)
  133. conf = timing >> 8;
  134. else
  135. conf = timing & 0xFF;
  136. if (itdev->timing10 == 0)
  137. pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
  138. else {
  139. pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
  140. pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
  141. }
  142. }
  143. /**
  144. * it821x_clock_strategy
  145. * @drive: drive to set up
  146. *
  147. * Select between the 50 and 66Mhz base clocks to get the best
  148. * results for this interface.
  149. */
  150. static void it821x_clock_strategy(ide_drive_t *drive)
  151. {
  152. ide_hwif_t *hwif = drive->hwif;
  153. struct pci_dev *dev = to_pci_dev(hwif->dev);
  154. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  155. ide_drive_t *pair = ide_get_pair_dev(drive);
  156. int clock, altclock, sel = 0;
  157. u8 unit = drive->dn & 1, v;
  158. if(itdev->want[0][0] > itdev->want[1][0]) {
  159. clock = itdev->want[0][1];
  160. altclock = itdev->want[1][1];
  161. } else {
  162. clock = itdev->want[1][1];
  163. altclock = itdev->want[0][1];
  164. }
  165. /*
  166. * if both clocks can be used for the mode with the higher priority
  167. * use the clock needed by the mode with the lower priority
  168. */
  169. if (clock == ATA_ANY)
  170. clock = altclock;
  171. /* Nobody cares - keep the same clock */
  172. if(clock == ATA_ANY)
  173. return;
  174. /* No change */
  175. if(clock == itdev->clock_mode)
  176. return;
  177. /* Load this into the controller ? */
  178. if(clock == ATA_66)
  179. itdev->clock_mode = ATA_66;
  180. else {
  181. itdev->clock_mode = ATA_50;
  182. sel = 1;
  183. }
  184. pci_read_config_byte(dev, 0x50, &v);
  185. v &= ~(1 << (1 + hwif->channel));
  186. v |= sel << (1 + hwif->channel);
  187. pci_write_config_byte(dev, 0x50, v);
  188. /*
  189. * Reprogram the UDMA/PIO of the pair drive for the switch
  190. * MWDMA will be dealt with by the dma switcher
  191. */
  192. if(pair && itdev->udma[1-unit] != UDMA_OFF) {
  193. it821x_program_udma(pair, itdev->udma[1-unit]);
  194. it821x_program(pair, itdev->pio[1-unit]);
  195. }
  196. /*
  197. * Reprogram the UDMA/PIO of our drive for the switch.
  198. * MWDMA will be dealt with by the dma switcher
  199. */
  200. if(itdev->udma[unit] != UDMA_OFF) {
  201. it821x_program_udma(drive, itdev->udma[unit]);
  202. it821x_program(drive, itdev->pio[unit]);
  203. }
  204. }
  205. /**
  206. * it821x_set_pio_mode - set host controller for PIO mode
  207. * @hwif: port
  208. * @drive: drive
  209. *
  210. * Tune the host to the desired PIO mode taking into the consideration
  211. * the maximum PIO mode supported by the other device on the cable.
  212. */
  213. static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  214. {
  215. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  216. ide_drive_t *pair = ide_get_pair_dev(drive);
  217. const u8 pio = drive->pio_mode - XFER_PIO_0;
  218. u8 unit = drive->dn & 1, set_pio = pio;
  219. /* Spec says 89 ref driver uses 88 */
  220. static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
  221. static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
  222. /*
  223. * Compute the best PIO mode we can for a given device. We must
  224. * pick a speed that does not cause problems with the other device
  225. * on the cable.
  226. */
  227. if (pair) {
  228. u8 pair_pio = pair->pio_mode - XFER_PIO_0;
  229. /* trim PIO to the slowest of the master/slave */
  230. if (pair_pio < set_pio)
  231. set_pio = pair_pio;
  232. }
  233. /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
  234. itdev->want[unit][1] = pio_want[set_pio];
  235. itdev->want[unit][0] = 1; /* PIO is lowest priority */
  236. itdev->pio[unit] = pio_timings[set_pio];
  237. it821x_clock_strategy(drive);
  238. it821x_program(drive, itdev->pio[unit]);
  239. }
  240. /**
  241. * it821x_tune_mwdma - tune a channel for MWDMA
  242. * @drive: drive to set up
  243. * @mode_wanted: the target operating mode
  244. *
  245. * Load the timing settings for this device mode into the
  246. * controller when doing MWDMA in pass through mode. The caller
  247. * must manage the whole lack of per device MWDMA/PIO timings and
  248. * the shared MWDMA/PIO timing register.
  249. */
  250. static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted)
  251. {
  252. ide_hwif_t *hwif = drive->hwif;
  253. struct pci_dev *dev = to_pci_dev(hwif->dev);
  254. struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
  255. u8 unit = drive->dn & 1, channel = hwif->channel, conf;
  256. static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
  257. static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
  258. itdev->want[unit][1] = mwdma_want[mode_wanted];
  259. itdev->want[unit][0] = 2; /* MWDMA is low priority */
  260. itdev->mwdma[unit] = dma[mode_wanted];
  261. itdev->udma[unit] = UDMA_OFF;
  262. /* UDMA bits off - Revision 0x10 do them in pairs */
  263. pci_read_config_byte(dev, 0x50, &conf);
  264. if (itdev->timing10)
  265. conf |= channel ? 0x60: 0x18;
  266. else
  267. conf |= 1 << (3 + 2 * channel + unit);
  268. pci_write_config_byte(dev, 0x50, conf);
  269. it821x_clock_strategy(drive);
  270. /* FIXME: do we need to program this ? */
  271. /* it821x_program(drive, itdev->mwdma[unit]); */
  272. }
  273. /**
  274. * it821x_tune_udma - tune a channel for UDMA
  275. * @drive: drive to set up
  276. * @mode_wanted: the target operating mode
  277. *
  278. * Load the timing settings for this device mode into the
  279. * controller when doing UDMA modes in pass through.
  280. */
  281. static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted)
  282. {
  283. ide_hwif_t *hwif = drive->hwif;
  284. struct pci_dev *dev = to_pci_dev(hwif->dev);
  285. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  286. u8 unit = drive->dn & 1, channel = hwif->channel, conf;
  287. static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
  288. static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
  289. itdev->want[unit][1] = udma_want[mode_wanted];
  290. itdev->want[unit][0] = 3; /* UDMA is high priority */
  291. itdev->mwdma[unit] = MWDMA_OFF;
  292. itdev->udma[unit] = udma[mode_wanted];
  293. if(mode_wanted >= 5)
  294. itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
  295. /* UDMA on. Again revision 0x10 must do the pair */
  296. pci_read_config_byte(dev, 0x50, &conf);
  297. if (itdev->timing10)
  298. conf &= channel ? 0x9F: 0xE7;
  299. else
  300. conf &= ~ (1 << (3 + 2 * channel + unit));
  301. pci_write_config_byte(dev, 0x50, conf);
  302. it821x_clock_strategy(drive);
  303. it821x_program_udma(drive, itdev->udma[unit]);
  304. }
  305. /**
  306. * it821x_dma_read - DMA hook
  307. * @drive: drive for DMA
  308. *
  309. * The IT821x has a single timing register for MWDMA and for PIO
  310. * operations. As we flip back and forth we have to reload the
  311. * clock. In addition the rev 0x10 device only works if the same
  312. * timing value is loaded into the master and slave UDMA clock
  313. * so we must also reload that.
  314. *
  315. * FIXME: we could figure out in advance if we need to do reloads
  316. */
  317. static void it821x_dma_start(ide_drive_t *drive)
  318. {
  319. ide_hwif_t *hwif = drive->hwif;
  320. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  321. u8 unit = drive->dn & 1;
  322. if(itdev->mwdma[unit] != MWDMA_OFF)
  323. it821x_program(drive, itdev->mwdma[unit]);
  324. else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
  325. it821x_program_udma(drive, itdev->udma[unit]);
  326. ide_dma_start(drive);
  327. }
  328. /**
  329. * it821x_dma_write - DMA hook
  330. * @drive: drive for DMA stop
  331. *
  332. * The IT821x has a single timing register for MWDMA and for PIO
  333. * operations. As we flip back and forth we have to reload the
  334. * clock.
  335. */
  336. static int it821x_dma_end(ide_drive_t *drive)
  337. {
  338. ide_hwif_t *hwif = drive->hwif;
  339. struct it821x_dev *itdev = ide_get_hwifdata(hwif);
  340. int ret = ide_dma_end(drive);
  341. u8 unit = drive->dn & 1;
  342. if(itdev->mwdma[unit] != MWDMA_OFF)
  343. it821x_program(drive, itdev->pio[unit]);
  344. return ret;
  345. }
  346. /**
  347. * it821x_set_dma_mode - set host controller for DMA mode
  348. * @hwif: port
  349. * @drive: drive
  350. *
  351. * Tune the ITE chipset for the desired DMA mode.
  352. */
  353. static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  354. {
  355. const u8 speed = drive->dma_mode;
  356. /*
  357. * MWDMA tuning is really hard because our MWDMA and PIO
  358. * timings are kept in the same place. We can switch in the
  359. * host dma on/off callbacks.
  360. */
  361. if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
  362. it821x_tune_udma(drive, speed - XFER_UDMA_0);
  363. else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
  364. it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
  365. }
  366. /**
  367. * it821x_cable_detect - cable detection
  368. * @hwif: interface to check
  369. *
  370. * Check for the presence of an ATA66 capable cable on the
  371. * interface. Problematic as it seems some cards don't have
  372. * the needed logic onboard.
  373. */
  374. static u8 it821x_cable_detect(ide_hwif_t *hwif)
  375. {
  376. /* The reference driver also only does disk side */
  377. return ATA_CBL_PATA80;
  378. }
  379. /**
  380. * it821x_quirkproc - post init callback
  381. * @drive: drive
  382. *
  383. * This callback is run after the drive has been probed but
  384. * before anything gets attached. It allows drivers to do any
  385. * final tuning that is needed, or fixups to work around bugs.
  386. */
  387. static void it821x_quirkproc(ide_drive_t *drive)
  388. {
  389. struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
  390. u16 *id = drive->id;
  391. if (!itdev->smart) {
  392. /*
  393. * If we are in pass through mode then not much
  394. * needs to be done, but we do bother to clear the
  395. * IRQ mask as we may well be in PIO (eg rev 0x10)
  396. * for now and we know unmasking is safe on this chipset.
  397. */
  398. drive->dev_flags |= IDE_DFLAG_UNMASK;
  399. } else {
  400. /*
  401. * Perform fixups on smart mode. We need to "lose" some
  402. * capabilities the firmware lacks but does not filter, and
  403. * also patch up some capability bits that it forgets to set
  404. * in RAID mode.
  405. */
  406. /* Check for RAID v native */
  407. if (strstr((char *)&id[ATA_ID_PROD],
  408. "Integrated Technology Express")) {
  409. /* In raid mode the ident block is slightly buggy
  410. We need to set the bits so that the IDE layer knows
  411. LBA28. LBA48 and DMA ar valid */
  412. id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */
  413. id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */
  414. id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */
  415. /* Reporting logic */
  416. printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
  417. drive->name, id[147] ? "Bootable " : "",
  418. id[ATA_ID_CSFO]);
  419. if (id[ATA_ID_CSFO] != 1)
  420. printk(KERN_CONT "(%dK stripe)", id[146]);
  421. printk(KERN_CONT ".\n");
  422. } else {
  423. /* Non RAID volume. Fixups to stop the core code
  424. doing unsupported things */
  425. id[ATA_ID_FIELD_VALID] &= 3;
  426. id[ATA_ID_QUEUE_DEPTH] = 0;
  427. id[ATA_ID_COMMAND_SET_1] = 0;
  428. id[ATA_ID_COMMAND_SET_2] &= 0xC400;
  429. id[ATA_ID_CFSSE] &= 0xC000;
  430. id[ATA_ID_CFS_ENABLE_1] = 0;
  431. id[ATA_ID_CFS_ENABLE_2] &= 0xC400;
  432. id[ATA_ID_CSF_DEFAULT] &= 0xC000;
  433. id[127] = 0;
  434. id[ATA_ID_DLF] = 0;
  435. id[ATA_ID_CSFO] = 0;
  436. id[ATA_ID_CFA_POWER] = 0;
  437. printk(KERN_INFO "%s: Performing identify fixups.\n",
  438. drive->name);
  439. }
  440. /*
  441. * Set MWDMA0 mode as enabled/support - just to tell
  442. * IDE core that DMA is supported (it821x hardware
  443. * takes care of DMA mode programming).
  444. */
  445. if (ata_id_has_dma(id)) {
  446. id[ATA_ID_MWDMA_MODES] |= 0x0101;
  447. drive->current_speed = XFER_MW_DMA_0;
  448. }
  449. }
  450. }
  451. static const struct ide_dma_ops it821x_pass_through_dma_ops = {
  452. .dma_host_set = ide_dma_host_set,
  453. .dma_setup = ide_dma_setup,
  454. .dma_start = it821x_dma_start,
  455. .dma_end = it821x_dma_end,
  456. .dma_test_irq = ide_dma_test_irq,
  457. .dma_lost_irq = ide_dma_lost_irq,
  458. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  459. .dma_sff_read_status = ide_dma_sff_read_status,
  460. };
  461. /**
  462. * init_hwif_it821x - set up hwif structs
  463. * @hwif: interface to set up
  464. *
  465. * We do the basic set up of the interface structure. The IT8212
  466. * requires several custom handlers so we override the default
  467. * ide DMA handlers appropriately
  468. */
  469. static void init_hwif_it821x(ide_hwif_t *hwif)
  470. {
  471. struct pci_dev *dev = to_pci_dev(hwif->dev);
  472. struct ide_host *host = pci_get_drvdata(dev);
  473. struct it821x_dev *itdevs = host->host_priv;
  474. struct it821x_dev *idev = itdevs + hwif->channel;
  475. u8 conf;
  476. ide_set_hwifdata(hwif, idev);
  477. pci_read_config_byte(dev, 0x50, &conf);
  478. if (conf & 1) {
  479. idev->smart = 1;
  480. hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  481. /* Long I/O's although allowed in LBA48 space cause the
  482. onboard firmware to enter the twighlight zone */
  483. hwif->rqsize = 256;
  484. }
  485. /* Pull the current clocks from 0x50 also */
  486. if (conf & (1 << (1 + hwif->channel)))
  487. idev->clock_mode = ATA_50;
  488. else
  489. idev->clock_mode = ATA_66;
  490. idev->want[0][1] = ATA_ANY;
  491. idev->want[1][1] = ATA_ANY;
  492. /*
  493. * Not in the docs but according to the reference driver
  494. * this is necessary.
  495. */
  496. if (dev->revision == 0x10) {
  497. idev->timing10 = 1;
  498. hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  499. if (idev->smart == 0)
  500. printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
  501. "workarounds activated\n", pci_name(dev));
  502. }
  503. if (idev->smart == 0) {
  504. /* MWDMA/PIO clock switching for pass through mode */
  505. hwif->dma_ops = &it821x_pass_through_dma_ops;
  506. } else
  507. hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
  508. if (hwif->dma_base == 0)
  509. return;
  510. hwif->ultra_mask = ATA_UDMA6;
  511. hwif->mwdma_mask = ATA_MWDMA2;
  512. /* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */
  513. if (idev->quirks & QUIRK_VORTEX86) {
  514. if (dev->revision == 0x11)
  515. hwif->ultra_mask = 0;
  516. }
  517. }
  518. static void it8212_disable_raid(struct pci_dev *dev)
  519. {
  520. /* Reset local CPU, and set BIOS not ready */
  521. pci_write_config_byte(dev, 0x5E, 0x01);
  522. /* Set to bypass mode, and reset PCI bus */
  523. pci_write_config_byte(dev, 0x50, 0x00);
  524. pci_write_config_word(dev, PCI_COMMAND,
  525. PCI_COMMAND_PARITY | PCI_COMMAND_IO |
  526. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  527. pci_write_config_word(dev, 0x40, 0xA0F3);
  528. pci_write_config_dword(dev,0x4C, 0x02040204);
  529. pci_write_config_byte(dev, 0x42, 0x36);
  530. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
  531. }
  532. static int init_chipset_it821x(struct pci_dev *dev)
  533. {
  534. u8 conf;
  535. static char *mode[2] = { "pass through", "smart" };
  536. /* Force the card into bypass mode if so requested */
  537. if (it8212_noraid) {
  538. printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
  539. pci_name(dev));
  540. it8212_disable_raid(dev);
  541. }
  542. pci_read_config_byte(dev, 0x50, &conf);
  543. printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
  544. pci_name(dev), mode[conf & 1]);
  545. return 0;
  546. }
  547. static const struct ide_port_ops it821x_port_ops = {
  548. /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
  549. .set_pio_mode = it821x_set_pio_mode,
  550. .set_dma_mode = it821x_set_dma_mode,
  551. .quirkproc = it821x_quirkproc,
  552. .cable_detect = it821x_cable_detect,
  553. };
  554. static const struct ide_port_info it821x_chipset = {
  555. .name = DRV_NAME,
  556. .init_chipset = init_chipset_it821x,
  557. .init_hwif = init_hwif_it821x,
  558. .port_ops = &it821x_port_ops,
  559. .pio_mask = ATA_PIO4,
  560. };
  561. /**
  562. * it821x_init_one - pci layer discovery entry
  563. * @dev: PCI device
  564. * @id: ident table entry
  565. *
  566. * Called by the PCI code when it finds an ITE821x controller.
  567. * We then use the IDE PCI generic helper to do most of the work.
  568. */
  569. static int it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  570. {
  571. struct it821x_dev *itdevs;
  572. int rc;
  573. itdevs = kcalloc(2, sizeof(*itdevs), GFP_KERNEL);
  574. if (itdevs == NULL) {
  575. printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
  576. return -ENOMEM;
  577. }
  578. itdevs->quirks = id->driver_data;
  579. rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
  580. if (rc)
  581. kfree(itdevs);
  582. return rc;
  583. }
  584. static void it821x_remove(struct pci_dev *dev)
  585. {
  586. struct ide_host *host = pci_get_drvdata(dev);
  587. struct it821x_dev *itdevs = host->host_priv;
  588. ide_pci_remove(dev);
  589. kfree(itdevs);
  590. }
  591. static const struct pci_device_id it821x_pci_tbl[] = {
  592. { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
  593. { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
  594. { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 },
  595. { 0, },
  596. };
  597. MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
  598. static struct pci_driver it821x_pci_driver = {
  599. .name = "ITE821x IDE",
  600. .id_table = it821x_pci_tbl,
  601. .probe = it821x_init_one,
  602. .remove = it821x_remove,
  603. .suspend = ide_pci_suspend,
  604. .resume = ide_pci_resume,
  605. };
  606. static int __init it821x_ide_init(void)
  607. {
  608. return ide_pci_register_driver(&it821x_pci_driver);
  609. }
  610. static void __exit it821x_ide_exit(void)
  611. {
  612. pci_unregister_driver(&it821x_pci_driver);
  613. }
  614. module_init(it821x_ide_init);
  615. module_exit(it821x_ide_exit);
  616. module_param_named(noraid, it8212_noraid, int, S_IRUGO);
  617. MODULE_PARM_DESC(noraid, "Force card into bypass mode");
  618. MODULE_AUTHOR("Alan Cox");
  619. MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
  620. MODULE_LICENSE("GPL");