icside.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 1996-2004 Russell King.
  4. *
  5. * Please note that this platform does not support 32-bit IDE IO.
  6. */
  7. #include <linux/string.h>
  8. #include <linux/module.h>
  9. #include <linux/ioport.h>
  10. #include <linux/slab.h>
  11. #include <linux/blkdev.h>
  12. #include <linux/errno.h>
  13. #include <linux/ide.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/device.h>
  16. #include <linux/init.h>
  17. #include <linux/scatterlist.h>
  18. #include <linux/io.h>
  19. #include <asm/dma.h>
  20. #include <asm/ecard.h>
  21. #define DRV_NAME "icside"
  22. #define ICS_IDENT_OFFSET 0x2280
  23. #define ICS_ARCIN_V5_INTRSTAT 0x0000
  24. #define ICS_ARCIN_V5_INTROFFSET 0x0004
  25. #define ICS_ARCIN_V5_IDEOFFSET 0x2800
  26. #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
  27. #define ICS_ARCIN_V5_IDESTEPPING 6
  28. #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
  29. #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
  30. #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
  31. #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
  32. #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
  33. #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
  34. #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
  35. #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
  36. #define ICS_ARCIN_V6_IDESTEPPING 6
  37. struct cardinfo {
  38. unsigned int dataoffset;
  39. unsigned int ctrloffset;
  40. unsigned int stepping;
  41. };
  42. static struct cardinfo icside_cardinfo_v5 = {
  43. .dataoffset = ICS_ARCIN_V5_IDEOFFSET,
  44. .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
  45. .stepping = ICS_ARCIN_V5_IDESTEPPING,
  46. };
  47. static struct cardinfo icside_cardinfo_v6_1 = {
  48. .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
  49. .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
  50. .stepping = ICS_ARCIN_V6_IDESTEPPING,
  51. };
  52. static struct cardinfo icside_cardinfo_v6_2 = {
  53. .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
  54. .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
  55. .stepping = ICS_ARCIN_V6_IDESTEPPING,
  56. };
  57. struct icside_state {
  58. unsigned int channel;
  59. unsigned int enabled;
  60. void __iomem *irq_port;
  61. void __iomem *ioc_base;
  62. unsigned int sel;
  63. unsigned int type;
  64. struct ide_host *host;
  65. };
  66. #define ICS_TYPE_A3IN 0
  67. #define ICS_TYPE_A3USER 1
  68. #define ICS_TYPE_V6 3
  69. #define ICS_TYPE_V5 15
  70. #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  71. /* ---------------- Version 5 PCB Support Functions --------------------- */
  72. /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  73. * Purpose : enable interrupts from card
  74. */
  75. static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  76. {
  77. struct icside_state *state = ec->irq_data;
  78. writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  79. }
  80. /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  81. * Purpose : disable interrupts from card
  82. */
  83. static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  84. {
  85. struct icside_state *state = ec->irq_data;
  86. readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  87. }
  88. static const expansioncard_ops_t icside_ops_arcin_v5 = {
  89. .irqenable = icside_irqenable_arcin_v5,
  90. .irqdisable = icside_irqdisable_arcin_v5,
  91. };
  92. /* ---------------- Version 6 PCB Support Functions --------------------- */
  93. /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
  94. * Purpose : enable interrupts from card
  95. */
  96. static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
  97. {
  98. struct icside_state *state = ec->irq_data;
  99. void __iomem *base = state->irq_port;
  100. state->enabled = 1;
  101. switch (state->channel) {
  102. case 0:
  103. writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
  104. readb(base + ICS_ARCIN_V6_INTROFFSET_2);
  105. break;
  106. case 1:
  107. writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
  108. readb(base + ICS_ARCIN_V6_INTROFFSET_1);
  109. break;
  110. }
  111. }
  112. /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
  113. * Purpose : disable interrupts from card
  114. */
  115. static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
  116. {
  117. struct icside_state *state = ec->irq_data;
  118. state->enabled = 0;
  119. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  120. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  121. }
  122. /* Prototype: icside_irqprobe(struct expansion_card *ec)
  123. * Purpose : detect an active interrupt from card
  124. */
  125. static int icside_irqpending_arcin_v6(struct expansion_card *ec)
  126. {
  127. struct icside_state *state = ec->irq_data;
  128. return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
  129. readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
  130. }
  131. static const expansioncard_ops_t icside_ops_arcin_v6 = {
  132. .irqenable = icside_irqenable_arcin_v6,
  133. .irqdisable = icside_irqdisable_arcin_v6,
  134. .irqpending = icside_irqpending_arcin_v6,
  135. };
  136. /*
  137. * Handle routing of interrupts. This is called before
  138. * we write the command to the drive.
  139. */
  140. static void icside_maskproc(ide_drive_t *drive, int mask)
  141. {
  142. ide_hwif_t *hwif = drive->hwif;
  143. struct expansion_card *ec = ECARD_DEV(hwif->dev);
  144. struct icside_state *state = ecard_get_drvdata(ec);
  145. unsigned long flags;
  146. local_irq_save(flags);
  147. state->channel = hwif->channel;
  148. if (state->enabled && !mask) {
  149. switch (hwif->channel) {
  150. case 0:
  151. writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  152. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  153. break;
  154. case 1:
  155. writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  156. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  157. break;
  158. }
  159. } else {
  160. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  161. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  162. }
  163. local_irq_restore(flags);
  164. }
  165. static const struct ide_port_ops icside_v6_no_dma_port_ops = {
  166. .maskproc = icside_maskproc,
  167. };
  168. #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
  169. /*
  170. * SG-DMA support.
  171. *
  172. * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
  173. * There is only one DMA controller per card, which means that only
  174. * one drive can be accessed at one time. NOTE! We do not enforce that
  175. * here, but we rely on the main IDE driver spotting that both
  176. * interfaces use the same IRQ, which should guarantee this.
  177. */
  178. /*
  179. * Configure the IOMD to give the appropriate timings for the transfer
  180. * mode being requested. We take the advice of the ATA standards, and
  181. * calculate the cycle time based on the transfer mode, and the EIDE
  182. * MW DMA specs that the drive provides in the IDENTIFY command.
  183. *
  184. * We have the following IOMD DMA modes to choose from:
  185. *
  186. * Type Active Recovery Cycle
  187. * A 250 (250) 312 (550) 562 (800)
  188. * B 187 250 437
  189. * C 125 (125) 125 (375) 250 (500)
  190. * D 62 125 187
  191. *
  192. * (figures in brackets are actual measured timings)
  193. *
  194. * However, we also need to take care of the read/write active and
  195. * recovery timings:
  196. *
  197. * Read Write
  198. * Mode Active -- Recovery -- Cycle IOMD type
  199. * MW0 215 50 215 480 A
  200. * MW1 80 50 50 150 C
  201. * MW2 70 25 25 120 C
  202. */
  203. static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  204. {
  205. unsigned long cycle_time = 0;
  206. int use_dma_info = 0;
  207. const u8 xfer_mode = drive->dma_mode;
  208. switch (xfer_mode) {
  209. case XFER_MW_DMA_2:
  210. cycle_time = 250;
  211. use_dma_info = 1;
  212. break;
  213. case XFER_MW_DMA_1:
  214. cycle_time = 250;
  215. use_dma_info = 1;
  216. break;
  217. case XFER_MW_DMA_0:
  218. cycle_time = 480;
  219. break;
  220. case XFER_SW_DMA_2:
  221. case XFER_SW_DMA_1:
  222. case XFER_SW_DMA_0:
  223. cycle_time = 480;
  224. break;
  225. }
  226. /*
  227. * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
  228. * take care to note the values in the ID...
  229. */
  230. if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
  231. cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
  232. ide_set_drivedata(drive, (void *)cycle_time);
  233. printk(KERN_INFO "%s: %s selected (peak %luMB/s)\n",
  234. drive->name, ide_xfer_verbose(xfer_mode),
  235. 2000 / (cycle_time ? cycle_time : (unsigned long) -1));
  236. }
  237. static const struct ide_port_ops icside_v6_port_ops = {
  238. .set_dma_mode = icside_set_dma_mode,
  239. .maskproc = icside_maskproc,
  240. };
  241. static void icside_dma_host_set(ide_drive_t *drive, int on)
  242. {
  243. }
  244. static int icside_dma_end(ide_drive_t *drive)
  245. {
  246. ide_hwif_t *hwif = drive->hwif;
  247. struct expansion_card *ec = ECARD_DEV(hwif->dev);
  248. disable_dma(ec->dma);
  249. return get_dma_residue(ec->dma) != 0;
  250. }
  251. static void icside_dma_start(ide_drive_t *drive)
  252. {
  253. ide_hwif_t *hwif = drive->hwif;
  254. struct expansion_card *ec = ECARD_DEV(hwif->dev);
  255. /* We can not enable DMA on both channels simultaneously. */
  256. BUG_ON(dma_channel_active(ec->dma));
  257. enable_dma(ec->dma);
  258. }
  259. static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
  260. {
  261. ide_hwif_t *hwif = drive->hwif;
  262. struct expansion_card *ec = ECARD_DEV(hwif->dev);
  263. struct icside_state *state = ecard_get_drvdata(ec);
  264. unsigned int dma_mode;
  265. if (cmd->tf_flags & IDE_TFLAG_WRITE)
  266. dma_mode = DMA_MODE_WRITE;
  267. else
  268. dma_mode = DMA_MODE_READ;
  269. /*
  270. * We can not enable DMA on both channels.
  271. */
  272. BUG_ON(dma_channel_active(ec->dma));
  273. /*
  274. * Ensure that we have the right interrupt routed.
  275. */
  276. icside_maskproc(drive, 0);
  277. /*
  278. * Route the DMA signals to the correct interface.
  279. */
  280. writeb(state->sel | hwif->channel, state->ioc_base);
  281. /*
  282. * Select the correct timing for this drive.
  283. */
  284. set_dma_speed(ec->dma, (unsigned long)ide_get_drivedata(drive));
  285. /*
  286. * Tell the DMA engine about the SG table and
  287. * data direction.
  288. */
  289. set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
  290. set_dma_mode(ec->dma, dma_mode);
  291. return 0;
  292. }
  293. static int icside_dma_test_irq(ide_drive_t *drive)
  294. {
  295. ide_hwif_t *hwif = drive->hwif;
  296. struct expansion_card *ec = ECARD_DEV(hwif->dev);
  297. struct icside_state *state = ecard_get_drvdata(ec);
  298. return readb(state->irq_port +
  299. (hwif->channel ?
  300. ICS_ARCIN_V6_INTRSTAT_2 :
  301. ICS_ARCIN_V6_INTRSTAT_1)) & 1;
  302. }
  303. static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
  304. {
  305. hwif->dmatable_cpu = NULL;
  306. hwif->dmatable_dma = 0;
  307. return 0;
  308. }
  309. static const struct ide_dma_ops icside_v6_dma_ops = {
  310. .dma_host_set = icside_dma_host_set,
  311. .dma_setup = icside_dma_setup,
  312. .dma_start = icside_dma_start,
  313. .dma_end = icside_dma_end,
  314. .dma_test_irq = icside_dma_test_irq,
  315. .dma_lost_irq = ide_dma_lost_irq,
  316. };
  317. #endif
  318. static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
  319. {
  320. return -EOPNOTSUPP;
  321. }
  322. static void icside_setup_ports(struct ide_hw *hw, void __iomem *base,
  323. struct cardinfo *info, struct expansion_card *ec)
  324. {
  325. unsigned long port = (unsigned long)base + info->dataoffset;
  326. hw->io_ports.data_addr = port;
  327. hw->io_ports.error_addr = port + (1 << info->stepping);
  328. hw->io_ports.nsect_addr = port + (2 << info->stepping);
  329. hw->io_ports.lbal_addr = port + (3 << info->stepping);
  330. hw->io_ports.lbam_addr = port + (4 << info->stepping);
  331. hw->io_ports.lbah_addr = port + (5 << info->stepping);
  332. hw->io_ports.device_addr = port + (6 << info->stepping);
  333. hw->io_ports.status_addr = port + (7 << info->stepping);
  334. hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
  335. hw->irq = ec->irq;
  336. hw->dev = &ec->dev;
  337. }
  338. static const struct ide_port_info icside_v5_port_info = {
  339. .host_flags = IDE_HFLAG_NO_DMA,
  340. .chipset = ide_acorn,
  341. };
  342. static int icside_register_v5(struct icside_state *state,
  343. struct expansion_card *ec)
  344. {
  345. void __iomem *base;
  346. struct ide_host *host;
  347. struct ide_hw hw, *hws[] = { &hw };
  348. int ret;
  349. base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
  350. if (!base)
  351. return -ENOMEM;
  352. state->irq_port = base;
  353. ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
  354. ec->irqmask = 1;
  355. ecard_setirq(ec, &icside_ops_arcin_v5, state);
  356. /*
  357. * Be on the safe side - disable interrupts
  358. */
  359. icside_irqdisable_arcin_v5(ec, 0);
  360. icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
  361. host = ide_host_alloc(&icside_v5_port_info, hws, 1);
  362. if (host == NULL)
  363. return -ENODEV;
  364. state->host = host;
  365. ecard_set_drvdata(ec, state);
  366. ret = ide_host_register(host, &icside_v5_port_info, hws);
  367. if (ret)
  368. goto err_free;
  369. return 0;
  370. err_free:
  371. ide_host_free(host);
  372. ecard_set_drvdata(ec, NULL);
  373. return ret;
  374. }
  375. static const struct ide_port_info icside_v6_port_info = {
  376. .init_dma = icside_dma_off_init,
  377. .port_ops = &icside_v6_no_dma_port_ops,
  378. .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
  379. .mwdma_mask = ATA_MWDMA2,
  380. .swdma_mask = ATA_SWDMA2,
  381. .chipset = ide_acorn,
  382. };
  383. static int icside_register_v6(struct icside_state *state,
  384. struct expansion_card *ec)
  385. {
  386. void __iomem *ioc_base, *easi_base;
  387. struct ide_host *host;
  388. unsigned int sel = 0;
  389. int ret;
  390. struct ide_hw hw[2], *hws[] = { &hw[0], &hw[1] };
  391. struct ide_port_info d = icside_v6_port_info;
  392. ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
  393. if (!ioc_base) {
  394. ret = -ENOMEM;
  395. goto out;
  396. }
  397. easi_base = ioc_base;
  398. if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
  399. easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
  400. if (!easi_base) {
  401. ret = -ENOMEM;
  402. goto out;
  403. }
  404. /*
  405. * Enable access to the EASI region.
  406. */
  407. sel = 1 << 5;
  408. }
  409. writeb(sel, ioc_base);
  410. ecard_setirq(ec, &icside_ops_arcin_v6, state);
  411. state->irq_port = easi_base;
  412. state->ioc_base = ioc_base;
  413. state->sel = sel;
  414. /*
  415. * Be on the safe side - disable interrupts
  416. */
  417. icside_irqdisable_arcin_v6(ec, 0);
  418. icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
  419. icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
  420. host = ide_host_alloc(&d, hws, 2);
  421. if (host == NULL)
  422. return -ENODEV;
  423. state->host = host;
  424. ecard_set_drvdata(ec, state);
  425. #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
  426. if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
  427. d.init_dma = icside_dma_init;
  428. d.port_ops = &icside_v6_port_ops;
  429. d.dma_ops = &icside_v6_dma_ops;
  430. }
  431. #endif
  432. ret = ide_host_register(host, &d, hws);
  433. if (ret)
  434. goto err_free;
  435. return 0;
  436. err_free:
  437. ide_host_free(host);
  438. if (d.dma_ops)
  439. free_dma(ec->dma);
  440. ecard_set_drvdata(ec, NULL);
  441. out:
  442. return ret;
  443. }
  444. static int icside_probe(struct expansion_card *ec, const struct ecard_id *id)
  445. {
  446. struct icside_state *state;
  447. void __iomem *idmem;
  448. int ret;
  449. ret = ecard_request_resources(ec);
  450. if (ret)
  451. goto out;
  452. state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
  453. if (!state) {
  454. ret = -ENOMEM;
  455. goto release;
  456. }
  457. state->type = ICS_TYPE_NOTYPE;
  458. idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
  459. if (idmem) {
  460. unsigned int type;
  461. type = readb(idmem + ICS_IDENT_OFFSET) & 1;
  462. type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
  463. type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
  464. type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
  465. ecardm_iounmap(ec, idmem);
  466. state->type = type;
  467. }
  468. switch (state->type) {
  469. case ICS_TYPE_A3IN:
  470. dev_warn(&ec->dev, "A3IN unsupported\n");
  471. ret = -ENODEV;
  472. break;
  473. case ICS_TYPE_A3USER:
  474. dev_warn(&ec->dev, "A3USER unsupported\n");
  475. ret = -ENODEV;
  476. break;
  477. case ICS_TYPE_V5:
  478. ret = icside_register_v5(state, ec);
  479. break;
  480. case ICS_TYPE_V6:
  481. ret = icside_register_v6(state, ec);
  482. break;
  483. default:
  484. dev_warn(&ec->dev, "unknown interface type\n");
  485. ret = -ENODEV;
  486. break;
  487. }
  488. if (ret == 0)
  489. goto out;
  490. kfree(state);
  491. release:
  492. ecard_release_resources(ec);
  493. out:
  494. return ret;
  495. }
  496. static void icside_remove(struct expansion_card *ec)
  497. {
  498. struct icside_state *state = ecard_get_drvdata(ec);
  499. switch (state->type) {
  500. case ICS_TYPE_V5:
  501. /* FIXME: tell IDE to stop using the interface */
  502. /* Disable interrupts */
  503. icside_irqdisable_arcin_v5(ec, 0);
  504. break;
  505. case ICS_TYPE_V6:
  506. /* FIXME: tell IDE to stop using the interface */
  507. if (ec->dma != NO_DMA)
  508. free_dma(ec->dma);
  509. /* Disable interrupts */
  510. icside_irqdisable_arcin_v6(ec, 0);
  511. /* Reset the ROM pointer/EASI selection */
  512. writeb(0, state->ioc_base);
  513. break;
  514. }
  515. ecard_set_drvdata(ec, NULL);
  516. kfree(state);
  517. ecard_release_resources(ec);
  518. }
  519. static void icside_shutdown(struct expansion_card *ec)
  520. {
  521. struct icside_state *state = ecard_get_drvdata(ec);
  522. unsigned long flags;
  523. /*
  524. * Disable interrupts from this card. We need to do
  525. * this before disabling EASI since we may be accessing
  526. * this register via that region.
  527. */
  528. local_irq_save(flags);
  529. ec->ops->irqdisable(ec, 0);
  530. local_irq_restore(flags);
  531. /*
  532. * Reset the ROM pointer so that we can read the ROM
  533. * after a soft reboot. This also disables access to
  534. * the IDE taskfile via the EASI region.
  535. */
  536. if (state->ioc_base)
  537. writeb(0, state->ioc_base);
  538. }
  539. static const struct ecard_id icside_ids[] = {
  540. { MANU_ICS, PROD_ICS_IDE },
  541. { MANU_ICS2, PROD_ICS2_IDE },
  542. { 0xffff, 0xffff }
  543. };
  544. static struct ecard_driver icside_driver = {
  545. .probe = icside_probe,
  546. .remove = icside_remove,
  547. .shutdown = icside_shutdown,
  548. .id_table = icside_ids,
  549. .drv = {
  550. .name = "icside",
  551. },
  552. };
  553. static int __init icside_init(void)
  554. {
  555. return ecard_register_driver(&icside_driver);
  556. }
  557. static void __exit icside_exit(void)
  558. {
  559. ecard_remove_driver(&icside_driver);
  560. }
  561. MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
  562. MODULE_LICENSE("GPL");
  563. MODULE_DESCRIPTION("ICS IDE driver");
  564. module_init(icside_init);
  565. module_exit(icside_exit);