hpt366.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
  4. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
  5. * Portions Copyright (C) 2003 Red Hat Inc
  6. * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  7. * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
  8. *
  9. * Thanks to HighPoint Technologies for their assistance, and hardware.
  10. * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11. * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12. * development and support.
  13. *
  14. *
  15. * HighPoint has its own drivers (open source except for the RAID part)
  16. * available from http://www.highpoint-tech.com/USA_new/service_support.htm
  17. * This may be useful to anyone wanting to work on this driver, however do not
  18. * trust them too much since the code tends to become less and less meaningful
  19. * as the time passes... :-/
  20. *
  21. * Note that final HPT370 support was done by force extraction of GPL.
  22. *
  23. * - add function for getting/setting power status of drive
  24. * - the HPT370's state machine can get confused. reset it before each dma
  25. * xfer to prevent that from happening.
  26. * - reset state engine whenever we get an error.
  27. * - check for busmaster state at end of dma.
  28. * - use new highpoint timings.
  29. * - detect bus speed using highpoint register.
  30. * - use pll if we don't have a clock table. added a 66MHz table that's
  31. * just 2x the 33MHz table.
  32. * - removed turnaround. NOTE: we never want to switch between pll and
  33. * pci clocks as the chip can glitch in those cases. the highpoint
  34. * approved workaround slows everything down too much to be useful. in
  35. * addition, we would have to serialize access to each chip.
  36. * Adrian Sun <a.sun@sun.com>
  37. *
  38. * add drive timings for 66MHz PCI bus,
  39. * fix ATA Cable signal detection, fix incorrect /proc info
  40. * add /proc display for per-drive PIO/DMA/UDMA mode and
  41. * per-channel ATA-33/66 Cable detect.
  42. * Duncan Laurie <void@sun.com>
  43. *
  44. * fixup /proc output for multiple controllers
  45. * Tim Hockin <thockin@sun.com>
  46. *
  47. * On hpt366:
  48. * Reset the hpt366 on error, reset on dma
  49. * Fix disabling Fast Interrupt hpt366.
  50. * Mike Waychison <crlf@sun.com>
  51. *
  52. * Added support for 372N clocking and clock switching. The 372N needs
  53. * different clocks on read/write. This requires overloading rw_disk and
  54. * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55. * keeping me sane.
  56. * Alan Cox <alan@lxorguk.ukuu.org.uk>
  57. *
  58. * - fix the clock turnaround code: it was writing to the wrong ports when
  59. * called for the secondary channel, caching the current clock mode per-
  60. * channel caused the cached register value to get out of sync with the
  61. * actual one, the channels weren't serialized, the turnaround shouldn't
  62. * be done on 66 MHz PCI bus
  63. * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
  64. * does not allow for this speed anyway
  65. * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
  66. * their primary channel is kind of virtual, it isn't tied to any pins)
  67. * - fix/remove bad/unused timing tables and use one set of tables for the whole
  68. * HPT37x chip family; save space by introducing the separate transfer mode
  69. * table in which the mode lookup is done
  70. * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
  71. * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
  72. * read it only from the function 0 of HPT374 chips
  73. * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
  74. * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  75. * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  76. * they tamper with its fields
  77. * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
  78. * since they may tamper with its fields
  79. * - prefix the driver startup messages with the real chip name
  80. * - claim the extra 240 bytes of I/O space for all chips
  81. * - optimize the UltraDMA filtering and the drive list lookup code
  82. * - use pci_get_slot() to get to the function 1 of HPT36x/374
  83. * - cache offset of the channel's misc. control registers (MCRs) being used
  84. * throughout the driver
  85. * - only touch the relevant MCR when detecting the cable type on HPT374's
  86. * function 1
  87. * - rename all the register related variables consistently
  88. * - move all the interrupt twiddling code from the speedproc handlers into
  89. * init_hwif_hpt366(), also grouping all the DMA related code together there
  90. * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
  91. * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
  92. * when setting an UltraDMA mode
  93. * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
  94. * the best possible one
  95. * - clean up DMA timeout handling for HPT370
  96. * - switch to using the enumeration type to differ between the numerous chip
  97. * variants, matching PCI device/revision ID with the chip type early, at the
  98. * init_setup stage
  99. * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
  100. * stop duplicating it for each channel by storing the pointer in the pci_dev
  101. * structure: first, at the init_setup stage, point it to a static "template"
  102. * with only the chip type and its specific base DPLL frequency, the highest
  103. * UltraDMA mode, and the chip settings table pointer filled, then, at the
  104. * init_chipset stage, allocate per-chip instance and fill it with the rest
  105. * of the necessary information
  106. * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
  107. * switch to calculating PCI clock frequency based on the chip's base DPLL
  108. * frequency
  109. * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
  110. * anything newer than HPT370/A (except HPT374 that is not capable of this
  111. * mode according to the manual)
  112. * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
  113. * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
  114. * unify HPT36x/37x timing setup code and the speedproc handlers by joining
  115. * the register setting lists into the table indexed by the clock selected
  116. * - set the correct hwif->ultra_mask for each individual chip
  117. * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
  118. * - stop resetting HPT370's state machine before each DMA transfer as that has
  119. * caused more harm than good
  120. * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
  121. */
  122. #include <linux/types.h>
  123. #include <linux/module.h>
  124. #include <linux/kernel.h>
  125. #include <linux/delay.h>
  126. #include <linux/blkdev.h>
  127. #include <linux/interrupt.h>
  128. #include <linux/pci.h>
  129. #include <linux/init.h>
  130. #include <linux/ide.h>
  131. #include <linux/slab.h>
  132. #include <linux/uaccess.h>
  133. #include <asm/io.h>
  134. #define DRV_NAME "hpt366"
  135. /* various tuning parameters */
  136. #undef HPT_RESET_STATE_ENGINE
  137. #undef HPT_DELAY_INTERRUPT
  138. static const char *bad_ata100_5[] = {
  139. "IBM-DTLA-307075",
  140. "IBM-DTLA-307060",
  141. "IBM-DTLA-307045",
  142. "IBM-DTLA-307030",
  143. "IBM-DTLA-307020",
  144. "IBM-DTLA-307015",
  145. "IBM-DTLA-305040",
  146. "IBM-DTLA-305030",
  147. "IBM-DTLA-305020",
  148. "IC35L010AVER07-0",
  149. "IC35L020AVER07-0",
  150. "IC35L030AVER07-0",
  151. "IC35L040AVER07-0",
  152. "IC35L060AVER07-0",
  153. "WDC AC310200R",
  154. NULL
  155. };
  156. static const char *bad_ata66_4[] = {
  157. "IBM-DTLA-307075",
  158. "IBM-DTLA-307060",
  159. "IBM-DTLA-307045",
  160. "IBM-DTLA-307030",
  161. "IBM-DTLA-307020",
  162. "IBM-DTLA-307015",
  163. "IBM-DTLA-305040",
  164. "IBM-DTLA-305030",
  165. "IBM-DTLA-305020",
  166. "IC35L010AVER07-0",
  167. "IC35L020AVER07-0",
  168. "IC35L030AVER07-0",
  169. "IC35L040AVER07-0",
  170. "IC35L060AVER07-0",
  171. "WDC AC310200R",
  172. "MAXTOR STM3320620A",
  173. NULL
  174. };
  175. static const char *bad_ata66_3[] = {
  176. "WDC AC310200R",
  177. NULL
  178. };
  179. static const char *bad_ata33[] = {
  180. "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
  181. "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
  182. "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
  183. "Maxtor 90510D4",
  184. "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
  185. "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
  186. "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
  187. NULL
  188. };
  189. static u8 xfer_speeds[] = {
  190. XFER_UDMA_6,
  191. XFER_UDMA_5,
  192. XFER_UDMA_4,
  193. XFER_UDMA_3,
  194. XFER_UDMA_2,
  195. XFER_UDMA_1,
  196. XFER_UDMA_0,
  197. XFER_MW_DMA_2,
  198. XFER_MW_DMA_1,
  199. XFER_MW_DMA_0,
  200. XFER_PIO_4,
  201. XFER_PIO_3,
  202. XFER_PIO_2,
  203. XFER_PIO_1,
  204. XFER_PIO_0
  205. };
  206. /* Key for bus clock timings
  207. * 36x 37x
  208. * bits bits
  209. * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  210. * cycles = value + 1
  211. * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  212. * cycles = value + 1
  213. * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  214. * register access.
  215. * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
  216. * register access.
  217. * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
  218. * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
  219. * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
  220. * MW DMA xfer.
  221. * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
  222. * task file register access.
  223. * 28 28 UDMA enable.
  224. * 29 29 DMA enable.
  225. * 30 30 PIO MST enable. If set, the chip is in bus master mode during
  226. * PIO xfer.
  227. * 31 31 FIFO enable.
  228. */
  229. static u32 forty_base_hpt36x[] = {
  230. /* XFER_UDMA_6 */ 0x900fd943,
  231. /* XFER_UDMA_5 */ 0x900fd943,
  232. /* XFER_UDMA_4 */ 0x900fd943,
  233. /* XFER_UDMA_3 */ 0x900ad943,
  234. /* XFER_UDMA_2 */ 0x900bd943,
  235. /* XFER_UDMA_1 */ 0x9008d943,
  236. /* XFER_UDMA_0 */ 0x9008d943,
  237. /* XFER_MW_DMA_2 */ 0xa008d943,
  238. /* XFER_MW_DMA_1 */ 0xa010d955,
  239. /* XFER_MW_DMA_0 */ 0xa010d9fc,
  240. /* XFER_PIO_4 */ 0xc008d963,
  241. /* XFER_PIO_3 */ 0xc010d974,
  242. /* XFER_PIO_2 */ 0xc010d997,
  243. /* XFER_PIO_1 */ 0xc010d9c7,
  244. /* XFER_PIO_0 */ 0xc018d9d9
  245. };
  246. static u32 thirty_three_base_hpt36x[] = {
  247. /* XFER_UDMA_6 */ 0x90c9a731,
  248. /* XFER_UDMA_5 */ 0x90c9a731,
  249. /* XFER_UDMA_4 */ 0x90c9a731,
  250. /* XFER_UDMA_3 */ 0x90cfa731,
  251. /* XFER_UDMA_2 */ 0x90caa731,
  252. /* XFER_UDMA_1 */ 0x90cba731,
  253. /* XFER_UDMA_0 */ 0x90c8a731,
  254. /* XFER_MW_DMA_2 */ 0xa0c8a731,
  255. /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
  256. /* XFER_MW_DMA_0 */ 0xa0c8a797,
  257. /* XFER_PIO_4 */ 0xc0c8a731,
  258. /* XFER_PIO_3 */ 0xc0c8a742,
  259. /* XFER_PIO_2 */ 0xc0d0a753,
  260. /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
  261. /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
  262. };
  263. static u32 twenty_five_base_hpt36x[] = {
  264. /* XFER_UDMA_6 */ 0x90c98521,
  265. /* XFER_UDMA_5 */ 0x90c98521,
  266. /* XFER_UDMA_4 */ 0x90c98521,
  267. /* XFER_UDMA_3 */ 0x90cf8521,
  268. /* XFER_UDMA_2 */ 0x90cf8521,
  269. /* XFER_UDMA_1 */ 0x90cb8521,
  270. /* XFER_UDMA_0 */ 0x90cb8521,
  271. /* XFER_MW_DMA_2 */ 0xa0ca8521,
  272. /* XFER_MW_DMA_1 */ 0xa0ca8532,
  273. /* XFER_MW_DMA_0 */ 0xa0ca8575,
  274. /* XFER_PIO_4 */ 0xc0ca8521,
  275. /* XFER_PIO_3 */ 0xc0ca8532,
  276. /* XFER_PIO_2 */ 0xc0ca8542,
  277. /* XFER_PIO_1 */ 0xc0d08572,
  278. /* XFER_PIO_0 */ 0xc0d08585
  279. };
  280. /*
  281. * The following are the new timing tables with PIO mode data/taskfile transfer
  282. * overclocking fixed...
  283. */
  284. /* This table is taken from the HPT370 data manual rev. 1.02 */
  285. static u32 thirty_three_base_hpt37x[] = {
  286. /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
  287. /* XFER_UDMA_5 */ 0x16455031,
  288. /* XFER_UDMA_4 */ 0x16455031,
  289. /* XFER_UDMA_3 */ 0x166d5031,
  290. /* XFER_UDMA_2 */ 0x16495031,
  291. /* XFER_UDMA_1 */ 0x164d5033,
  292. /* XFER_UDMA_0 */ 0x16515097,
  293. /* XFER_MW_DMA_2 */ 0x26515031,
  294. /* XFER_MW_DMA_1 */ 0x26515033,
  295. /* XFER_MW_DMA_0 */ 0x26515097,
  296. /* XFER_PIO_4 */ 0x06515021,
  297. /* XFER_PIO_3 */ 0x06515022,
  298. /* XFER_PIO_2 */ 0x06515033,
  299. /* XFER_PIO_1 */ 0x06915065,
  300. /* XFER_PIO_0 */ 0x06d1508a
  301. };
  302. static u32 fifty_base_hpt37x[] = {
  303. /* XFER_UDMA_6 */ 0x1a861842,
  304. /* XFER_UDMA_5 */ 0x1a861842,
  305. /* XFER_UDMA_4 */ 0x1aae1842,
  306. /* XFER_UDMA_3 */ 0x1a8e1842,
  307. /* XFER_UDMA_2 */ 0x1a0e1842,
  308. /* XFER_UDMA_1 */ 0x1a161854,
  309. /* XFER_UDMA_0 */ 0x1a1a18ea,
  310. /* XFER_MW_DMA_2 */ 0x2a821842,
  311. /* XFER_MW_DMA_1 */ 0x2a821854,
  312. /* XFER_MW_DMA_0 */ 0x2a8218ea,
  313. /* XFER_PIO_4 */ 0x0a821842,
  314. /* XFER_PIO_3 */ 0x0a821843,
  315. /* XFER_PIO_2 */ 0x0a821855,
  316. /* XFER_PIO_1 */ 0x0ac218a8,
  317. /* XFER_PIO_0 */ 0x0b02190c
  318. };
  319. static u32 sixty_six_base_hpt37x[] = {
  320. /* XFER_UDMA_6 */ 0x1c86fe62,
  321. /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
  322. /* XFER_UDMA_4 */ 0x1c8afe62,
  323. /* XFER_UDMA_3 */ 0x1c8efe62,
  324. /* XFER_UDMA_2 */ 0x1c92fe62,
  325. /* XFER_UDMA_1 */ 0x1c9afe62,
  326. /* XFER_UDMA_0 */ 0x1c82fe62,
  327. /* XFER_MW_DMA_2 */ 0x2c82fe62,
  328. /* XFER_MW_DMA_1 */ 0x2c82fe66,
  329. /* XFER_MW_DMA_0 */ 0x2c82ff2e,
  330. /* XFER_PIO_4 */ 0x0c82fe62,
  331. /* XFER_PIO_3 */ 0x0c82fe84,
  332. /* XFER_PIO_2 */ 0x0c82fea6,
  333. /* XFER_PIO_1 */ 0x0d02ff26,
  334. /* XFER_PIO_0 */ 0x0d42ff7f
  335. };
  336. #define HPT371_ALLOW_ATA133_6 1
  337. #define HPT302_ALLOW_ATA133_6 1
  338. #define HPT372_ALLOW_ATA133_6 1
  339. #define HPT370_ALLOW_ATA100_5 0
  340. #define HPT366_ALLOW_ATA66_4 1
  341. #define HPT366_ALLOW_ATA66_3 1
  342. /* Supported ATA clock frequencies */
  343. enum ata_clock {
  344. ATA_CLOCK_25MHZ,
  345. ATA_CLOCK_33MHZ,
  346. ATA_CLOCK_40MHZ,
  347. ATA_CLOCK_50MHZ,
  348. ATA_CLOCK_66MHZ,
  349. NUM_ATA_CLOCKS
  350. };
  351. struct hpt_timings {
  352. u32 pio_mask;
  353. u32 dma_mask;
  354. u32 ultra_mask;
  355. u32 *clock_table[NUM_ATA_CLOCKS];
  356. };
  357. /*
  358. * Hold all the HighPoint chip information in one place.
  359. */
  360. struct hpt_info {
  361. char *chip_name; /* Chip name */
  362. u8 chip_type; /* Chip type */
  363. u8 udma_mask; /* Allowed UltraDMA modes mask. */
  364. u8 dpll_clk; /* DPLL clock in MHz */
  365. u8 pci_clk; /* PCI clock in MHz */
  366. struct hpt_timings *timings; /* Chipset timing data */
  367. u8 clock; /* ATA clock selected */
  368. };
  369. /* Supported HighPoint chips */
  370. enum {
  371. HPT36x,
  372. HPT370,
  373. HPT370A,
  374. HPT374,
  375. HPT372,
  376. HPT372A,
  377. HPT302,
  378. HPT371,
  379. HPT372N,
  380. HPT302N,
  381. HPT371N
  382. };
  383. static struct hpt_timings hpt36x_timings = {
  384. .pio_mask = 0xc1f8ffff,
  385. .dma_mask = 0x303800ff,
  386. .ultra_mask = 0x30070000,
  387. .clock_table = {
  388. [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
  389. [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
  390. [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
  391. [ATA_CLOCK_50MHZ] = NULL,
  392. [ATA_CLOCK_66MHZ] = NULL
  393. }
  394. };
  395. static struct hpt_timings hpt37x_timings = {
  396. .pio_mask = 0xcfc3ffff,
  397. .dma_mask = 0x31c001ff,
  398. .ultra_mask = 0x303c0000,
  399. .clock_table = {
  400. [ATA_CLOCK_25MHZ] = NULL,
  401. [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
  402. [ATA_CLOCK_40MHZ] = NULL,
  403. [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
  404. [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
  405. }
  406. };
  407. static const struct hpt_info hpt36x = {
  408. .chip_name = "HPT36x",
  409. .chip_type = HPT36x,
  410. .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
  411. .dpll_clk = 0, /* no DPLL */
  412. .timings = &hpt36x_timings
  413. };
  414. static const struct hpt_info hpt370 = {
  415. .chip_name = "HPT370",
  416. .chip_type = HPT370,
  417. .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
  418. .dpll_clk = 48,
  419. .timings = &hpt37x_timings
  420. };
  421. static const struct hpt_info hpt370a = {
  422. .chip_name = "HPT370A",
  423. .chip_type = HPT370A,
  424. .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
  425. .dpll_clk = 48,
  426. .timings = &hpt37x_timings
  427. };
  428. static const struct hpt_info hpt374 = {
  429. .chip_name = "HPT374",
  430. .chip_type = HPT374,
  431. .udma_mask = ATA_UDMA5,
  432. .dpll_clk = 48,
  433. .timings = &hpt37x_timings
  434. };
  435. static const struct hpt_info hpt372 = {
  436. .chip_name = "HPT372",
  437. .chip_type = HPT372,
  438. .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  439. .dpll_clk = 55,
  440. .timings = &hpt37x_timings
  441. };
  442. static const struct hpt_info hpt372a = {
  443. .chip_name = "HPT372A",
  444. .chip_type = HPT372A,
  445. .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  446. .dpll_clk = 66,
  447. .timings = &hpt37x_timings
  448. };
  449. static const struct hpt_info hpt302 = {
  450. .chip_name = "HPT302",
  451. .chip_type = HPT302,
  452. .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  453. .dpll_clk = 66,
  454. .timings = &hpt37x_timings
  455. };
  456. static const struct hpt_info hpt371 = {
  457. .chip_name = "HPT371",
  458. .chip_type = HPT371,
  459. .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  460. .dpll_clk = 66,
  461. .timings = &hpt37x_timings
  462. };
  463. static const struct hpt_info hpt372n = {
  464. .chip_name = "HPT372N",
  465. .chip_type = HPT372N,
  466. .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  467. .dpll_clk = 77,
  468. .timings = &hpt37x_timings
  469. };
  470. static const struct hpt_info hpt302n = {
  471. .chip_name = "HPT302N",
  472. .chip_type = HPT302N,
  473. .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  474. .dpll_clk = 77,
  475. .timings = &hpt37x_timings
  476. };
  477. static const struct hpt_info hpt371n = {
  478. .chip_name = "HPT371N",
  479. .chip_type = HPT371N,
  480. .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
  481. .dpll_clk = 77,
  482. .timings = &hpt37x_timings
  483. };
  484. static bool check_in_drive_list(ide_drive_t *drive, const char **list)
  485. {
  486. return match_string(list, -1, (char *)&drive->id[ATA_ID_PROD]) >= 0;
  487. }
  488. static struct hpt_info *hpt3xx_get_info(struct device *dev)
  489. {
  490. struct ide_host *host = dev_get_drvdata(dev);
  491. struct hpt_info *info = (struct hpt_info *)host->host_priv;
  492. return dev == host->dev[1] ? info + 1 : info;
  493. }
  494. /*
  495. * The Marvell bridge chips used on the HighPoint SATA cards do not seem
  496. * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  497. */
  498. static u8 hpt3xx_udma_filter(ide_drive_t *drive)
  499. {
  500. ide_hwif_t *hwif = drive->hwif;
  501. struct hpt_info *info = hpt3xx_get_info(hwif->dev);
  502. u8 mask = hwif->ultra_mask;
  503. switch (info->chip_type) {
  504. case HPT36x:
  505. if (!HPT366_ALLOW_ATA66_4 ||
  506. check_in_drive_list(drive, bad_ata66_4))
  507. mask = ATA_UDMA3;
  508. if (!HPT366_ALLOW_ATA66_3 ||
  509. check_in_drive_list(drive, bad_ata66_3))
  510. mask = ATA_UDMA2;
  511. break;
  512. case HPT370:
  513. if (!HPT370_ALLOW_ATA100_5 ||
  514. check_in_drive_list(drive, bad_ata100_5))
  515. mask = ATA_UDMA4;
  516. break;
  517. case HPT370A:
  518. if (!HPT370_ALLOW_ATA100_5 ||
  519. check_in_drive_list(drive, bad_ata100_5))
  520. return ATA_UDMA4;
  521. fallthrough;
  522. case HPT372 :
  523. case HPT372A:
  524. case HPT372N:
  525. case HPT374 :
  526. if (ata_id_is_sata(drive->id))
  527. mask &= ~0x0e;
  528. fallthrough;
  529. default:
  530. return mask;
  531. }
  532. return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
  533. }
  534. static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
  535. {
  536. ide_hwif_t *hwif = drive->hwif;
  537. struct hpt_info *info = hpt3xx_get_info(hwif->dev);
  538. switch (info->chip_type) {
  539. case HPT372 :
  540. case HPT372A:
  541. case HPT372N:
  542. case HPT374 :
  543. if (ata_id_is_sata(drive->id))
  544. return 0x00;
  545. fallthrough;
  546. default:
  547. return 0x07;
  548. }
  549. }
  550. static u32 get_speed_setting(u8 speed, struct hpt_info *info)
  551. {
  552. int i;
  553. /*
  554. * Lookup the transfer mode table to get the index into
  555. * the timing table.
  556. *
  557. * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
  558. */
  559. for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
  560. if (xfer_speeds[i] == speed)
  561. break;
  562. return info->timings->clock_table[info->clock][i];
  563. }
  564. static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  565. {
  566. struct pci_dev *dev = to_pci_dev(hwif->dev);
  567. struct hpt_info *info = hpt3xx_get_info(hwif->dev);
  568. struct hpt_timings *t = info->timings;
  569. u8 itr_addr = 0x40 + (drive->dn * 4);
  570. u32 old_itr = 0;
  571. const u8 speed = drive->dma_mode;
  572. u32 new_itr = get_speed_setting(speed, info);
  573. u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
  574. (speed < XFER_UDMA_0 ? t->dma_mask :
  575. t->ultra_mask);
  576. pci_read_config_dword(dev, itr_addr, &old_itr);
  577. new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
  578. /*
  579. * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
  580. * to avoid problems handling I/O errors later
  581. */
  582. new_itr &= ~0xc0000000;
  583. pci_write_config_dword(dev, itr_addr, new_itr);
  584. }
  585. static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  586. {
  587. drive->dma_mode = drive->pio_mode;
  588. hpt3xx_set_mode(hwif, drive);
  589. }
  590. static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
  591. {
  592. ide_hwif_t *hwif = drive->hwif;
  593. struct pci_dev *dev = to_pci_dev(hwif->dev);
  594. struct hpt_info *info = hpt3xx_get_info(hwif->dev);
  595. if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
  596. return;
  597. if (info->chip_type >= HPT370) {
  598. u8 scr1 = 0;
  599. pci_read_config_byte(dev, 0x5a, &scr1);
  600. if (((scr1 & 0x10) >> 4) != mask) {
  601. if (mask)
  602. scr1 |= 0x10;
  603. else
  604. scr1 &= ~0x10;
  605. pci_write_config_byte(dev, 0x5a, scr1);
  606. }
  607. } else if (mask)
  608. disable_irq(hwif->irq);
  609. else
  610. enable_irq(hwif->irq);
  611. }
  612. /*
  613. * This is specific to the HPT366 UDMA chipset
  614. * by HighPoint|Triones Technologies, Inc.
  615. */
  616. static void hpt366_dma_lost_irq(ide_drive_t *drive)
  617. {
  618. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  619. u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
  620. pci_read_config_byte(dev, 0x50, &mcr1);
  621. pci_read_config_byte(dev, 0x52, &mcr3);
  622. pci_read_config_byte(dev, 0x5a, &scr1);
  623. printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
  624. drive->name, __func__, mcr1, mcr3, scr1);
  625. if (scr1 & 0x10)
  626. pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
  627. ide_dma_lost_irq(drive);
  628. }
  629. static void hpt370_clear_engine(ide_drive_t *drive)
  630. {
  631. ide_hwif_t *hwif = drive->hwif;
  632. struct pci_dev *dev = to_pci_dev(hwif->dev);
  633. pci_write_config_byte(dev, hwif->select_data, 0x37);
  634. udelay(10);
  635. }
  636. static void hpt370_irq_timeout(ide_drive_t *drive)
  637. {
  638. ide_hwif_t *hwif = drive->hwif;
  639. struct pci_dev *dev = to_pci_dev(hwif->dev);
  640. u16 bfifo = 0;
  641. u8 dma_cmd;
  642. pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
  643. printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
  644. /* get DMA command mode */
  645. dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
  646. /* stop DMA */
  647. outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
  648. hpt370_clear_engine(drive);
  649. }
  650. static void hpt370_dma_start(ide_drive_t *drive)
  651. {
  652. #ifdef HPT_RESET_STATE_ENGINE
  653. hpt370_clear_engine(drive);
  654. #endif
  655. ide_dma_start(drive);
  656. }
  657. static int hpt370_dma_end(ide_drive_t *drive)
  658. {
  659. ide_hwif_t *hwif = drive->hwif;
  660. u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
  661. if (dma_stat & ATA_DMA_ACTIVE) {
  662. /* wait a little */
  663. udelay(20);
  664. dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
  665. if (dma_stat & ATA_DMA_ACTIVE)
  666. hpt370_irq_timeout(drive);
  667. }
  668. return ide_dma_end(drive);
  669. }
  670. /* returns 1 if DMA IRQ issued, 0 otherwise */
  671. static int hpt374_dma_test_irq(ide_drive_t *drive)
  672. {
  673. ide_hwif_t *hwif = drive->hwif;
  674. struct pci_dev *dev = to_pci_dev(hwif->dev);
  675. u16 bfifo = 0;
  676. u8 dma_stat;
  677. pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
  678. if (bfifo & 0x1FF) {
  679. // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
  680. return 0;
  681. }
  682. dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
  683. /* return 1 if INTR asserted */
  684. if (dma_stat & ATA_DMA_INTR)
  685. return 1;
  686. return 0;
  687. }
  688. static int hpt374_dma_end(ide_drive_t *drive)
  689. {
  690. ide_hwif_t *hwif = drive->hwif;
  691. struct pci_dev *dev = to_pci_dev(hwif->dev);
  692. u8 mcr = 0, mcr_addr = hwif->select_data;
  693. u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
  694. pci_read_config_byte(dev, 0x6a, &bwsr);
  695. pci_read_config_byte(dev, mcr_addr, &mcr);
  696. if (bwsr & mask)
  697. pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
  698. return ide_dma_end(drive);
  699. }
  700. /**
  701. * hpt3xxn_set_clock - perform clock switching dance
  702. * @hwif: hwif to switch
  703. * @mode: clocking mode (0x21 for write, 0x23 otherwise)
  704. *
  705. * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
  706. */
  707. static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
  708. {
  709. unsigned long base = hwif->extra_base;
  710. u8 scr2 = inb(base + 0x6b);
  711. if ((scr2 & 0x7f) == mode)
  712. return;
  713. /* Tristate the bus */
  714. outb(0x80, base + 0x63);
  715. outb(0x80, base + 0x67);
  716. /* Switch clock and reset channels */
  717. outb(mode, base + 0x6b);
  718. outb(0xc0, base + 0x69);
  719. /*
  720. * Reset the state machines.
  721. * NOTE: avoid accidentally enabling the disabled channels.
  722. */
  723. outb(inb(base + 0x60) | 0x32, base + 0x60);
  724. outb(inb(base + 0x64) | 0x32, base + 0x64);
  725. /* Complete reset */
  726. outb(0x00, base + 0x69);
  727. /* Reconnect channels to bus */
  728. outb(0x00, base + 0x63);
  729. outb(0x00, base + 0x67);
  730. }
  731. /**
  732. * hpt3xxn_rw_disk - prepare for I/O
  733. * @drive: drive for command
  734. * @rq: block request structure
  735. *
  736. * This is called when a disk I/O is issued to HPT3xxN.
  737. * We need it because of the clock switching.
  738. */
  739. static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
  740. {
  741. hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
  742. }
  743. /**
  744. * hpt37x_calibrate_dpll - calibrate the DPLL
  745. * @dev: PCI device
  746. *
  747. * Perform a calibration cycle on the DPLL.
  748. * Returns 1 if this succeeds
  749. */
  750. static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
  751. {
  752. u32 dpll = (f_high << 16) | f_low | 0x100;
  753. u8 scr2;
  754. int i;
  755. pci_write_config_dword(dev, 0x5c, dpll);
  756. /* Wait for oscillator ready */
  757. for(i = 0; i < 0x5000; ++i) {
  758. udelay(50);
  759. pci_read_config_byte(dev, 0x5b, &scr2);
  760. if (scr2 & 0x80)
  761. break;
  762. }
  763. /* See if it stays ready (we'll just bail out if it's not yet) */
  764. for(i = 0; i < 0x1000; ++i) {
  765. pci_read_config_byte(dev, 0x5b, &scr2);
  766. /* DPLL destabilized? */
  767. if(!(scr2 & 0x80))
  768. return 0;
  769. }
  770. /* Turn off tuning, we have the DPLL set */
  771. pci_read_config_dword (dev, 0x5c, &dpll);
  772. pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
  773. return 1;
  774. }
  775. static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
  776. {
  777. struct ide_host *host = pci_get_drvdata(dev);
  778. struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
  779. u8 chip_type = info->chip_type;
  780. u8 new_mcr, old_mcr = 0;
  781. /*
  782. * Disable the "fast interrupt" prediction. Don't hold off
  783. * on interrupts. (== 0x01 despite what the docs say)
  784. */
  785. pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
  786. if (chip_type >= HPT374)
  787. new_mcr = old_mcr & ~0x07;
  788. else if (chip_type >= HPT370) {
  789. new_mcr = old_mcr;
  790. new_mcr &= ~0x02;
  791. #ifdef HPT_DELAY_INTERRUPT
  792. new_mcr &= ~0x01;
  793. #else
  794. new_mcr |= 0x01;
  795. #endif
  796. } else /* HPT366 and HPT368 */
  797. new_mcr = old_mcr & ~0x80;
  798. if (new_mcr != old_mcr)
  799. pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
  800. }
  801. static int init_chipset_hpt366(struct pci_dev *dev)
  802. {
  803. unsigned long io_base = pci_resource_start(dev, 4);
  804. struct hpt_info *info = hpt3xx_get_info(&dev->dev);
  805. const char *name = DRV_NAME;
  806. u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
  807. u8 chip_type;
  808. enum ata_clock clock;
  809. chip_type = info->chip_type;
  810. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
  811. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
  812. pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
  813. pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
  814. /*
  815. * First, try to estimate the PCI clock frequency...
  816. */
  817. if (chip_type >= HPT370) {
  818. u8 scr1 = 0;
  819. u16 f_cnt = 0;
  820. u32 temp = 0;
  821. /* Interrupt force enable. */
  822. pci_read_config_byte(dev, 0x5a, &scr1);
  823. if (scr1 & 0x10)
  824. pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
  825. /*
  826. * HighPoint does this for HPT372A.
  827. * NOTE: This register is only writeable via I/O space.
  828. */
  829. if (chip_type == HPT372A)
  830. outb(0x0e, io_base + 0x9c);
  831. /*
  832. * Default to PCI clock. Make sure MA15/16 are set to output
  833. * to prevent drives having problems with 40-pin cables.
  834. */
  835. pci_write_config_byte(dev, 0x5b, 0x23);
  836. /*
  837. * We'll have to read f_CNT value in order to determine
  838. * the PCI clock frequency according to the following ratio:
  839. *
  840. * f_CNT = Fpci * 192 / Fdpll
  841. *
  842. * First try reading the register in which the HighPoint BIOS
  843. * saves f_CNT value before reprogramming the DPLL from its
  844. * default setting (which differs for the various chips).
  845. *
  846. * NOTE: This register is only accessible via I/O space;
  847. * HPT374 BIOS only saves it for the function 0, so we have to
  848. * always read it from there -- no need to check the result of
  849. * pci_get_slot() for the function 0 as the whole device has
  850. * been already "pinned" (via function 1) in init_setup_hpt374()
  851. */
  852. if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
  853. struct pci_dev *dev1 = pci_get_slot(dev->bus,
  854. dev->devfn - 1);
  855. unsigned long io_base = pci_resource_start(dev1, 4);
  856. temp = inl(io_base + 0x90);
  857. pci_dev_put(dev1);
  858. } else
  859. temp = inl(io_base + 0x90);
  860. /*
  861. * In case the signature check fails, we'll have to
  862. * resort to reading the f_CNT register itself in hopes
  863. * that nobody has touched the DPLL yet...
  864. */
  865. if ((temp & 0xFFFFF000) != 0xABCDE000) {
  866. int i;
  867. printk(KERN_WARNING "%s %s: no clock data saved by "
  868. "BIOS\n", name, pci_name(dev));
  869. /* Calculate the average value of f_CNT. */
  870. for (temp = i = 0; i < 128; i++) {
  871. pci_read_config_word(dev, 0x78, &f_cnt);
  872. temp += f_cnt & 0x1ff;
  873. mdelay(1);
  874. }
  875. f_cnt = temp / 128;
  876. } else
  877. f_cnt = temp & 0x1ff;
  878. dpll_clk = info->dpll_clk;
  879. pci_clk = (f_cnt * dpll_clk) / 192;
  880. /* Clamp PCI clock to bands. */
  881. if (pci_clk < 40)
  882. pci_clk = 33;
  883. else if(pci_clk < 45)
  884. pci_clk = 40;
  885. else if(pci_clk < 55)
  886. pci_clk = 50;
  887. else
  888. pci_clk = 66;
  889. printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
  890. "assuming %d MHz PCI\n", name, pci_name(dev),
  891. dpll_clk, f_cnt, pci_clk);
  892. } else {
  893. u32 itr1 = 0;
  894. pci_read_config_dword(dev, 0x40, &itr1);
  895. /* Detect PCI clock by looking at cmd_high_time. */
  896. switch ((itr1 >> 8) & 0x0f) {
  897. case 0x09:
  898. pci_clk = 40;
  899. break;
  900. case 0x05:
  901. pci_clk = 25;
  902. break;
  903. case 0x07:
  904. default:
  905. pci_clk = 33;
  906. break;
  907. }
  908. }
  909. /* Let's assume we'll use PCI clock for the ATA clock... */
  910. switch (pci_clk) {
  911. case 25:
  912. clock = ATA_CLOCK_25MHZ;
  913. break;
  914. case 33:
  915. default:
  916. clock = ATA_CLOCK_33MHZ;
  917. break;
  918. case 40:
  919. clock = ATA_CLOCK_40MHZ;
  920. break;
  921. case 50:
  922. clock = ATA_CLOCK_50MHZ;
  923. break;
  924. case 66:
  925. clock = ATA_CLOCK_66MHZ;
  926. break;
  927. }
  928. /*
  929. * Only try the DPLL if we don't have a table for the PCI clock that
  930. * we are running at for HPT370/A, always use it for anything newer...
  931. *
  932. * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
  933. * We also don't like using the DPLL because this causes glitches
  934. * on PRST-/SRST- when the state engine gets reset...
  935. */
  936. if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
  937. u16 f_low, delta = pci_clk < 50 ? 2 : 4;
  938. int adjust;
  939. /*
  940. * Select 66 MHz DPLL clock only if UltraATA/133 mode is
  941. * supported/enabled, use 50 MHz DPLL clock otherwise...
  942. */
  943. if (info->udma_mask == ATA_UDMA6) {
  944. dpll_clk = 66;
  945. clock = ATA_CLOCK_66MHZ;
  946. } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
  947. dpll_clk = 50;
  948. clock = ATA_CLOCK_50MHZ;
  949. }
  950. if (info->timings->clock_table[clock] == NULL) {
  951. printk(KERN_ERR "%s %s: unknown bus timing!\n",
  952. name, pci_name(dev));
  953. return -EIO;
  954. }
  955. /* Select the DPLL clock. */
  956. pci_write_config_byte(dev, 0x5b, 0x21);
  957. /*
  958. * Adjust the DPLL based upon PCI clock, enable it,
  959. * and wait for stabilization...
  960. */
  961. f_low = (pci_clk * 48) / dpll_clk;
  962. for (adjust = 0; adjust < 8; adjust++) {
  963. if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
  964. break;
  965. /*
  966. * See if it'll settle at a fractionally different clock
  967. */
  968. if (adjust & 1)
  969. f_low -= adjust >> 1;
  970. else
  971. f_low += adjust >> 1;
  972. }
  973. if (adjust == 8) {
  974. printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
  975. name, pci_name(dev));
  976. return -EIO;
  977. }
  978. printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
  979. name, pci_name(dev), dpll_clk);
  980. } else {
  981. /* Mark the fact that we're not using the DPLL. */
  982. dpll_clk = 0;
  983. printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
  984. name, pci_name(dev), pci_clk);
  985. }
  986. /* Store the clock frequencies. */
  987. info->dpll_clk = dpll_clk;
  988. info->pci_clk = pci_clk;
  989. info->clock = clock;
  990. if (chip_type >= HPT370) {
  991. u8 mcr1, mcr4;
  992. /*
  993. * Reset the state engines.
  994. * NOTE: Avoid accidentally enabling the disabled channels.
  995. */
  996. pci_read_config_byte (dev, 0x50, &mcr1);
  997. pci_read_config_byte (dev, 0x54, &mcr4);
  998. pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
  999. pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
  1000. udelay(100);
  1001. }
  1002. /*
  1003. * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
  1004. * the MISC. register to stretch the UltraDMA Tss timing.
  1005. * NOTE: This register is only writeable via I/O space.
  1006. */
  1007. if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
  1008. outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
  1009. hpt3xx_disable_fast_irq(dev, 0x50);
  1010. hpt3xx_disable_fast_irq(dev, 0x54);
  1011. return 0;
  1012. }
  1013. static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
  1014. {
  1015. struct pci_dev *dev = to_pci_dev(hwif->dev);
  1016. struct hpt_info *info = hpt3xx_get_info(hwif->dev);
  1017. u8 chip_type = info->chip_type;
  1018. u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
  1019. /*
  1020. * The HPT37x uses the CBLID pins as outputs for MA15/MA16
  1021. * address lines to access an external EEPROM. To read valid
  1022. * cable detect state the pins must be enabled as inputs.
  1023. */
  1024. if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
  1025. /*
  1026. * HPT374 PCI function 1
  1027. * - set bit 15 of reg 0x52 to enable TCBLID as input
  1028. * - set bit 15 of reg 0x56 to enable FCBLID as input
  1029. */
  1030. u8 mcr_addr = hwif->select_data + 2;
  1031. u16 mcr;
  1032. pci_read_config_word(dev, mcr_addr, &mcr);
  1033. pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
  1034. /* Debounce, then read cable ID register */
  1035. udelay(10);
  1036. pci_read_config_byte(dev, 0x5a, &scr1);
  1037. pci_write_config_word(dev, mcr_addr, mcr);
  1038. } else if (chip_type >= HPT370) {
  1039. /*
  1040. * HPT370/372 and 374 pcifn 0
  1041. * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
  1042. */
  1043. u8 scr2 = 0;
  1044. pci_read_config_byte(dev, 0x5b, &scr2);
  1045. pci_write_config_byte(dev, 0x5b, scr2 & ~1);
  1046. /* Debounce, then read cable ID register */
  1047. udelay(10);
  1048. pci_read_config_byte(dev, 0x5a, &scr1);
  1049. pci_write_config_byte(dev, 0x5b, scr2);
  1050. } else
  1051. pci_read_config_byte(dev, 0x5a, &scr1);
  1052. return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
  1053. }
  1054. static void init_hwif_hpt366(ide_hwif_t *hwif)
  1055. {
  1056. struct hpt_info *info = hpt3xx_get_info(hwif->dev);
  1057. u8 chip_type = info->chip_type;
  1058. /* Cache the channel's MISC. control registers' offset */
  1059. hwif->select_data = hwif->channel ? 0x54 : 0x50;
  1060. /*
  1061. * HPT3xxN chips have some complications:
  1062. *
  1063. * - on 33 MHz PCI we must clock switch
  1064. * - on 66 MHz PCI we must NOT use the PCI clock
  1065. */
  1066. if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
  1067. /*
  1068. * Clock is shared between the channels,
  1069. * so we'll have to serialize them... :-(
  1070. */
  1071. hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
  1072. hwif->rw_disk = &hpt3xxn_rw_disk;
  1073. }
  1074. }
  1075. static int init_dma_hpt366(ide_hwif_t *hwif,
  1076. const struct ide_port_info *d)
  1077. {
  1078. struct pci_dev *dev = to_pci_dev(hwif->dev);
  1079. unsigned long flags, base = ide_pci_dma_base(hwif, d);
  1080. u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
  1081. if (base == 0)
  1082. return -1;
  1083. hwif->dma_base = base;
  1084. if (ide_pci_check_simplex(hwif, d) < 0)
  1085. return -1;
  1086. if (ide_pci_set_master(dev, d->name) < 0)
  1087. return -1;
  1088. dma_old = inb(base + 2);
  1089. local_irq_save(flags);
  1090. dma_new = dma_old;
  1091. pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
  1092. pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
  1093. if (masterdma & 0x30) dma_new |= 0x20;
  1094. if ( slavedma & 0x30) dma_new |= 0x40;
  1095. if (dma_new != dma_old)
  1096. outb(dma_new, base + 2);
  1097. local_irq_restore(flags);
  1098. printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
  1099. hwif->name, base, base + 7);
  1100. hwif->extra_base = base + (hwif->channel ? 8 : 16);
  1101. if (ide_allocate_dma_engine(hwif))
  1102. return -1;
  1103. return 0;
  1104. }
  1105. static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
  1106. {
  1107. if (dev2->irq != dev->irq) {
  1108. /* FIXME: we need a core pci_set_interrupt() */
  1109. dev2->irq = dev->irq;
  1110. printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
  1111. "fixed\n", pci_name(dev2));
  1112. }
  1113. }
  1114. static void hpt371_init(struct pci_dev *dev)
  1115. {
  1116. u8 mcr1 = 0;
  1117. /*
  1118. * HPT371 chips physically have only one channel, the secondary one,
  1119. * but the primary channel registers do exist! Go figure...
  1120. * So, we manually disable the non-existing channel here
  1121. * (if the BIOS hasn't done this already).
  1122. */
  1123. pci_read_config_byte(dev, 0x50, &mcr1);
  1124. if (mcr1 & 0x04)
  1125. pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
  1126. }
  1127. static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
  1128. {
  1129. u8 mcr1 = 0, pin1 = 0, pin2 = 0;
  1130. /*
  1131. * Now we'll have to force both channels enabled if
  1132. * at least one of them has been enabled by BIOS...
  1133. */
  1134. pci_read_config_byte(dev, 0x50, &mcr1);
  1135. if (mcr1 & 0x30)
  1136. pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
  1137. pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
  1138. pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
  1139. if (pin1 != pin2 && dev->irq == dev2->irq) {
  1140. printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
  1141. "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
  1142. return 1;
  1143. }
  1144. return 0;
  1145. }
  1146. #define IDE_HFLAGS_HPT3XX \
  1147. (IDE_HFLAG_NO_ATAPI_DMA | \
  1148. IDE_HFLAG_OFF_BOARD)
  1149. static const struct ide_port_ops hpt3xx_port_ops = {
  1150. .set_pio_mode = hpt3xx_set_pio_mode,
  1151. .set_dma_mode = hpt3xx_set_mode,
  1152. .maskproc = hpt3xx_maskproc,
  1153. .mdma_filter = hpt3xx_mdma_filter,
  1154. .udma_filter = hpt3xx_udma_filter,
  1155. .cable_detect = hpt3xx_cable_detect,
  1156. };
  1157. static const struct ide_dma_ops hpt37x_dma_ops = {
  1158. .dma_host_set = ide_dma_host_set,
  1159. .dma_setup = ide_dma_setup,
  1160. .dma_start = ide_dma_start,
  1161. .dma_end = hpt374_dma_end,
  1162. .dma_test_irq = hpt374_dma_test_irq,
  1163. .dma_lost_irq = ide_dma_lost_irq,
  1164. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  1165. .dma_sff_read_status = ide_dma_sff_read_status,
  1166. };
  1167. static const struct ide_dma_ops hpt370_dma_ops = {
  1168. .dma_host_set = ide_dma_host_set,
  1169. .dma_setup = ide_dma_setup,
  1170. .dma_start = hpt370_dma_start,
  1171. .dma_end = hpt370_dma_end,
  1172. .dma_test_irq = ide_dma_test_irq,
  1173. .dma_lost_irq = ide_dma_lost_irq,
  1174. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  1175. .dma_clear = hpt370_irq_timeout,
  1176. .dma_sff_read_status = ide_dma_sff_read_status,
  1177. };
  1178. static const struct ide_dma_ops hpt36x_dma_ops = {
  1179. .dma_host_set = ide_dma_host_set,
  1180. .dma_setup = ide_dma_setup,
  1181. .dma_start = ide_dma_start,
  1182. .dma_end = ide_dma_end,
  1183. .dma_test_irq = ide_dma_test_irq,
  1184. .dma_lost_irq = hpt366_dma_lost_irq,
  1185. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  1186. .dma_sff_read_status = ide_dma_sff_read_status,
  1187. };
  1188. static const struct ide_port_info hpt366_chipsets[] = {
  1189. { /* 0: HPT36x */
  1190. .name = DRV_NAME,
  1191. .init_chipset = init_chipset_hpt366,
  1192. .init_hwif = init_hwif_hpt366,
  1193. .init_dma = init_dma_hpt366,
  1194. /*
  1195. * HPT36x chips have one channel per function and have
  1196. * both channel enable bits located differently and visible
  1197. * to both functions -- really stupid design decision... :-(
  1198. * Bit 4 is for the primary channel, bit 5 for the secondary.
  1199. */
  1200. .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
  1201. .port_ops = &hpt3xx_port_ops,
  1202. .dma_ops = &hpt36x_dma_ops,
  1203. .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
  1204. .pio_mask = ATA_PIO4,
  1205. .mwdma_mask = ATA_MWDMA2,
  1206. },
  1207. { /* 1: HPT3xx */
  1208. .name = DRV_NAME,
  1209. .init_chipset = init_chipset_hpt366,
  1210. .init_hwif = init_hwif_hpt366,
  1211. .init_dma = init_dma_hpt366,
  1212. .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
  1213. .port_ops = &hpt3xx_port_ops,
  1214. .dma_ops = &hpt37x_dma_ops,
  1215. .host_flags = IDE_HFLAGS_HPT3XX,
  1216. .pio_mask = ATA_PIO4,
  1217. .mwdma_mask = ATA_MWDMA2,
  1218. }
  1219. };
  1220. /**
  1221. * hpt366_init_one - called when an HPT366 is found
  1222. * @dev: the hpt366 device
  1223. * @id: the matching pci id
  1224. *
  1225. * Called when the PCI registration layer (or the IDE initialization)
  1226. * finds a device matching our IDE device tables.
  1227. */
  1228. static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  1229. {
  1230. const struct hpt_info *info = NULL;
  1231. struct hpt_info *dyn_info;
  1232. struct pci_dev *dev2 = NULL;
  1233. struct ide_port_info d;
  1234. u8 idx = id->driver_data;
  1235. u8 rev = dev->revision;
  1236. int ret;
  1237. if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
  1238. return -ENODEV;
  1239. switch (idx) {
  1240. case 0:
  1241. if (rev < 3)
  1242. info = &hpt36x;
  1243. else {
  1244. switch (min_t(u8, rev, 6)) {
  1245. case 3: info = &hpt370; break;
  1246. case 4: info = &hpt370a; break;
  1247. case 5: info = &hpt372; break;
  1248. case 6: info = &hpt372n; break;
  1249. }
  1250. idx++;
  1251. }
  1252. break;
  1253. case 1:
  1254. info = (rev > 1) ? &hpt372n : &hpt372a;
  1255. break;
  1256. case 2:
  1257. info = (rev > 1) ? &hpt302n : &hpt302;
  1258. break;
  1259. case 3:
  1260. hpt371_init(dev);
  1261. info = (rev > 1) ? &hpt371n : &hpt371;
  1262. break;
  1263. case 4:
  1264. info = &hpt374;
  1265. break;
  1266. case 5:
  1267. info = &hpt372n;
  1268. break;
  1269. }
  1270. printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
  1271. d = hpt366_chipsets[min_t(u8, idx, 1)];
  1272. d.udma_mask = info->udma_mask;
  1273. /* fixup ->dma_ops for HPT370/HPT370A */
  1274. if (info == &hpt370 || info == &hpt370a)
  1275. d.dma_ops = &hpt370_dma_ops;
  1276. if (info == &hpt36x || info == &hpt374)
  1277. dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
  1278. dyn_info = kcalloc(dev2 ? 2 : 1, sizeof(*dyn_info), GFP_KERNEL);
  1279. if (dyn_info == NULL) {
  1280. printk(KERN_ERR "%s %s: out of memory!\n",
  1281. d.name, pci_name(dev));
  1282. pci_dev_put(dev2);
  1283. return -ENOMEM;
  1284. }
  1285. /*
  1286. * Copy everything from a static "template" structure
  1287. * to just allocated per-chip hpt_info structure.
  1288. */
  1289. memcpy(dyn_info, info, sizeof(*dyn_info));
  1290. if (dev2) {
  1291. memcpy(dyn_info + 1, info, sizeof(*dyn_info));
  1292. if (info == &hpt374)
  1293. hpt374_init(dev, dev2);
  1294. else {
  1295. if (hpt36x_init(dev, dev2))
  1296. d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
  1297. }
  1298. ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
  1299. if (ret < 0) {
  1300. pci_dev_put(dev2);
  1301. kfree(dyn_info);
  1302. }
  1303. return ret;
  1304. }
  1305. ret = ide_pci_init_one(dev, &d, dyn_info);
  1306. if (ret < 0)
  1307. kfree(dyn_info);
  1308. return ret;
  1309. }
  1310. static void hpt366_remove(struct pci_dev *dev)
  1311. {
  1312. struct ide_host *host = pci_get_drvdata(dev);
  1313. struct ide_info *info = host->host_priv;
  1314. struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
  1315. ide_pci_remove(dev);
  1316. pci_dev_put(dev2);
  1317. kfree(info);
  1318. }
  1319. static const struct pci_device_id hpt366_pci_tbl[] = {
  1320. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
  1321. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
  1322. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
  1323. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
  1324. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
  1325. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
  1326. { 0, },
  1327. };
  1328. MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
  1329. static struct pci_driver hpt366_pci_driver = {
  1330. .name = "HPT366_IDE",
  1331. .id_table = hpt366_pci_tbl,
  1332. .probe = hpt366_init_one,
  1333. .remove = hpt366_remove,
  1334. .suspend = ide_pci_suspend,
  1335. .resume = ide_pci_resume,
  1336. };
  1337. static int __init hpt366_ide_init(void)
  1338. {
  1339. return ide_pci_register_driver(&hpt366_pci_driver);
  1340. }
  1341. static void __exit hpt366_ide_exit(void)
  1342. {
  1343. pci_unregister_driver(&hpt366_pci_driver);
  1344. }
  1345. module_init(hpt366_ide_init);
  1346. module_exit(hpt366_ide_exit);
  1347. MODULE_AUTHOR("Andre Hedrick");
  1348. MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
  1349. MODULE_LICENSE("GPL");