cs5536.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CS5536 PATA support
  4. * (C) 2007 Martin K. Petersen <mkp@mkp.net>
  5. * (C) 2009 Bartlomiej Zolnierkiewicz
  6. *
  7. * Documentation:
  8. * Available from AMD web site.
  9. *
  10. * The IDE timing registers for the CS5536 live in the Geode Machine
  11. * Specific Register file and not PCI config space. Most BIOSes
  12. * virtualize the PCI registers so the chip looks like a standard IDE
  13. * controller. Unfortunately not all implementations get this right.
  14. * In particular some have problems with unaligned accesses to the
  15. * virtualized PCI registers. This driver always does full dword
  16. * writes to work around the issue. Also, in case of a bad BIOS this
  17. * driver can be loaded with the "msr=1" parameter which forces using
  18. * the Machine Specific Registers to configure the device.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/pci.h>
  23. #include <linux/init.h>
  24. #include <linux/ide.h>
  25. #include <asm/msr.h>
  26. #define DRV_NAME "cs5536"
  27. enum {
  28. MSR_IDE_CFG = 0x51300010,
  29. PCI_IDE_CFG = 0x40,
  30. CFG = 0,
  31. DTC = 2,
  32. CAST = 3,
  33. ETC = 4,
  34. IDE_CFG_CHANEN = (1 << 1),
  35. IDE_CFG_CABLE = (1 << 17) | (1 << 16),
  36. IDE_D0_SHIFT = 24,
  37. IDE_D1_SHIFT = 16,
  38. IDE_DRV_MASK = 0xff,
  39. IDE_CAST_D0_SHIFT = 6,
  40. IDE_CAST_D1_SHIFT = 4,
  41. IDE_CAST_DRV_MASK = 0x3,
  42. IDE_CAST_CMD_SHIFT = 24,
  43. IDE_CAST_CMD_MASK = 0xff,
  44. IDE_ETC_UDMA_MASK = 0xc0,
  45. };
  46. static int use_msr;
  47. static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
  48. {
  49. if (unlikely(use_msr)) {
  50. u32 dummy;
  51. rdmsr(MSR_IDE_CFG + reg, *val, dummy);
  52. return 0;
  53. }
  54. return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
  55. }
  56. static int cs5536_write(struct pci_dev *pdev, int reg, int val)
  57. {
  58. if (unlikely(use_msr)) {
  59. wrmsr(MSR_IDE_CFG + reg, val, 0);
  60. return 0;
  61. }
  62. return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
  63. }
  64. static void cs5536_program_dtc(ide_drive_t *drive, u8 tim)
  65. {
  66. struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
  67. int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
  68. u32 dtc;
  69. cs5536_read(pdev, DTC, &dtc);
  70. dtc &= ~(IDE_DRV_MASK << dshift);
  71. dtc |= tim << dshift;
  72. cs5536_write(pdev, DTC, dtc);
  73. }
  74. /**
  75. * cs5536_cable_detect - detect cable type
  76. * @hwif: Port to detect on
  77. *
  78. * Perform cable detection for ATA66 capable cable.
  79. *
  80. * Returns a cable type.
  81. */
  82. static u8 cs5536_cable_detect(ide_hwif_t *hwif)
  83. {
  84. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  85. u32 cfg;
  86. cs5536_read(pdev, CFG, &cfg);
  87. if (cfg & IDE_CFG_CABLE)
  88. return ATA_CBL_PATA80;
  89. else
  90. return ATA_CBL_PATA40;
  91. }
  92. /**
  93. * cs5536_set_pio_mode - PIO timing setup
  94. * @hwif: ATA port
  95. * @drive: ATA device
  96. */
  97. static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  98. {
  99. static const u8 drv_timings[5] = {
  100. 0x98, 0x55, 0x32, 0x21, 0x20,
  101. };
  102. static const u8 addr_timings[5] = {
  103. 0x2, 0x1, 0x0, 0x0, 0x0,
  104. };
  105. static const u8 cmd_timings[5] = {
  106. 0x99, 0x92, 0x90, 0x22, 0x20,
  107. };
  108. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  109. ide_drive_t *pair = ide_get_pair_dev(drive);
  110. int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
  111. unsigned long timings = (unsigned long)ide_get_drivedata(drive);
  112. u32 cast;
  113. const u8 pio = drive->pio_mode - XFER_PIO_0;
  114. u8 cmd_pio = pio;
  115. if (pair)
  116. cmd_pio = min_t(u8, pio, pair->pio_mode - XFER_PIO_0);
  117. timings &= (IDE_DRV_MASK << 8);
  118. timings |= drv_timings[pio];
  119. ide_set_drivedata(drive, (void *)timings);
  120. cs5536_program_dtc(drive, drv_timings[pio]);
  121. cs5536_read(pdev, CAST, &cast);
  122. cast &= ~(IDE_CAST_DRV_MASK << cshift);
  123. cast |= addr_timings[pio] << cshift;
  124. cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
  125. cast |= cmd_timings[cmd_pio] << IDE_CAST_CMD_SHIFT;
  126. cs5536_write(pdev, CAST, cast);
  127. }
  128. /**
  129. * cs5536_set_dma_mode - DMA timing setup
  130. * @hwif: ATA port
  131. * @drive: ATA device
  132. */
  133. static void cs5536_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  134. {
  135. static const u8 udma_timings[6] = {
  136. 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
  137. };
  138. static const u8 mwdma_timings[3] = {
  139. 0x67, 0x21, 0x20,
  140. };
  141. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  142. int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
  143. unsigned long timings = (unsigned long)ide_get_drivedata(drive);
  144. u32 etc;
  145. const u8 mode = drive->dma_mode;
  146. cs5536_read(pdev, ETC, &etc);
  147. if (mode >= XFER_UDMA_0) {
  148. etc &= ~(IDE_DRV_MASK << dshift);
  149. etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
  150. } else { /* MWDMA */
  151. etc &= ~(IDE_ETC_UDMA_MASK << dshift);
  152. timings &= IDE_DRV_MASK;
  153. timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
  154. ide_set_drivedata(drive, (void *)timings);
  155. }
  156. cs5536_write(pdev, ETC, etc);
  157. }
  158. static void cs5536_dma_start(ide_drive_t *drive)
  159. {
  160. unsigned long timings = (unsigned long)ide_get_drivedata(drive);
  161. if (drive->current_speed < XFER_UDMA_0 &&
  162. (timings >> 8) != (timings & IDE_DRV_MASK))
  163. cs5536_program_dtc(drive, timings >> 8);
  164. ide_dma_start(drive);
  165. }
  166. static int cs5536_dma_end(ide_drive_t *drive)
  167. {
  168. int ret = ide_dma_end(drive);
  169. unsigned long timings = (unsigned long)ide_get_drivedata(drive);
  170. if (drive->current_speed < XFER_UDMA_0 &&
  171. (timings >> 8) != (timings & IDE_DRV_MASK))
  172. cs5536_program_dtc(drive, timings & IDE_DRV_MASK);
  173. return ret;
  174. }
  175. static const struct ide_port_ops cs5536_port_ops = {
  176. .set_pio_mode = cs5536_set_pio_mode,
  177. .set_dma_mode = cs5536_set_dma_mode,
  178. .cable_detect = cs5536_cable_detect,
  179. };
  180. static const struct ide_dma_ops cs5536_dma_ops = {
  181. .dma_host_set = ide_dma_host_set,
  182. .dma_setup = ide_dma_setup,
  183. .dma_start = cs5536_dma_start,
  184. .dma_end = cs5536_dma_end,
  185. .dma_test_irq = ide_dma_test_irq,
  186. .dma_lost_irq = ide_dma_lost_irq,
  187. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  188. .dma_sff_read_status = ide_dma_sff_read_status,
  189. };
  190. static const struct ide_port_info cs5536_info = {
  191. .name = DRV_NAME,
  192. .port_ops = &cs5536_port_ops,
  193. .dma_ops = &cs5536_dma_ops,
  194. .host_flags = IDE_HFLAG_SINGLE,
  195. .pio_mask = ATA_PIO4,
  196. .mwdma_mask = ATA_MWDMA2,
  197. .udma_mask = ATA_UDMA5,
  198. };
  199. /**
  200. * cs5536_init_one
  201. * @dev: PCI device
  202. * @id: Entry in match table
  203. */
  204. static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  205. {
  206. u32 cfg;
  207. if (use_msr)
  208. printk(KERN_INFO DRV_NAME ": Using MSR regs instead of PCI\n");
  209. cs5536_read(dev, CFG, &cfg);
  210. if ((cfg & IDE_CFG_CHANEN) == 0) {
  211. printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
  212. return -ENODEV;
  213. }
  214. return ide_pci_init_one(dev, &cs5536_info, NULL);
  215. }
  216. static const struct pci_device_id cs5536_pci_tbl[] = {
  217. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
  218. { },
  219. };
  220. static struct pci_driver cs5536_pci_driver = {
  221. .name = DRV_NAME,
  222. .id_table = cs5536_pci_tbl,
  223. .probe = cs5536_init_one,
  224. .remove = ide_pci_remove,
  225. .suspend = ide_pci_suspend,
  226. .resume = ide_pci_resume,
  227. };
  228. module_pci_driver(cs5536_pci_driver);
  229. MODULE_AUTHOR("Martin K. Petersen, Bartlomiej Zolnierkiewicz");
  230. MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
  231. MODULE_LICENSE("GPL");
  232. MODULE_DEVICE_TABLE(pci, cs5536_pci_tbl);
  233. module_param_named(msr, use_msr, int, 0644);
  234. MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");