cs5535.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
  4. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  5. *
  6. * History:
  7. * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
  8. * - Reworked tuneproc, set_drive, misc mods to prep for mainline
  9. * - Work was sponsored by CIS (M) Sdn Bhd.
  10. * Ported to Kernel 2.6.11 on June 26, 2005 by
  11. * Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
  12. * Alexander Kiausch <alex.kiausch@t-online.de>
  13. * Originally developed by AMD for 2.4/2.6
  14. *
  15. * Development of this chipset driver was funded
  16. * by the nice folks at National Semiconductor/AMD.
  17. *
  18. * Documentation:
  19. * CS5535 documentation available from AMD
  20. */
  21. #include <linux/module.h>
  22. #include <linux/pci.h>
  23. #include <linux/ide.h>
  24. #define DRV_NAME "cs5535"
  25. #define MSR_ATAC_BASE 0x51300000
  26. #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
  27. #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
  28. #define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
  29. #define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
  30. #define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
  31. #define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
  32. #define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
  33. #define ATAC_RESET (MSR_ATAC_BASE+0x10)
  34. #define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
  35. #define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
  36. #define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
  37. #define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
  38. #define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
  39. #define ATAC_BM0_CMD_PRIM 0x00
  40. #define ATAC_BM0_STS_PRIM 0x02
  41. #define ATAC_BM0_PRD 0x04
  42. #define CS5535_CABLE_DETECT 0x48
  43. /* Format I PIO settings. We separate out cmd and data for safer timings */
  44. static unsigned int cs5535_pio_cmd_timings[5] =
  45. { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
  46. static unsigned int cs5535_pio_dta_timings[5] =
  47. { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
  48. static unsigned int cs5535_mwdma_timings[3] =
  49. { 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
  50. static unsigned int cs5535_udma_timings[5] =
  51. { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
  52. /* Macros to check if the register is the reset value - reset value is an
  53. invalid timing and indicates the register has not been set previously */
  54. #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
  55. #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
  56. /****
  57. * cs5535_set_speed - Configure the chipset to the new speed
  58. * @drive: Drive to set up
  59. * @speed: desired speed
  60. *
  61. * cs5535_set_speed() configures the chipset to a new speed.
  62. */
  63. static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
  64. {
  65. u32 reg = 0, dummy;
  66. u8 unit = drive->dn & 1;
  67. /* Set the PIO timings */
  68. if (speed < XFER_SW_DMA_0) {
  69. ide_drive_t *pair = ide_get_pair_dev(drive);
  70. u8 cmd, pioa;
  71. cmd = pioa = speed - XFER_PIO_0;
  72. if (pair) {
  73. u8 piob = pair->pio_mode - XFER_PIO_0;
  74. if (piob < cmd)
  75. cmd = piob;
  76. }
  77. /* Write the speed of the current drive */
  78. reg = (cs5535_pio_cmd_timings[cmd] << 16) |
  79. cs5535_pio_dta_timings[pioa];
  80. wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
  81. /* And if nessesary - change the speed of the other drive */
  82. rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
  83. if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
  84. cs5535_pio_cmd_timings[cmd]) {
  85. reg &= 0x0000FFFF;
  86. reg |= cs5535_pio_cmd_timings[cmd] << 16;
  87. wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
  88. }
  89. /* Set bit 31 of the DMA register for PIO format 1 timings */
  90. rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
  91. wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
  92. reg | 0x80000000UL, 0);
  93. } else {
  94. rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
  95. reg &= 0x80000000UL; /* Preserve the PIO format bit */
  96. if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
  97. reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
  98. else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
  99. reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
  100. else
  101. return;
  102. wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
  103. }
  104. }
  105. /**
  106. * cs5535_set_dma_mode - set host controller for DMA mode
  107. * @hwif: port
  108. * @drive: drive
  109. *
  110. * Programs the chipset for DMA mode.
  111. */
  112. static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  113. {
  114. cs5535_set_speed(drive, drive->dma_mode);
  115. }
  116. /**
  117. * cs5535_set_pio_mode - set host controller for PIO mode
  118. * @hwif: port
  119. * @drive: drive
  120. *
  121. * A callback from the upper layers for PIO-only tuning.
  122. */
  123. static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  124. {
  125. cs5535_set_speed(drive, drive->pio_mode);
  126. }
  127. static u8 cs5535_cable_detect(ide_hwif_t *hwif)
  128. {
  129. struct pci_dev *dev = to_pci_dev(hwif->dev);
  130. u8 bit;
  131. /* if a 80 wire cable was detected */
  132. pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
  133. return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  134. }
  135. static const struct ide_port_ops cs5535_port_ops = {
  136. .set_pio_mode = cs5535_set_pio_mode,
  137. .set_dma_mode = cs5535_set_dma_mode,
  138. .cable_detect = cs5535_cable_detect,
  139. };
  140. static const struct ide_port_info cs5535_chipset = {
  141. .name = DRV_NAME,
  142. .port_ops = &cs5535_port_ops,
  143. .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
  144. .pio_mask = ATA_PIO4,
  145. .mwdma_mask = ATA_MWDMA2,
  146. .udma_mask = ATA_UDMA4,
  147. };
  148. static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  149. {
  150. return ide_pci_init_one(dev, &cs5535_chipset, NULL);
  151. }
  152. static const struct pci_device_id cs5535_pci_tbl[] = {
  153. { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
  154. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
  155. { 0, },
  156. };
  157. MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
  158. static struct pci_driver cs5535_pci_driver = {
  159. .name = "CS5535_IDE",
  160. .id_table = cs5535_pci_tbl,
  161. .probe = cs5535_init_one,
  162. .remove = ide_pci_remove,
  163. .suspend = ide_pci_suspend,
  164. .resume = ide_pci_resume,
  165. };
  166. static int __init cs5535_ide_init(void)
  167. {
  168. return ide_pci_register_driver(&cs5535_pci_driver);
  169. }
  170. static void __exit cs5535_ide_exit(void)
  171. {
  172. pci_unregister_driver(&cs5535_pci_driver);
  173. }
  174. module_init(cs5535_ide_init);
  175. module_exit(cs5535_ide_exit);
  176. MODULE_AUTHOR("AMD");
  177. MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
  178. MODULE_LICENSE("GPL");