cs5520.c 4.7 KB

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  1. /*
  2. * IDE tuning and bus mastering support for the CS5510/CS5520
  3. * chipsets
  4. *
  5. * The CS5510/CS5520 are slightly unusual devices. Unlike the
  6. * typical IDE controllers they do bus mastering with the drive in
  7. * PIO mode and smarter silicon.
  8. *
  9. * The practical upshot of this is that we must always tune the
  10. * drive for the right PIO mode. We must also ignore all the blacklists
  11. * and the drive bus mastering DMA information.
  12. *
  13. * *** This driver is strictly experimental ***
  14. *
  15. * (c) Copyright Red Hat Inc 2002
  16. *
  17. * This program is free software; you can redistribute it and/or modify it
  18. * under the terms of the GNU General Public License as published by the
  19. * Free Software Foundation; either version 2, or (at your option) any
  20. * later version.
  21. *
  22. * This program is distributed in the hope that it will be useful, but
  23. * WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  25. * General Public License for more details.
  26. *
  27. * For the avoidance of doubt the "preferred form" of this code is one which
  28. * is in an open non patent encumbered format. Where cryptographic key signing
  29. * forms part of the process of creating an executable the information
  30. * including keys needed to generate an equivalently functional executable
  31. * are deemed to be part of the source code.
  32. *
  33. */
  34. #include <linux/module.h>
  35. #include <linux/types.h>
  36. #include <linux/kernel.h>
  37. #include <linux/init.h>
  38. #include <linux/pci.h>
  39. #include <linux/ide.h>
  40. #include <linux/dma-mapping.h>
  41. #define DRV_NAME "cs5520"
  42. struct pio_clocks
  43. {
  44. int address;
  45. int assert;
  46. int recovery;
  47. };
  48. static struct pio_clocks cs5520_pio_clocks[]={
  49. {3, 6, 11},
  50. {2, 5, 6},
  51. {1, 4, 3},
  52. {1, 3, 2},
  53. {1, 2, 1}
  54. };
  55. static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  56. {
  57. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  58. int controller = drive->dn > 1 ? 1 : 0;
  59. const u8 pio = drive->pio_mode - XFER_PIO_0;
  60. /* 8bit CAT/CRT - 8bit command timing for channel */
  61. pci_write_config_byte(pdev, 0x62 + controller,
  62. (cs5520_pio_clocks[pio].recovery << 4) |
  63. (cs5520_pio_clocks[pio].assert));
  64. /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
  65. /* FIXME: should these use address ? */
  66. /* Data read timing */
  67. pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
  68. (cs5520_pio_clocks[pio].recovery << 4) |
  69. (cs5520_pio_clocks[pio].assert));
  70. /* Write command timing */
  71. pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
  72. (cs5520_pio_clocks[pio].recovery << 4) |
  73. (cs5520_pio_clocks[pio].assert));
  74. }
  75. static void cs5520_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  76. {
  77. printk(KERN_ERR "cs55x0: bad ide timing.\n");
  78. drive->pio_mode = XFER_PIO_0 + 0;
  79. cs5520_set_pio_mode(hwif, drive);
  80. }
  81. static const struct ide_port_ops cs5520_port_ops = {
  82. .set_pio_mode = cs5520_set_pio_mode,
  83. .set_dma_mode = cs5520_set_dma_mode,
  84. };
  85. static const struct ide_port_info cyrix_chipset = {
  86. .name = DRV_NAME,
  87. .enablebits = { { 0x60, 0x01, 0x01 }, { 0x60, 0x02, 0x02 } },
  88. .port_ops = &cs5520_port_ops,
  89. .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_CS5520,
  90. .pio_mask = ATA_PIO4,
  91. };
  92. /*
  93. * The 5510/5520 are a bit weird. They don't quite set up the way
  94. * the PCI helper layer expects so we must do much of the set up
  95. * work longhand.
  96. */
  97. static int cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  98. {
  99. const struct ide_port_info *d = &cyrix_chipset;
  100. struct ide_hw hw[2], *hws[] = { NULL, NULL };
  101. ide_setup_pci_noise(dev, d);
  102. /* We must not grab the entire device, it has 'ISA' space in its
  103. * BARS too and we will freak out other bits of the kernel
  104. */
  105. if (pci_enable_device_io(dev)) {
  106. printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
  107. return -ENODEV;
  108. }
  109. pci_set_master(dev);
  110. if (dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) {
  111. printk(KERN_WARNING "%s: No suitable DMA available.\n",
  112. d->name);
  113. return -ENODEV;
  114. }
  115. /*
  116. * Now the chipset is configured we can let the core
  117. * do all the device setup for us
  118. */
  119. ide_pci_setup_ports(dev, d, &hw[0], &hws[0]);
  120. hw[0].irq = 14;
  121. hw[1].irq = 15;
  122. return ide_host_add(d, hws, 2, NULL);
  123. }
  124. static const struct pci_device_id cs5520_pci_tbl[] = {
  125. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
  126. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
  127. { 0, },
  128. };
  129. MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
  130. static struct pci_driver cs5520_pci_driver = {
  131. .name = "Cyrix_IDE",
  132. .id_table = cs5520_pci_tbl,
  133. .probe = cs5520_init_one,
  134. .suspend = ide_pci_suspend,
  135. .resume = ide_pci_resume,
  136. };
  137. static int __init cs5520_ide_init(void)
  138. {
  139. return ide_pci_register_driver(&cs5520_pci_driver);
  140. }
  141. module_init(cs5520_ide_init);
  142. MODULE_AUTHOR("Alan Cox");
  143. MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
  144. MODULE_LICENSE("GPL");