alim15x3.c 15 KB

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  1. /*
  2. * Copyright (C) 1998-2000 Michel Aubry, Maintainer
  3. * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
  4. * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
  5. *
  6. * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
  7. * May be copied or modified under the terms of the GNU General Public License
  8. * Copyright (C) 2002 Alan Cox
  9. * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
  10. * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
  11. * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
  12. *
  13. * (U)DMA capable version of ali 1533/1543(C), 1535(D)
  14. *
  15. **********************************************************************
  16. * 9/7/99 --Parts from the above author are included and need to be
  17. * converted into standard interface, once I finish the thought.
  18. *
  19. * Recent changes
  20. * Don't use LBA48 mode on ALi <= 0xC4
  21. * Don't poke 0x79 with a non ALi northbridge
  22. * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
  23. * Allow UDMA6 on revisions > 0xC4
  24. *
  25. * Documentation
  26. * Chipset documentation available under NDA only
  27. *
  28. */
  29. #include <linux/module.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/pci.h>
  33. #include <linux/ide.h>
  34. #include <linux/init.h>
  35. #include <linux/dmi.h>
  36. #include <asm/io.h>
  37. #define DRV_NAME "alim15x3"
  38. /*
  39. * ALi devices are not plug in. Otherwise these static values would
  40. * need to go. They ought to go away anyway
  41. */
  42. static u8 m5229_revision;
  43. static u8 chip_is_1543c_e;
  44. static struct pci_dev *isa_dev;
  45. static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
  46. {
  47. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  48. int pio_fifo = 0x54 + hwif->channel;
  49. u8 fifo;
  50. int shift = 4 * (drive->dn & 1);
  51. pci_read_config_byte(pdev, pio_fifo, &fifo);
  52. fifo &= ~(0x0F << shift);
  53. fifo |= (on << shift);
  54. pci_write_config_byte(pdev, pio_fifo, fifo);
  55. }
  56. static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive,
  57. struct ide_timing *t, u8 ultra)
  58. {
  59. struct pci_dev *dev = to_pci_dev(hwif->dev);
  60. int port = hwif->channel ? 0x5c : 0x58;
  61. int udmat = 0x56 + hwif->channel;
  62. u8 unit = drive->dn & 1, udma;
  63. int shift = 4 * unit;
  64. /* Set up the UDMA */
  65. pci_read_config_byte(dev, udmat, &udma);
  66. udma &= ~(0x0F << shift);
  67. udma |= ultra << shift;
  68. pci_write_config_byte(dev, udmat, udma);
  69. if (t == NULL)
  70. return;
  71. t->setup = clamp_val(t->setup, 1, 8) & 7;
  72. t->act8b = clamp_val(t->act8b, 1, 8) & 7;
  73. t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
  74. t->active = clamp_val(t->active, 1, 8) & 7;
  75. t->recover = clamp_val(t->recover, 1, 16) & 15;
  76. pci_write_config_byte(dev, port, t->setup);
  77. pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b);
  78. pci_write_config_byte(dev, port + unit + 2,
  79. (t->active << 4) | t->recover);
  80. }
  81. /**
  82. * ali_set_pio_mode - set host controller for PIO mode
  83. * @hwif: port
  84. * @drive: drive
  85. *
  86. * Program the controller for the given PIO mode.
  87. */
  88. static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  89. {
  90. ide_drive_t *pair = ide_get_pair_dev(drive);
  91. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  92. unsigned long T = 1000000 / bus_speed; /* PCI clock based */
  93. struct ide_timing t;
  94. ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
  95. if (pair) {
  96. struct ide_timing p;
  97. ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
  98. ide_timing_merge(&p, &t, &t,
  99. IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  100. if (pair->dma_mode) {
  101. ide_timing_compute(pair, pair->dma_mode, &p, T, 1);
  102. ide_timing_merge(&p, &t, &t,
  103. IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  104. }
  105. }
  106. /*
  107. * PIO mode => ATA FIFO on, ATAPI FIFO off
  108. */
  109. ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00);
  110. ali_program_timings(hwif, drive, &t, 0);
  111. }
  112. /**
  113. * ali_udma_filter - compute UDMA mask
  114. * @drive: IDE device
  115. *
  116. * Return available UDMA modes.
  117. *
  118. * The actual rules for the ALi are:
  119. * No UDMA on revisions <= 0x20
  120. * Disk only for revisions < 0xC2
  121. * Not WDC drives on M1543C-E (?)
  122. */
  123. static u8 ali_udma_filter(ide_drive_t *drive)
  124. {
  125. if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
  126. if (drive->media != ide_disk)
  127. return 0;
  128. if (chip_is_1543c_e &&
  129. strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
  130. return 0;
  131. }
  132. return drive->hwif->ultra_mask;
  133. }
  134. /**
  135. * ali_set_dma_mode - set host controller for DMA mode
  136. * @hwif: port
  137. * @drive: drive
  138. *
  139. * Configure the hardware for the desired IDE transfer mode.
  140. */
  141. static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  142. {
  143. static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
  144. struct pci_dev *dev = to_pci_dev(hwif->dev);
  145. ide_drive_t *pair = ide_get_pair_dev(drive);
  146. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  147. unsigned long T = 1000000 / bus_speed; /* PCI clock based */
  148. const u8 speed = drive->dma_mode;
  149. u8 tmpbyte = 0x00;
  150. struct ide_timing t;
  151. if (speed < XFER_UDMA_0) {
  152. ide_timing_compute(drive, drive->dma_mode, &t, T, 1);
  153. if (pair) {
  154. struct ide_timing p;
  155. ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
  156. ide_timing_merge(&p, &t, &t,
  157. IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  158. if (pair->dma_mode) {
  159. ide_timing_compute(pair, pair->dma_mode,
  160. &p, T, 1);
  161. ide_timing_merge(&p, &t, &t,
  162. IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  163. }
  164. }
  165. ali_program_timings(hwif, drive, &t, 0);
  166. } else {
  167. ali_program_timings(hwif, drive, NULL,
  168. udma_timing[speed - XFER_UDMA_0]);
  169. if (speed >= XFER_UDMA_3) {
  170. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  171. tmpbyte |= 1;
  172. pci_write_config_byte(dev, 0x4b, tmpbyte);
  173. }
  174. }
  175. }
  176. /**
  177. * ali_dma_check - DMA check
  178. * @drive: target device
  179. * @cmd: command
  180. *
  181. * Returns 1 if the DMA cannot be performed, zero on success.
  182. */
  183. static int ali_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
  184. {
  185. if (m5229_revision < 0xC2 && drive->media != ide_disk) {
  186. if (cmd->tf_flags & IDE_TFLAG_WRITE)
  187. return 1; /* try PIO instead of DMA */
  188. }
  189. return 0;
  190. }
  191. /**
  192. * init_chipset_ali15x3 - Initialise an ALi IDE controller
  193. * @dev: PCI device
  194. *
  195. * This function initializes the ALI IDE controller and where
  196. * appropriate also sets up the 1533 southbridge.
  197. */
  198. static int init_chipset_ali15x3(struct pci_dev *dev)
  199. {
  200. unsigned long flags;
  201. u8 tmpbyte;
  202. struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
  203. m5229_revision = dev->revision;
  204. isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
  205. local_irq_save(flags);
  206. if (m5229_revision < 0xC2) {
  207. /*
  208. * revision 0x20 (1543-E, 1543-F)
  209. * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
  210. * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
  211. */
  212. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  213. /*
  214. * clear bit 7
  215. */
  216. pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
  217. /*
  218. * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
  219. */
  220. if (m5229_revision >= 0x20 && isa_dev) {
  221. pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
  222. chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
  223. }
  224. goto out;
  225. }
  226. /*
  227. * 1543C-B?, 1535, 1535D, 1553
  228. * Note 1: not all "motherboard" support this detection
  229. * Note 2: if no udma 66 device, the detection may "error".
  230. * but in this case, we will not set the device to
  231. * ultra 66, the detection result is not important
  232. */
  233. /*
  234. * enable "Cable Detection", m5229, 0x4b, bit3
  235. */
  236. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  237. pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
  238. /*
  239. * We should only tune the 1533 enable if we are using an ALi
  240. * North bridge. We might have no north found on some zany
  241. * box without a device at 0:0.0. The ALi bridge will be at
  242. * 0:0.0 so if we didn't find one we know what is cooking.
  243. */
  244. if (north && north->vendor != PCI_VENDOR_ID_AL)
  245. goto out;
  246. if (m5229_revision < 0xC5 && isa_dev)
  247. {
  248. /*
  249. * set south-bridge's enable bit, m1533, 0x79
  250. */
  251. pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
  252. if (m5229_revision == 0xC2) {
  253. /*
  254. * 1543C-B0 (m1533, 0x79, bit 2)
  255. */
  256. pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
  257. } else if (m5229_revision >= 0xC3) {
  258. /*
  259. * 1553/1535 (m1533, 0x79, bit 1)
  260. */
  261. pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
  262. }
  263. }
  264. out:
  265. /*
  266. * CD_ROM DMA on (m5229, 0x53, bit0)
  267. * Enable this bit even if we want to use PIO.
  268. * PIO FIFO off (m5229, 0x53, bit1)
  269. * The hardware will use 0x54h and 0x55h to control PIO FIFO.
  270. * (Not on later devices it seems)
  271. *
  272. * 0x53 changes meaning on later revs - we must no touch
  273. * bit 1 on them. Need to check if 0x20 is the right break.
  274. */
  275. if (m5229_revision >= 0x20) {
  276. pci_read_config_byte(dev, 0x53, &tmpbyte);
  277. if (m5229_revision <= 0x20)
  278. tmpbyte = (tmpbyte & (~0x02)) | 0x01;
  279. else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
  280. tmpbyte |= 0x03;
  281. else
  282. tmpbyte |= 0x01;
  283. pci_write_config_byte(dev, 0x53, tmpbyte);
  284. }
  285. local_irq_restore(flags);
  286. pci_dev_put(north);
  287. pci_dev_put(isa_dev);
  288. return 0;
  289. }
  290. /*
  291. * Cable special cases
  292. */
  293. static const struct dmi_system_id cable_dmi_table[] = {
  294. {
  295. .ident = "HP Pavilion N5430",
  296. .matches = {
  297. DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
  298. DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
  299. },
  300. },
  301. {
  302. .ident = "Toshiba Satellite S1800-814",
  303. .matches = {
  304. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  305. DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
  306. },
  307. },
  308. { }
  309. };
  310. static int ali_cable_override(struct pci_dev *pdev)
  311. {
  312. /* Fujitsu P2000 */
  313. if (pdev->subsystem_vendor == 0x10CF &&
  314. pdev->subsystem_device == 0x10AF)
  315. return 1;
  316. /* Mitac 8317 (Winbook-A) and relatives */
  317. if (pdev->subsystem_vendor == 0x1071 &&
  318. pdev->subsystem_device == 0x8317)
  319. return 1;
  320. /* Systems by DMI */
  321. if (dmi_check_system(cable_dmi_table))
  322. return 1;
  323. return 0;
  324. }
  325. /**
  326. * ali_cable_detect - cable detection
  327. * @hwif: IDE interface
  328. *
  329. * This checks if the controller and the cable are capable
  330. * of UDMA66 transfers. It doesn't check the drives.
  331. */
  332. static u8 ali_cable_detect(ide_hwif_t *hwif)
  333. {
  334. struct pci_dev *dev = to_pci_dev(hwif->dev);
  335. u8 cbl = ATA_CBL_PATA40, tmpbyte;
  336. if (m5229_revision >= 0xC2) {
  337. /*
  338. * m5229 80-pin cable detection (from Host View)
  339. *
  340. * 0x4a bit0 is 0 => primary channel has 80-pin
  341. * 0x4a bit1 is 0 => secondary channel has 80-pin
  342. *
  343. * Certain laptops use short but suitable cables
  344. * and don't implement the detect logic.
  345. */
  346. if (ali_cable_override(dev))
  347. cbl = ATA_CBL_PATA40_SHORT;
  348. else {
  349. pci_read_config_byte(dev, 0x4a, &tmpbyte);
  350. if ((tmpbyte & (1 << hwif->channel)) == 0)
  351. cbl = ATA_CBL_PATA80;
  352. }
  353. }
  354. return cbl;
  355. }
  356. #ifndef CONFIG_SPARC64
  357. /**
  358. * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
  359. * @hwif: interface to configure
  360. *
  361. * Obtain the IRQ tables for an ALi based IDE solution on the PC
  362. * class platforms. This part of the code isn't applicable to the
  363. * Sparc systems.
  364. */
  365. static void init_hwif_ali15x3(ide_hwif_t *hwif)
  366. {
  367. u8 ideic, inmir;
  368. s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
  369. 1, 11, 0, 12, 0, 14, 0, 15 };
  370. int irq = -1;
  371. if (isa_dev) {
  372. /*
  373. * read IDE interface control
  374. */
  375. pci_read_config_byte(isa_dev, 0x58, &ideic);
  376. /* bit0, bit1 */
  377. ideic = ideic & 0x03;
  378. /* get IRQ for IDE Controller */
  379. if ((hwif->channel && ideic == 0x03) ||
  380. (!hwif->channel && !ideic)) {
  381. /*
  382. * get SIRQ1 routing table
  383. */
  384. pci_read_config_byte(isa_dev, 0x44, &inmir);
  385. inmir = inmir & 0x0f;
  386. irq = irq_routing_table[inmir];
  387. } else if (hwif->channel && !(ideic & 0x01)) {
  388. /*
  389. * get SIRQ2 routing table
  390. */
  391. pci_read_config_byte(isa_dev, 0x75, &inmir);
  392. inmir = inmir & 0x0f;
  393. irq = irq_routing_table[inmir];
  394. }
  395. if(irq >= 0)
  396. hwif->irq = irq;
  397. }
  398. }
  399. #else
  400. #define init_hwif_ali15x3 NULL
  401. #endif /* CONFIG_SPARC64 */
  402. /**
  403. * init_dma_ali15x3 - set up DMA on ALi15x3
  404. * @hwif: IDE interface
  405. * @d: IDE port info
  406. *
  407. * Set up the DMA functionality on the ALi 15x3.
  408. */
  409. static int init_dma_ali15x3(ide_hwif_t *hwif, const struct ide_port_info *d)
  410. {
  411. struct pci_dev *dev = to_pci_dev(hwif->dev);
  412. unsigned long base = ide_pci_dma_base(hwif, d);
  413. if (base == 0)
  414. return -1;
  415. hwif->dma_base = base;
  416. if (ide_pci_check_simplex(hwif, d) < 0)
  417. return -1;
  418. if (ide_pci_set_master(dev, d->name) < 0)
  419. return -1;
  420. if (!hwif->channel)
  421. outb(inb(base + 2) & 0x60, base + 2);
  422. printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
  423. hwif->name, base, base + 7);
  424. if (ide_allocate_dma_engine(hwif))
  425. return -1;
  426. return 0;
  427. }
  428. static const struct ide_port_ops ali_port_ops = {
  429. .set_pio_mode = ali_set_pio_mode,
  430. .set_dma_mode = ali_set_dma_mode,
  431. .udma_filter = ali_udma_filter,
  432. .cable_detect = ali_cable_detect,
  433. };
  434. static const struct ide_dma_ops ali_dma_ops = {
  435. .dma_host_set = ide_dma_host_set,
  436. .dma_setup = ide_dma_setup,
  437. .dma_start = ide_dma_start,
  438. .dma_end = ide_dma_end,
  439. .dma_test_irq = ide_dma_test_irq,
  440. .dma_lost_irq = ide_dma_lost_irq,
  441. .dma_check = ali_dma_check,
  442. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  443. .dma_sff_read_status = ide_dma_sff_read_status,
  444. };
  445. static const struct ide_port_info ali15x3_chipset = {
  446. .name = DRV_NAME,
  447. .init_chipset = init_chipset_ali15x3,
  448. .init_hwif = init_hwif_ali15x3,
  449. .init_dma = init_dma_ali15x3,
  450. .port_ops = &ali_port_ops,
  451. .dma_ops = &sff_dma_ops,
  452. .pio_mask = ATA_PIO5,
  453. .swdma_mask = ATA_SWDMA2,
  454. .mwdma_mask = ATA_MWDMA2,
  455. };
  456. /**
  457. * alim15x3_init_one - set up an ALi15x3 IDE controller
  458. * @dev: PCI device to set up
  459. *
  460. * Perform the actual set up for an ALi15x3 that has been found by the
  461. * hot plug layer.
  462. */
  463. static int alim15x3_init_one(struct pci_dev *dev,
  464. const struct pci_device_id *id)
  465. {
  466. struct ide_port_info d = ali15x3_chipset;
  467. u8 rev = dev->revision, idx = id->driver_data;
  468. /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
  469. if (rev <= 0xC4)
  470. d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
  471. if (rev >= 0x20) {
  472. if (rev == 0x20)
  473. d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  474. if (rev < 0xC2)
  475. d.udma_mask = ATA_UDMA2;
  476. else if (rev == 0xC2 || rev == 0xC3)
  477. d.udma_mask = ATA_UDMA4;
  478. else if (rev == 0xC4)
  479. d.udma_mask = ATA_UDMA5;
  480. else
  481. d.udma_mask = ATA_UDMA6;
  482. d.dma_ops = &ali_dma_ops;
  483. } else {
  484. d.host_flags |= IDE_HFLAG_NO_DMA;
  485. d.mwdma_mask = d.swdma_mask = 0;
  486. }
  487. if (idx == 0)
  488. d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
  489. return ide_pci_init_one(dev, &d, NULL);
  490. }
  491. static const struct pci_device_id alim15x3_pci_tbl[] = {
  492. { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
  493. { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
  494. { 0, },
  495. };
  496. MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
  497. static struct pci_driver alim15x3_pci_driver = {
  498. .name = "ALI15x3_IDE",
  499. .id_table = alim15x3_pci_tbl,
  500. .probe = alim15x3_init_one,
  501. .remove = ide_pci_remove,
  502. .suspend = ide_pci_suspend,
  503. .resume = ide_pci_resume,
  504. };
  505. static int __init ali15x3_ide_init(void)
  506. {
  507. return ide_pci_register_driver(&alim15x3_pci_driver);
  508. }
  509. static void __exit ali15x3_ide_exit(void)
  510. {
  511. pci_unregister_driver(&alim15x3_pci_driver);
  512. }
  513. module_init(ali15x3_ide_init);
  514. module_exit(ali15x3_ide_exit);
  515. MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz");
  516. MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
  517. MODULE_LICENSE("GPL");