aec62xx.c 9.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
  4. * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
  5. *
  6. */
  7. #include <linux/module.h>
  8. #include <linux/types.h>
  9. #include <linux/pci.h>
  10. #include <linux/ide.h>
  11. #include <linux/init.h>
  12. #include <asm/io.h>
  13. #define DRV_NAME "aec62xx"
  14. struct chipset_bus_clock_list_entry {
  15. u8 xfer_speed;
  16. u8 chipset_settings;
  17. u8 ultra_settings;
  18. };
  19. static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  20. { XFER_UDMA_6, 0x31, 0x07 },
  21. { XFER_UDMA_5, 0x31, 0x06 },
  22. { XFER_UDMA_4, 0x31, 0x05 },
  23. { XFER_UDMA_3, 0x31, 0x04 },
  24. { XFER_UDMA_2, 0x31, 0x03 },
  25. { XFER_UDMA_1, 0x31, 0x02 },
  26. { XFER_UDMA_0, 0x31, 0x01 },
  27. { XFER_MW_DMA_2, 0x31, 0x00 },
  28. { XFER_MW_DMA_1, 0x31, 0x00 },
  29. { XFER_MW_DMA_0, 0x0a, 0x00 },
  30. { XFER_PIO_4, 0x31, 0x00 },
  31. { XFER_PIO_3, 0x33, 0x00 },
  32. { XFER_PIO_2, 0x08, 0x00 },
  33. { XFER_PIO_1, 0x0a, 0x00 },
  34. { XFER_PIO_0, 0x00, 0x00 },
  35. { 0, 0x00, 0x00 }
  36. };
  37. static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  38. { XFER_UDMA_6, 0x41, 0x06 },
  39. { XFER_UDMA_5, 0x41, 0x05 },
  40. { XFER_UDMA_4, 0x41, 0x04 },
  41. { XFER_UDMA_3, 0x41, 0x03 },
  42. { XFER_UDMA_2, 0x41, 0x02 },
  43. { XFER_UDMA_1, 0x41, 0x01 },
  44. { XFER_UDMA_0, 0x41, 0x01 },
  45. { XFER_MW_DMA_2, 0x41, 0x00 },
  46. { XFER_MW_DMA_1, 0x42, 0x00 },
  47. { XFER_MW_DMA_0, 0x7a, 0x00 },
  48. { XFER_PIO_4, 0x41, 0x00 },
  49. { XFER_PIO_3, 0x43, 0x00 },
  50. { XFER_PIO_2, 0x78, 0x00 },
  51. { XFER_PIO_1, 0x7a, 0x00 },
  52. { XFER_PIO_0, 0x70, 0x00 },
  53. { 0, 0x00, 0x00 }
  54. };
  55. /*
  56. * TO DO: active tuning and correction of cards without a bios.
  57. */
  58. static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  59. {
  60. for ( ; chipset_table->xfer_speed ; chipset_table++)
  61. if (chipset_table->xfer_speed == speed) {
  62. return chipset_table->chipset_settings;
  63. }
  64. return chipset_table->chipset_settings;
  65. }
  66. static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  67. {
  68. for ( ; chipset_table->xfer_speed ; chipset_table++)
  69. if (chipset_table->xfer_speed == speed) {
  70. return chipset_table->ultra_settings;
  71. }
  72. return chipset_table->ultra_settings;
  73. }
  74. static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  75. {
  76. struct pci_dev *dev = to_pci_dev(hwif->dev);
  77. struct ide_host *host = pci_get_drvdata(dev);
  78. struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
  79. u16 d_conf = 0;
  80. u8 ultra = 0, ultra_conf = 0;
  81. u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
  82. const u8 speed = drive->dma_mode;
  83. unsigned long flags;
  84. local_irq_save(flags);
  85. /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
  86. pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
  87. tmp0 = pci_bus_clock_list(speed, bus_clock);
  88. d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
  89. pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
  90. tmp1 = 0x00;
  91. tmp2 = 0x00;
  92. pci_read_config_byte(dev, 0x54, &ultra);
  93. tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
  94. ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
  95. tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
  96. pci_write_config_byte(dev, 0x54, tmp2);
  97. local_irq_restore(flags);
  98. }
  99. static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  100. {
  101. struct pci_dev *dev = to_pci_dev(hwif->dev);
  102. struct ide_host *host = pci_get_drvdata(dev);
  103. struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
  104. u8 unit = drive->dn & 1;
  105. u8 tmp1 = 0, tmp2 = 0;
  106. u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
  107. const u8 speed = drive->dma_mode;
  108. unsigned long flags;
  109. local_irq_save(flags);
  110. /* high 4-bits: Active, low 4-bits: Recovery */
  111. pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
  112. drive_conf = pci_bus_clock_list(speed, bus_clock);
  113. pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
  114. pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
  115. tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
  116. ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
  117. tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
  118. pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
  119. local_irq_restore(flags);
  120. }
  121. static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  122. {
  123. drive->dma_mode = drive->pio_mode;
  124. hwif->port_ops->set_dma_mode(hwif, drive);
  125. }
  126. static int init_chipset_aec62xx(struct pci_dev *dev)
  127. {
  128. /* These are necessary to get AEC6280 Macintosh cards to work */
  129. if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
  130. (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
  131. u8 reg49h = 0, reg4ah = 0;
  132. /* Clear reset and test bits. */
  133. pci_read_config_byte(dev, 0x49, &reg49h);
  134. pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
  135. /* Enable chip interrupt output. */
  136. pci_read_config_byte(dev, 0x4a, &reg4ah);
  137. pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
  138. /* Enable burst mode. */
  139. pci_read_config_byte(dev, 0x4a, &reg4ah);
  140. pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
  141. }
  142. return 0;
  143. }
  144. static u8 atp86x_cable_detect(ide_hwif_t *hwif)
  145. {
  146. struct pci_dev *dev = to_pci_dev(hwif->dev);
  147. u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
  148. pci_read_config_byte(dev, 0x49, &ata66);
  149. return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
  150. }
  151. static const struct ide_port_ops atp850_port_ops = {
  152. .set_pio_mode = aec_set_pio_mode,
  153. .set_dma_mode = aec6210_set_mode,
  154. };
  155. static const struct ide_port_ops atp86x_port_ops = {
  156. .set_pio_mode = aec_set_pio_mode,
  157. .set_dma_mode = aec6260_set_mode,
  158. .cable_detect = atp86x_cable_detect,
  159. };
  160. static const struct ide_port_info aec62xx_chipsets[] = {
  161. { /* 0: AEC6210 */
  162. .name = DRV_NAME,
  163. .init_chipset = init_chipset_aec62xx,
  164. .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
  165. .port_ops = &atp850_port_ops,
  166. .host_flags = IDE_HFLAG_SERIALIZE |
  167. IDE_HFLAG_NO_ATAPI_DMA |
  168. IDE_HFLAG_NO_DSC |
  169. IDE_HFLAG_OFF_BOARD,
  170. .pio_mask = ATA_PIO4,
  171. .mwdma_mask = ATA_MWDMA2,
  172. .udma_mask = ATA_UDMA2,
  173. },
  174. { /* 1: AEC6260 */
  175. .name = DRV_NAME,
  176. .init_chipset = init_chipset_aec62xx,
  177. .port_ops = &atp86x_port_ops,
  178. .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
  179. IDE_HFLAG_OFF_BOARD,
  180. .pio_mask = ATA_PIO4,
  181. .mwdma_mask = ATA_MWDMA2,
  182. .udma_mask = ATA_UDMA4,
  183. },
  184. { /* 2: AEC6260R */
  185. .name = DRV_NAME,
  186. .init_chipset = init_chipset_aec62xx,
  187. .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
  188. .port_ops = &atp86x_port_ops,
  189. .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
  190. IDE_HFLAG_NON_BOOTABLE,
  191. .pio_mask = ATA_PIO4,
  192. .mwdma_mask = ATA_MWDMA2,
  193. .udma_mask = ATA_UDMA4,
  194. },
  195. { /* 3: AEC6280 */
  196. .name = DRV_NAME,
  197. .init_chipset = init_chipset_aec62xx,
  198. .port_ops = &atp86x_port_ops,
  199. .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
  200. IDE_HFLAG_OFF_BOARD,
  201. .pio_mask = ATA_PIO4,
  202. .mwdma_mask = ATA_MWDMA2,
  203. .udma_mask = ATA_UDMA5,
  204. },
  205. { /* 4: AEC6280R */
  206. .name = DRV_NAME,
  207. .init_chipset = init_chipset_aec62xx,
  208. .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
  209. .port_ops = &atp86x_port_ops,
  210. .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
  211. IDE_HFLAG_OFF_BOARD,
  212. .pio_mask = ATA_PIO4,
  213. .mwdma_mask = ATA_MWDMA2,
  214. .udma_mask = ATA_UDMA5,
  215. }
  216. };
  217. /**
  218. * aec62xx_init_one - called when a AEC is found
  219. * @dev: the aec62xx device
  220. * @id: the matching pci id
  221. *
  222. * Called when the PCI registration layer (or the IDE initialization)
  223. * finds a device matching our IDE device tables.
  224. *
  225. * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
  226. * chips, pass a local copy of 'struct ide_port_info' down the call chain.
  227. */
  228. static int aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  229. {
  230. const struct chipset_bus_clock_list_entry *bus_clock;
  231. struct ide_port_info d;
  232. u8 idx = id->driver_data;
  233. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  234. int err;
  235. if (bus_speed <= 33)
  236. bus_clock = aec6xxx_33_base;
  237. else
  238. bus_clock = aec6xxx_34_base;
  239. err = pci_enable_device(dev);
  240. if (err)
  241. return err;
  242. d = aec62xx_chipsets[idx];
  243. if (idx == 3 || idx == 4) {
  244. unsigned long dma_base = pci_resource_start(dev, 4);
  245. if (inb(dma_base + 2) & 0x10) {
  246. printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
  247. "\n", pci_name(dev), (idx == 4) ? "R" : "");
  248. d.udma_mask = ATA_UDMA6;
  249. }
  250. }
  251. err = ide_pci_init_one(dev, &d, (void *)bus_clock);
  252. if (err)
  253. pci_disable_device(dev);
  254. return err;
  255. }
  256. static void aec62xx_remove(struct pci_dev *dev)
  257. {
  258. ide_pci_remove(dev);
  259. pci_disable_device(dev);
  260. }
  261. static const struct pci_device_id aec62xx_pci_tbl[] = {
  262. { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
  263. { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
  264. { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
  265. { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
  266. { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
  267. { 0, },
  268. };
  269. MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
  270. static struct pci_driver aec62xx_pci_driver = {
  271. .name = "AEC62xx_IDE",
  272. .id_table = aec62xx_pci_tbl,
  273. .probe = aec62xx_init_one,
  274. .remove = aec62xx_remove,
  275. .suspend = ide_pci_suspend,
  276. .resume = ide_pci_resume,
  277. };
  278. static int __init aec62xx_ide_init(void)
  279. {
  280. return ide_pci_register_driver(&aec62xx_pci_driver);
  281. }
  282. static void __exit aec62xx_ide_exit(void)
  283. {
  284. pci_unregister_driver(&aec62xx_pci_driver);
  285. }
  286. module_init(aec62xx_ide_init);
  287. module_exit(aec62xx_ide_exit);
  288. MODULE_AUTHOR("Andre Hedrick");
  289. MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
  290. MODULE_LICENSE("GPL");