dw-i3c-master.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Author: Vitor Soares <vitor.soares@synopsys.com>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/completion.h>
  10. #include <linux/err.h>
  11. #include <linux/errno.h>
  12. #include <linux/i3c/master.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ioport.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/list.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/reset.h>
  21. #include <linux/slab.h>
  22. #define DEVICE_CTRL 0x0
  23. #define DEV_CTRL_ENABLE BIT(31)
  24. #define DEV_CTRL_RESUME BIT(30)
  25. #define DEV_CTRL_HOT_JOIN_NACK BIT(8)
  26. #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7)
  27. #define DEVICE_ADDR 0x4
  28. #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31)
  29. #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16))
  30. #define HW_CAPABILITY 0x8
  31. #define COMMAND_QUEUE_PORT 0xc
  32. #define COMMAND_PORT_TOC BIT(30)
  33. #define COMMAND_PORT_READ_TRANSFER BIT(28)
  34. #define COMMAND_PORT_SDAP BIT(27)
  35. #define COMMAND_PORT_ROC BIT(26)
  36. #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21))
  37. #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16))
  38. #define COMMAND_PORT_CP BIT(15)
  39. #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7))
  40. #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3))
  41. #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16))
  42. #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536
  43. #define COMMAND_PORT_TRANSFER_ARG 0x01
  44. #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
  45. #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
  46. #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
  47. #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5)
  48. #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4)
  49. #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3)
  50. #define COMMAND_PORT_SHORT_DATA_ARG 0x02
  51. #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21))
  52. #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03
  53. #define RESPONSE_QUEUE_PORT 0x10
  54. #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28)
  55. #define RESPONSE_NO_ERROR 0
  56. #define RESPONSE_ERROR_CRC 1
  57. #define RESPONSE_ERROR_PARITY 2
  58. #define RESPONSE_ERROR_FRAME 3
  59. #define RESPONSE_ERROR_IBA_NACK 4
  60. #define RESPONSE_ERROR_ADDRESS_NACK 5
  61. #define RESPONSE_ERROR_OVER_UNDER_FLOW 6
  62. #define RESPONSE_ERROR_TRANSF_ABORT 8
  63. #define RESPONSE_ERROR_I2C_W_NACK_ERR 9
  64. #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24)
  65. #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0))
  66. #define RX_TX_DATA_PORT 0x14
  67. #define IBI_QUEUE_STATUS 0x18
  68. #define QUEUE_THLD_CTRL 0x1c
  69. #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
  70. #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
  71. #define DATA_BUFFER_THLD_CTRL 0x20
  72. #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8)
  73. #define IBI_QUEUE_CTRL 0x24
  74. #define IBI_MR_REQ_REJECT 0x2C
  75. #define IBI_SIR_REQ_REJECT 0x30
  76. #define IBI_REQ_REJECT_ALL GENMASK(31, 0)
  77. #define RESET_CTRL 0x34
  78. #define RESET_CTRL_IBI_QUEUE BIT(5)
  79. #define RESET_CTRL_RX_FIFO BIT(4)
  80. #define RESET_CTRL_TX_FIFO BIT(3)
  81. #define RESET_CTRL_RESP_QUEUE BIT(2)
  82. #define RESET_CTRL_CMD_QUEUE BIT(1)
  83. #define RESET_CTRL_SOFT BIT(0)
  84. #define SLV_EVENT_CTRL 0x38
  85. #define INTR_STATUS 0x3c
  86. #define INTR_STATUS_EN 0x40
  87. #define INTR_SIGNAL_EN 0x44
  88. #define INTR_FORCE 0x48
  89. #define INTR_BUSOWNER_UPDATE_STAT BIT(13)
  90. #define INTR_IBI_UPDATED_STAT BIT(12)
  91. #define INTR_READ_REQ_RECV_STAT BIT(11)
  92. #define INTR_DEFSLV_STAT BIT(10)
  93. #define INTR_TRANSFER_ERR_STAT BIT(9)
  94. #define INTR_DYN_ADDR_ASSGN_STAT BIT(8)
  95. #define INTR_CCC_UPDATED_STAT BIT(6)
  96. #define INTR_TRANSFER_ABORT_STAT BIT(5)
  97. #define INTR_RESP_READY_STAT BIT(4)
  98. #define INTR_CMD_QUEUE_READY_STAT BIT(3)
  99. #define INTR_IBI_THLD_STAT BIT(2)
  100. #define INTR_RX_THLD_STAT BIT(1)
  101. #define INTR_TX_THLD_STAT BIT(0)
  102. #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \
  103. INTR_IBI_UPDATED_STAT | \
  104. INTR_READ_REQ_RECV_STAT | \
  105. INTR_DEFSLV_STAT | \
  106. INTR_TRANSFER_ERR_STAT | \
  107. INTR_DYN_ADDR_ASSGN_STAT | \
  108. INTR_CCC_UPDATED_STAT | \
  109. INTR_TRANSFER_ABORT_STAT | \
  110. INTR_RESP_READY_STAT | \
  111. INTR_CMD_QUEUE_READY_STAT | \
  112. INTR_IBI_THLD_STAT | \
  113. INTR_TX_THLD_STAT | \
  114. INTR_RX_THLD_STAT)
  115. #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \
  116. INTR_RESP_READY_STAT)
  117. #define QUEUE_STATUS_LEVEL 0x4c
  118. #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24)
  119. #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16)
  120. #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8)
  121. #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0))
  122. #define DATA_BUFFER_STATUS_LEVEL 0x50
  123. #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0))
  124. #define PRESENT_STATE 0x54
  125. #define CCC_DEVICE_STATUS 0x58
  126. #define DEVICE_ADDR_TABLE_POINTER 0x5c
  127. #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16)
  128. #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0))
  129. #define DEV_CHAR_TABLE_POINTER 0x60
  130. #define VENDOR_SPECIFIC_REG_POINTER 0x6c
  131. #define SLV_PID_VALUE 0x74
  132. #define SLV_CHAR_CTRL 0x78
  133. #define SLV_MAX_LEN 0x7c
  134. #define MAX_READ_TURNAROUND 0x80
  135. #define MAX_DATA_SPEED 0x84
  136. #define SLV_DEBUG_STATUS 0x88
  137. #define SLV_INTR_REQ 0x8c
  138. #define DEVICE_CTRL_EXTENDED 0xb0
  139. #define SCL_I3C_OD_TIMING 0xb4
  140. #define SCL_I3C_PP_TIMING 0xb8
  141. #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
  142. #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0))
  143. #define SCL_I3C_TIMING_CNT_MIN 5
  144. #define SCL_I2C_FM_TIMING 0xbc
  145. #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16))
  146. #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
  147. #define SCL_I2C_FMP_TIMING 0xc0
  148. #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
  149. #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
  150. #define SCL_EXT_LCNT_TIMING 0xc8
  151. #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24))
  152. #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16))
  153. #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8))
  154. #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0))
  155. #define SCL_EXT_TERMN_LCNT_TIMING 0xcc
  156. #define BUS_FREE_TIMING 0xd4
  157. #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0))
  158. #define BUS_IDLE_TIMING 0xd8
  159. #define I3C_VER_ID 0xe0
  160. #define I3C_VER_TYPE 0xe4
  161. #define EXTENDED_CAPABILITY 0xe8
  162. #define SLAVE_CONFIG 0xec
  163. #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
  164. #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16))
  165. #define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0))
  166. #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2))
  167. #define MAX_DEVS 32
  168. #define I3C_BUS_SDR1_SCL_RATE 8000000
  169. #define I3C_BUS_SDR2_SCL_RATE 6000000
  170. #define I3C_BUS_SDR3_SCL_RATE 4000000
  171. #define I3C_BUS_SDR4_SCL_RATE 2000000
  172. #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300
  173. #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500
  174. #define I3C_BUS_THIGH_MAX_NS 41
  175. #define XFER_TIMEOUT (msecs_to_jiffies(1000))
  176. struct dw_i3c_master_caps {
  177. u8 cmdfifodepth;
  178. u8 datafifodepth;
  179. };
  180. struct dw_i3c_cmd {
  181. u32 cmd_lo;
  182. u32 cmd_hi;
  183. u16 tx_len;
  184. const void *tx_buf;
  185. u16 rx_len;
  186. void *rx_buf;
  187. u8 error;
  188. };
  189. struct dw_i3c_xfer {
  190. struct list_head node;
  191. struct completion comp;
  192. int ret;
  193. unsigned int ncmds;
  194. struct dw_i3c_cmd cmds[];
  195. };
  196. struct dw_i3c_master {
  197. struct i3c_master_controller base;
  198. u16 maxdevs;
  199. u16 datstartaddr;
  200. u32 free_pos;
  201. struct {
  202. struct list_head list;
  203. struct dw_i3c_xfer *cur;
  204. spinlock_t lock;
  205. } xferqueue;
  206. struct dw_i3c_master_caps caps;
  207. void __iomem *regs;
  208. struct reset_control *core_rst;
  209. struct clk *core_clk;
  210. char version[5];
  211. char type[5];
  212. u8 addrs[MAX_DEVS];
  213. };
  214. struct dw_i3c_i2c_dev_data {
  215. u8 index;
  216. };
  217. static u8 even_parity(u8 p)
  218. {
  219. p ^= p >> 4;
  220. p &= 0xf;
  221. return (0x9669 >> p) & 1;
  222. }
  223. static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
  224. const struct i3c_ccc_cmd *cmd)
  225. {
  226. if (cmd->ndests > 1)
  227. return false;
  228. switch (cmd->id) {
  229. case I3C_CCC_ENEC(true):
  230. case I3C_CCC_ENEC(false):
  231. case I3C_CCC_DISEC(true):
  232. case I3C_CCC_DISEC(false):
  233. case I3C_CCC_ENTAS(0, true):
  234. case I3C_CCC_ENTAS(0, false):
  235. case I3C_CCC_RSTDAA(true):
  236. case I3C_CCC_RSTDAA(false):
  237. case I3C_CCC_ENTDAA:
  238. case I3C_CCC_SETMWL(true):
  239. case I3C_CCC_SETMWL(false):
  240. case I3C_CCC_SETMRL(true):
  241. case I3C_CCC_SETMRL(false):
  242. case I3C_CCC_ENTHDR(0):
  243. case I3C_CCC_SETDASA:
  244. case I3C_CCC_SETNEWDA:
  245. case I3C_CCC_GETMWL:
  246. case I3C_CCC_GETMRL:
  247. case I3C_CCC_GETPID:
  248. case I3C_CCC_GETBCR:
  249. case I3C_CCC_GETDCR:
  250. case I3C_CCC_GETSTATUS:
  251. case I3C_CCC_GETMXDS:
  252. case I3C_CCC_GETHDRCAP:
  253. return true;
  254. default:
  255. return false;
  256. }
  257. }
  258. static inline struct dw_i3c_master *
  259. to_dw_i3c_master(struct i3c_master_controller *master)
  260. {
  261. return container_of(master, struct dw_i3c_master, base);
  262. }
  263. static void dw_i3c_master_disable(struct dw_i3c_master *master)
  264. {
  265. writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
  266. master->regs + DEVICE_CTRL);
  267. }
  268. static void dw_i3c_master_enable(struct dw_i3c_master *master)
  269. {
  270. writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
  271. master->regs + DEVICE_CTRL);
  272. }
  273. static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
  274. {
  275. int pos;
  276. for (pos = 0; pos < master->maxdevs; pos++) {
  277. if (addr == master->addrs[pos])
  278. return pos;
  279. }
  280. return -EINVAL;
  281. }
  282. static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
  283. {
  284. if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
  285. return -ENOSPC;
  286. return ffs(master->free_pos) - 1;
  287. }
  288. static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
  289. const u8 *bytes, int nbytes)
  290. {
  291. writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
  292. if (nbytes & 3) {
  293. u32 tmp = 0;
  294. memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
  295. writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
  296. }
  297. }
  298. static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
  299. u8 *bytes, int nbytes)
  300. {
  301. readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
  302. if (nbytes & 3) {
  303. u32 tmp;
  304. readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
  305. memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
  306. }
  307. }
  308. static struct dw_i3c_xfer *
  309. dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
  310. {
  311. struct dw_i3c_xfer *xfer;
  312. xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
  313. if (!xfer)
  314. return NULL;
  315. INIT_LIST_HEAD(&xfer->node);
  316. xfer->ncmds = ncmds;
  317. xfer->ret = -ETIMEDOUT;
  318. return xfer;
  319. }
  320. static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer)
  321. {
  322. kfree(xfer);
  323. }
  324. static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
  325. {
  326. struct dw_i3c_xfer *xfer = master->xferqueue.cur;
  327. unsigned int i;
  328. u32 thld_ctrl;
  329. if (!xfer)
  330. return;
  331. for (i = 0; i < xfer->ncmds; i++) {
  332. struct dw_i3c_cmd *cmd = &xfer->cmds[i];
  333. dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
  334. }
  335. thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
  336. thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
  337. thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
  338. writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
  339. for (i = 0; i < xfer->ncmds; i++) {
  340. struct dw_i3c_cmd *cmd = &xfer->cmds[i];
  341. writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
  342. writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
  343. }
  344. }
  345. static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
  346. struct dw_i3c_xfer *xfer)
  347. {
  348. unsigned long flags;
  349. init_completion(&xfer->comp);
  350. spin_lock_irqsave(&master->xferqueue.lock, flags);
  351. if (master->xferqueue.cur) {
  352. list_add_tail(&xfer->node, &master->xferqueue.list);
  353. } else {
  354. master->xferqueue.cur = xfer;
  355. dw_i3c_master_start_xfer_locked(master);
  356. }
  357. spin_unlock_irqrestore(&master->xferqueue.lock, flags);
  358. }
  359. static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
  360. struct dw_i3c_xfer *xfer)
  361. {
  362. if (master->xferqueue.cur == xfer) {
  363. u32 status;
  364. master->xferqueue.cur = NULL;
  365. writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
  366. RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE,
  367. master->regs + RESET_CTRL);
  368. readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
  369. !status, 10, 1000000);
  370. } else {
  371. list_del_init(&xfer->node);
  372. }
  373. }
  374. static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
  375. struct dw_i3c_xfer *xfer)
  376. {
  377. unsigned long flags;
  378. spin_lock_irqsave(&master->xferqueue.lock, flags);
  379. dw_i3c_master_dequeue_xfer_locked(master, xfer);
  380. spin_unlock_irqrestore(&master->xferqueue.lock, flags);
  381. }
  382. static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
  383. {
  384. struct dw_i3c_xfer *xfer = master->xferqueue.cur;
  385. int i, ret = 0;
  386. u32 nresp;
  387. if (!xfer)
  388. return;
  389. nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
  390. nresp = QUEUE_STATUS_LEVEL_RESP(nresp);
  391. for (i = 0; i < nresp; i++) {
  392. struct dw_i3c_cmd *cmd;
  393. u32 resp;
  394. resp = readl(master->regs + RESPONSE_QUEUE_PORT);
  395. cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)];
  396. cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
  397. cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
  398. if (cmd->rx_len && !cmd->error)
  399. dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
  400. cmd->rx_len);
  401. }
  402. for (i = 0; i < nresp; i++) {
  403. switch (xfer->cmds[i].error) {
  404. case RESPONSE_NO_ERROR:
  405. break;
  406. case RESPONSE_ERROR_PARITY:
  407. case RESPONSE_ERROR_IBA_NACK:
  408. case RESPONSE_ERROR_TRANSF_ABORT:
  409. case RESPONSE_ERROR_CRC:
  410. case RESPONSE_ERROR_FRAME:
  411. ret = -EIO;
  412. break;
  413. case RESPONSE_ERROR_OVER_UNDER_FLOW:
  414. ret = -ENOSPC;
  415. break;
  416. case RESPONSE_ERROR_I2C_W_NACK_ERR:
  417. case RESPONSE_ERROR_ADDRESS_NACK:
  418. default:
  419. ret = -EINVAL;
  420. break;
  421. }
  422. }
  423. xfer->ret = ret;
  424. complete(&xfer->comp);
  425. if (ret < 0) {
  426. dw_i3c_master_dequeue_xfer_locked(master, xfer);
  427. writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
  428. master->regs + DEVICE_CTRL);
  429. }
  430. xfer = list_first_entry_or_null(&master->xferqueue.list,
  431. struct dw_i3c_xfer,
  432. node);
  433. if (xfer)
  434. list_del_init(&xfer->node);
  435. master->xferqueue.cur = xfer;
  436. dw_i3c_master_start_xfer_locked(master);
  437. }
  438. static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
  439. {
  440. unsigned long core_rate, core_period;
  441. u32 scl_timing;
  442. u8 hcnt, lcnt;
  443. core_rate = clk_get_rate(master->core_clk);
  444. if (!core_rate)
  445. return -EINVAL;
  446. core_period = DIV_ROUND_UP(1000000000, core_rate);
  447. hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1;
  448. if (hcnt < SCL_I3C_TIMING_CNT_MIN)
  449. hcnt = SCL_I3C_TIMING_CNT_MIN;
  450. lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt;
  451. if (lcnt < SCL_I3C_TIMING_CNT_MIN)
  452. lcnt = SCL_I3C_TIMING_CNT_MIN;
  453. scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
  454. writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
  455. if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
  456. writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
  457. lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period);
  458. scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
  459. writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
  460. lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
  461. scl_timing = SCL_EXT_LCNT_1(lcnt);
  462. lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
  463. scl_timing |= SCL_EXT_LCNT_2(lcnt);
  464. lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
  465. scl_timing |= SCL_EXT_LCNT_3(lcnt);
  466. lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
  467. scl_timing |= SCL_EXT_LCNT_4(lcnt);
  468. writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
  469. return 0;
  470. }
  471. static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
  472. {
  473. unsigned long core_rate, core_period;
  474. u16 hcnt, lcnt;
  475. u32 scl_timing;
  476. core_rate = clk_get_rate(master->core_clk);
  477. if (!core_rate)
  478. return -EINVAL;
  479. core_period = DIV_ROUND_UP(1000000000, core_rate);
  480. lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period);
  481. hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt;
  482. scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
  483. SCL_I2C_FMP_TIMING_LCNT(lcnt);
  484. writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
  485. lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
  486. hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt;
  487. scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
  488. SCL_I2C_FM_TIMING_LCNT(lcnt);
  489. writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
  490. writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
  491. writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
  492. master->regs + DEVICE_CTRL);
  493. return 0;
  494. }
  495. static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
  496. {
  497. struct dw_i3c_master *master = to_dw_i3c_master(m);
  498. struct i3c_bus *bus = i3c_master_get_bus(m);
  499. struct i3c_device_info info = { };
  500. u32 thld_ctrl;
  501. int ret;
  502. switch (bus->mode) {
  503. case I3C_BUS_MODE_MIXED_FAST:
  504. case I3C_BUS_MODE_MIXED_LIMITED:
  505. ret = dw_i2c_clk_cfg(master);
  506. if (ret)
  507. return ret;
  508. fallthrough;
  509. case I3C_BUS_MODE_PURE:
  510. ret = dw_i3c_clk_cfg(master);
  511. if (ret)
  512. return ret;
  513. break;
  514. default:
  515. return -EINVAL;
  516. }
  517. thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
  518. thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
  519. writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
  520. thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
  521. thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
  522. writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
  523. writel(INTR_ALL, master->regs + INTR_STATUS);
  524. writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
  525. writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
  526. ret = i3c_master_get_free_addr(m, 0);
  527. if (ret < 0)
  528. return ret;
  529. writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
  530. master->regs + DEVICE_ADDR);
  531. memset(&info, 0, sizeof(info));
  532. info.dyn_addr = ret;
  533. ret = i3c_master_set_info(&master->base, &info);
  534. if (ret)
  535. return ret;
  536. writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
  537. writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
  538. /* For now don't support Hot-Join */
  539. writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
  540. master->regs + DEVICE_CTRL);
  541. dw_i3c_master_enable(master);
  542. return 0;
  543. }
  544. static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
  545. {
  546. struct dw_i3c_master *master = to_dw_i3c_master(m);
  547. dw_i3c_master_disable(master);
  548. }
  549. static int dw_i3c_ccc_set(struct dw_i3c_master *master,
  550. struct i3c_ccc_cmd *ccc)
  551. {
  552. struct dw_i3c_xfer *xfer;
  553. struct dw_i3c_cmd *cmd;
  554. int ret, pos = 0;
  555. if (ccc->id & I3C_CCC_DIRECT) {
  556. pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
  557. if (pos < 0)
  558. return pos;
  559. }
  560. xfer = dw_i3c_master_alloc_xfer(master, 1);
  561. if (!xfer)
  562. return -ENOMEM;
  563. cmd = xfer->cmds;
  564. cmd->tx_buf = ccc->dests[0].payload.data;
  565. cmd->tx_len = ccc->dests[0].payload.len;
  566. cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
  567. COMMAND_PORT_TRANSFER_ARG;
  568. cmd->cmd_lo = COMMAND_PORT_CP |
  569. COMMAND_PORT_DEV_INDEX(pos) |
  570. COMMAND_PORT_CMD(ccc->id) |
  571. COMMAND_PORT_TOC |
  572. COMMAND_PORT_ROC;
  573. dw_i3c_master_enqueue_xfer(master, xfer);
  574. if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
  575. dw_i3c_master_dequeue_xfer(master, xfer);
  576. ret = xfer->ret;
  577. if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
  578. ccc->err = I3C_ERROR_M2;
  579. dw_i3c_master_free_xfer(xfer);
  580. return ret;
  581. }
  582. static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
  583. {
  584. struct dw_i3c_xfer *xfer;
  585. struct dw_i3c_cmd *cmd;
  586. int ret, pos;
  587. pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
  588. if (pos < 0)
  589. return pos;
  590. xfer = dw_i3c_master_alloc_xfer(master, 1);
  591. if (!xfer)
  592. return -ENOMEM;
  593. cmd = xfer->cmds;
  594. cmd->rx_buf = ccc->dests[0].payload.data;
  595. cmd->rx_len = ccc->dests[0].payload.len;
  596. cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
  597. COMMAND_PORT_TRANSFER_ARG;
  598. cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
  599. COMMAND_PORT_CP |
  600. COMMAND_PORT_DEV_INDEX(pos) |
  601. COMMAND_PORT_CMD(ccc->id) |
  602. COMMAND_PORT_TOC |
  603. COMMAND_PORT_ROC;
  604. dw_i3c_master_enqueue_xfer(master, xfer);
  605. if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
  606. dw_i3c_master_dequeue_xfer(master, xfer);
  607. ret = xfer->ret;
  608. if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
  609. ccc->err = I3C_ERROR_M2;
  610. dw_i3c_master_free_xfer(xfer);
  611. return ret;
  612. }
  613. static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
  614. struct i3c_ccc_cmd *ccc)
  615. {
  616. struct dw_i3c_master *master = to_dw_i3c_master(m);
  617. int ret = 0;
  618. if (ccc->id == I3C_CCC_ENTDAA)
  619. return -EINVAL;
  620. if (ccc->rnw)
  621. ret = dw_i3c_ccc_get(master, ccc);
  622. else
  623. ret = dw_i3c_ccc_set(master, ccc);
  624. return ret;
  625. }
  626. static int dw_i3c_master_daa(struct i3c_master_controller *m)
  627. {
  628. struct dw_i3c_master *master = to_dw_i3c_master(m);
  629. struct dw_i3c_xfer *xfer;
  630. struct dw_i3c_cmd *cmd;
  631. u32 olddevs, newdevs;
  632. u8 p, last_addr = 0;
  633. int ret, pos;
  634. olddevs = ~(master->free_pos);
  635. /* Prepare DAT before launching DAA. */
  636. for (pos = 0; pos < master->maxdevs; pos++) {
  637. if (olddevs & BIT(pos))
  638. continue;
  639. ret = i3c_master_get_free_addr(m, last_addr + 1);
  640. if (ret < 0)
  641. return -ENOSPC;
  642. master->addrs[pos] = ret;
  643. p = even_parity(ret);
  644. last_addr = ret;
  645. ret |= (p << 7);
  646. writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
  647. master->regs +
  648. DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
  649. }
  650. xfer = dw_i3c_master_alloc_xfer(master, 1);
  651. if (!xfer)
  652. return -ENOMEM;
  653. pos = dw_i3c_master_get_free_pos(master);
  654. cmd = &xfer->cmds[0];
  655. cmd->cmd_hi = 0x1;
  656. cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
  657. COMMAND_PORT_DEV_INDEX(pos) |
  658. COMMAND_PORT_CMD(I3C_CCC_ENTDAA) |
  659. COMMAND_PORT_ADDR_ASSGN_CMD |
  660. COMMAND_PORT_TOC |
  661. COMMAND_PORT_ROC;
  662. dw_i3c_master_enqueue_xfer(master, xfer);
  663. if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
  664. dw_i3c_master_dequeue_xfer(master, xfer);
  665. newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
  666. newdevs &= ~olddevs;
  667. for (pos = 0; pos < master->maxdevs; pos++) {
  668. if (newdevs & BIT(pos))
  669. i3c_master_add_i3c_dev_locked(m, master->addrs[pos]);
  670. }
  671. dw_i3c_master_free_xfer(xfer);
  672. i3c_master_disec_locked(m, I3C_BROADCAST_ADDR,
  673. I3C_CCC_EVENT_HJ |
  674. I3C_CCC_EVENT_MR |
  675. I3C_CCC_EVENT_SIR);
  676. return 0;
  677. }
  678. static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
  679. struct i3c_priv_xfer *i3c_xfers,
  680. int i3c_nxfers)
  681. {
  682. struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
  683. struct i3c_master_controller *m = i3c_dev_get_master(dev);
  684. struct dw_i3c_master *master = to_dw_i3c_master(m);
  685. unsigned int nrxwords = 0, ntxwords = 0;
  686. struct dw_i3c_xfer *xfer;
  687. int i, ret = 0;
  688. if (!i3c_nxfers)
  689. return 0;
  690. if (i3c_nxfers > master->caps.cmdfifodepth)
  691. return -ENOTSUPP;
  692. for (i = 0; i < i3c_nxfers; i++) {
  693. if (i3c_xfers[i].rnw)
  694. nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
  695. else
  696. ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
  697. }
  698. if (ntxwords > master->caps.datafifodepth ||
  699. nrxwords > master->caps.datafifodepth)
  700. return -ENOTSUPP;
  701. xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
  702. if (!xfer)
  703. return -ENOMEM;
  704. for (i = 0; i < i3c_nxfers; i++) {
  705. struct dw_i3c_cmd *cmd = &xfer->cmds[i];
  706. cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) |
  707. COMMAND_PORT_TRANSFER_ARG;
  708. if (i3c_xfers[i].rnw) {
  709. cmd->rx_buf = i3c_xfers[i].data.in;
  710. cmd->rx_len = i3c_xfers[i].len;
  711. cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
  712. COMMAND_PORT_SPEED(dev->info.max_read_ds);
  713. } else {
  714. cmd->tx_buf = i3c_xfers[i].data.out;
  715. cmd->tx_len = i3c_xfers[i].len;
  716. cmd->cmd_lo =
  717. COMMAND_PORT_SPEED(dev->info.max_write_ds);
  718. }
  719. cmd->cmd_lo |= COMMAND_PORT_TID(i) |
  720. COMMAND_PORT_DEV_INDEX(data->index) |
  721. COMMAND_PORT_ROC;
  722. if (i == (i3c_nxfers - 1))
  723. cmd->cmd_lo |= COMMAND_PORT_TOC;
  724. }
  725. dw_i3c_master_enqueue_xfer(master, xfer);
  726. if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
  727. dw_i3c_master_dequeue_xfer(master, xfer);
  728. ret = xfer->ret;
  729. dw_i3c_master_free_xfer(xfer);
  730. return ret;
  731. }
  732. static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
  733. u8 old_dyn_addr)
  734. {
  735. struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
  736. struct i3c_master_controller *m = i3c_dev_get_master(dev);
  737. struct dw_i3c_master *master = to_dw_i3c_master(m);
  738. int pos;
  739. pos = dw_i3c_master_get_free_pos(master);
  740. if (data->index > pos && pos > 0) {
  741. writel(0,
  742. master->regs +
  743. DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
  744. master->addrs[data->index] = 0;
  745. master->free_pos |= BIT(data->index);
  746. data->index = pos;
  747. master->addrs[pos] = dev->info.dyn_addr;
  748. master->free_pos &= ~BIT(pos);
  749. }
  750. writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr),
  751. master->regs +
  752. DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
  753. master->addrs[data->index] = dev->info.dyn_addr;
  754. return 0;
  755. }
  756. static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
  757. {
  758. struct i3c_master_controller *m = i3c_dev_get_master(dev);
  759. struct dw_i3c_master *master = to_dw_i3c_master(m);
  760. struct dw_i3c_i2c_dev_data *data;
  761. int pos;
  762. pos = dw_i3c_master_get_free_pos(master);
  763. if (pos < 0)
  764. return pos;
  765. data = kzalloc(sizeof(*data), GFP_KERNEL);
  766. if (!data)
  767. return -ENOMEM;
  768. data->index = pos;
  769. master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
  770. master->free_pos &= ~BIT(pos);
  771. i3c_dev_set_master_data(dev, data);
  772. writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]),
  773. master->regs +
  774. DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
  775. return 0;
  776. }
  777. static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
  778. {
  779. struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
  780. struct i3c_master_controller *m = i3c_dev_get_master(dev);
  781. struct dw_i3c_master *master = to_dw_i3c_master(m);
  782. writel(0,
  783. master->regs +
  784. DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
  785. i3c_dev_set_master_data(dev, NULL);
  786. master->addrs[data->index] = 0;
  787. master->free_pos |= BIT(data->index);
  788. kfree(data);
  789. }
  790. static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
  791. const struct i2c_msg *i2c_xfers,
  792. int i2c_nxfers)
  793. {
  794. struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
  795. struct i3c_master_controller *m = i2c_dev_get_master(dev);
  796. struct dw_i3c_master *master = to_dw_i3c_master(m);
  797. unsigned int nrxwords = 0, ntxwords = 0;
  798. struct dw_i3c_xfer *xfer;
  799. int i, ret = 0;
  800. if (!i2c_nxfers)
  801. return 0;
  802. if (i2c_nxfers > master->caps.cmdfifodepth)
  803. return -ENOTSUPP;
  804. for (i = 0; i < i2c_nxfers; i++) {
  805. if (i2c_xfers[i].flags & I2C_M_RD)
  806. nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
  807. else
  808. ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
  809. }
  810. if (ntxwords > master->caps.datafifodepth ||
  811. nrxwords > master->caps.datafifodepth)
  812. return -ENOTSUPP;
  813. xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
  814. if (!xfer)
  815. return -ENOMEM;
  816. for (i = 0; i < i2c_nxfers; i++) {
  817. struct dw_i3c_cmd *cmd = &xfer->cmds[i];
  818. cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) |
  819. COMMAND_PORT_TRANSFER_ARG;
  820. cmd->cmd_lo = COMMAND_PORT_TID(i) |
  821. COMMAND_PORT_DEV_INDEX(data->index) |
  822. COMMAND_PORT_ROC;
  823. if (i2c_xfers[i].flags & I2C_M_RD) {
  824. cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
  825. cmd->rx_buf = i2c_xfers[i].buf;
  826. cmd->rx_len = i2c_xfers[i].len;
  827. } else {
  828. cmd->tx_buf = i2c_xfers[i].buf;
  829. cmd->tx_len = i2c_xfers[i].len;
  830. }
  831. if (i == (i2c_nxfers - 1))
  832. cmd->cmd_lo |= COMMAND_PORT_TOC;
  833. }
  834. dw_i3c_master_enqueue_xfer(master, xfer);
  835. if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
  836. dw_i3c_master_dequeue_xfer(master, xfer);
  837. ret = xfer->ret;
  838. dw_i3c_master_free_xfer(xfer);
  839. return ret;
  840. }
  841. static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
  842. {
  843. struct i3c_master_controller *m = i2c_dev_get_master(dev);
  844. struct dw_i3c_master *master = to_dw_i3c_master(m);
  845. struct dw_i3c_i2c_dev_data *data;
  846. int pos;
  847. pos = dw_i3c_master_get_free_pos(master);
  848. if (pos < 0)
  849. return pos;
  850. data = kzalloc(sizeof(*data), GFP_KERNEL);
  851. if (!data)
  852. return -ENOMEM;
  853. data->index = pos;
  854. master->addrs[pos] = dev->addr;
  855. master->free_pos &= ~BIT(pos);
  856. i2c_dev_set_master_data(dev, data);
  857. writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
  858. DEV_ADDR_TABLE_STATIC_ADDR(dev->addr),
  859. master->regs +
  860. DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
  861. return 0;
  862. }
  863. static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
  864. {
  865. struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
  866. struct i3c_master_controller *m = i2c_dev_get_master(dev);
  867. struct dw_i3c_master *master = to_dw_i3c_master(m);
  868. writel(0,
  869. master->regs +
  870. DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
  871. i2c_dev_set_master_data(dev, NULL);
  872. master->addrs[data->index] = 0;
  873. master->free_pos |= BIT(data->index);
  874. kfree(data);
  875. }
  876. static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
  877. {
  878. struct dw_i3c_master *master = dev_id;
  879. u32 status;
  880. status = readl(master->regs + INTR_STATUS);
  881. if (!(status & readl(master->regs + INTR_STATUS_EN))) {
  882. writel(INTR_ALL, master->regs + INTR_STATUS);
  883. return IRQ_NONE;
  884. }
  885. spin_lock(&master->xferqueue.lock);
  886. dw_i3c_master_end_xfer_locked(master, status);
  887. if (status & INTR_TRANSFER_ERR_STAT)
  888. writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
  889. spin_unlock(&master->xferqueue.lock);
  890. return IRQ_HANDLED;
  891. }
  892. static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
  893. .bus_init = dw_i3c_master_bus_init,
  894. .bus_cleanup = dw_i3c_master_bus_cleanup,
  895. .attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
  896. .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
  897. .detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
  898. .do_daa = dw_i3c_master_daa,
  899. .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
  900. .send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
  901. .priv_xfers = dw_i3c_master_priv_xfers,
  902. .attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
  903. .detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
  904. .i2c_xfers = dw_i3c_master_i2c_xfers,
  905. };
  906. static int dw_i3c_probe(struct platform_device *pdev)
  907. {
  908. struct dw_i3c_master *master;
  909. int ret, irq;
  910. master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
  911. if (!master)
  912. return -ENOMEM;
  913. master->regs = devm_platform_ioremap_resource(pdev, 0);
  914. if (IS_ERR(master->regs))
  915. return PTR_ERR(master->regs);
  916. master->core_clk = devm_clk_get(&pdev->dev, NULL);
  917. if (IS_ERR(master->core_clk))
  918. return PTR_ERR(master->core_clk);
  919. master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
  920. "core_rst");
  921. if (IS_ERR(master->core_rst))
  922. return PTR_ERR(master->core_rst);
  923. ret = clk_prepare_enable(master->core_clk);
  924. if (ret)
  925. goto err_disable_core_clk;
  926. reset_control_deassert(master->core_rst);
  927. spin_lock_init(&master->xferqueue.lock);
  928. INIT_LIST_HEAD(&master->xferqueue.list);
  929. writel(INTR_ALL, master->regs + INTR_STATUS);
  930. irq = platform_get_irq(pdev, 0);
  931. ret = devm_request_irq(&pdev->dev, irq,
  932. dw_i3c_master_irq_handler, 0,
  933. dev_name(&pdev->dev), master);
  934. if (ret)
  935. goto err_assert_rst;
  936. platform_set_drvdata(pdev, master);
  937. /* Information regarding the FIFOs/QUEUEs depth */
  938. ret = readl(master->regs + QUEUE_STATUS_LEVEL);
  939. master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
  940. ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
  941. master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
  942. ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
  943. master->datstartaddr = ret;
  944. master->maxdevs = ret >> 16;
  945. master->free_pos = GENMASK(master->maxdevs - 1, 0);
  946. ret = i3c_master_register(&master->base, &pdev->dev,
  947. &dw_mipi_i3c_ops, false);
  948. if (ret)
  949. goto err_assert_rst;
  950. return 0;
  951. err_assert_rst:
  952. reset_control_assert(master->core_rst);
  953. err_disable_core_clk:
  954. clk_disable_unprepare(master->core_clk);
  955. return ret;
  956. }
  957. static int dw_i3c_remove(struct platform_device *pdev)
  958. {
  959. struct dw_i3c_master *master = platform_get_drvdata(pdev);
  960. int ret;
  961. ret = i3c_master_unregister(&master->base);
  962. if (ret)
  963. return ret;
  964. reset_control_assert(master->core_rst);
  965. clk_disable_unprepare(master->core_clk);
  966. return 0;
  967. }
  968. static const struct of_device_id dw_i3c_master_of_match[] = {
  969. { .compatible = "snps,dw-i3c-master-1.00a", },
  970. {},
  971. };
  972. MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
  973. static struct platform_driver dw_i3c_driver = {
  974. .probe = dw_i3c_probe,
  975. .remove = dw_i3c_remove,
  976. .driver = {
  977. .name = "dw-i3c-master",
  978. .of_match_table = of_match_ptr(dw_i3c_master_of_match),
  979. },
  980. };
  981. module_platform_driver(dw_i3c_driver);
  982. MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
  983. MODULE_DESCRIPTION("DesignWare MIPI I3C driver");
  984. MODULE_LICENSE("GPL v2");