master.c 67 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Cadence Design Systems Inc.
  4. *
  5. * Author: Boris Brezillon <boris.brezillon@bootlin.com>
  6. */
  7. #include <linux/atomic.h>
  8. #include <linux/bug.h>
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/export.h>
  12. #include <linux/kernel.h>
  13. #include <linux/list.h>
  14. #include <linux/of.h>
  15. #include <linux/slab.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/workqueue.h>
  18. #include "internals.h"
  19. static DEFINE_IDR(i3c_bus_idr);
  20. static DEFINE_MUTEX(i3c_core_lock);
  21. /**
  22. * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
  23. * @bus: I3C bus to take the lock on
  24. *
  25. * This function takes the bus lock so that no other operations can occur on
  26. * the bus. This is needed for all kind of bus maintenance operation, like
  27. * - enabling/disabling slave events
  28. * - re-triggering DAA
  29. * - changing the dynamic address of a device
  30. * - relinquishing mastership
  31. * - ...
  32. *
  33. * The reason for this kind of locking is that we don't want drivers and core
  34. * logic to rely on I3C device information that could be changed behind their
  35. * back.
  36. */
  37. static void i3c_bus_maintenance_lock(struct i3c_bus *bus)
  38. {
  39. down_write(&bus->lock);
  40. }
  41. /**
  42. * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance
  43. * operation
  44. * @bus: I3C bus to release the lock on
  45. *
  46. * Should be called when the bus maintenance operation is done. See
  47. * i3c_bus_maintenance_lock() for more details on what these maintenance
  48. * operations are.
  49. */
  50. static void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
  51. {
  52. up_write(&bus->lock);
  53. }
  54. /**
  55. * i3c_bus_normaluse_lock - Lock the bus for a normal operation
  56. * @bus: I3C bus to take the lock on
  57. *
  58. * This function takes the bus lock for any operation that is not a maintenance
  59. * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of
  60. * maintenance operations). Basically all communications with I3C devices are
  61. * normal operations (HDR, SDR transfers or CCC commands that do not change bus
  62. * state or I3C dynamic address).
  63. *
  64. * Note that this lock is not guaranteeing serialization of normal operations.
  65. * In other words, transfer requests passed to the I3C master can be submitted
  66. * in parallel and I3C master drivers have to use their own locking to make
  67. * sure two different communications are not inter-mixed, or access to the
  68. * output/input queue is not done while the engine is busy.
  69. */
  70. void i3c_bus_normaluse_lock(struct i3c_bus *bus)
  71. {
  72. down_read(&bus->lock);
  73. }
  74. /**
  75. * i3c_bus_normaluse_unlock - Release the bus lock after a normal operation
  76. * @bus: I3C bus to release the lock on
  77. *
  78. * Should be called when a normal operation is done. See
  79. * i3c_bus_normaluse_lock() for more details on what these normal operations
  80. * are.
  81. */
  82. void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
  83. {
  84. up_read(&bus->lock);
  85. }
  86. static struct i3c_master_controller *
  87. i3c_bus_to_i3c_master(struct i3c_bus *i3cbus)
  88. {
  89. return container_of(i3cbus, struct i3c_master_controller, bus);
  90. }
  91. static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev)
  92. {
  93. return container_of(dev, struct i3c_master_controller, dev);
  94. }
  95. static const struct device_type i3c_device_type;
  96. static struct i3c_bus *dev_to_i3cbus(struct device *dev)
  97. {
  98. struct i3c_master_controller *master;
  99. if (dev->type == &i3c_device_type)
  100. return dev_to_i3cdev(dev)->bus;
  101. master = dev_to_i3cmaster(dev);
  102. return &master->bus;
  103. }
  104. static struct i3c_dev_desc *dev_to_i3cdesc(struct device *dev)
  105. {
  106. struct i3c_master_controller *master;
  107. if (dev->type == &i3c_device_type)
  108. return dev_to_i3cdev(dev)->desc;
  109. master = dev_to_i3cmaster(dev);
  110. return master->this;
  111. }
  112. static ssize_t bcr_show(struct device *dev,
  113. struct device_attribute *da,
  114. char *buf)
  115. {
  116. struct i3c_bus *bus = dev_to_i3cbus(dev);
  117. struct i3c_dev_desc *desc;
  118. ssize_t ret;
  119. i3c_bus_normaluse_lock(bus);
  120. desc = dev_to_i3cdesc(dev);
  121. ret = sprintf(buf, "%x\n", desc->info.bcr);
  122. i3c_bus_normaluse_unlock(bus);
  123. return ret;
  124. }
  125. static DEVICE_ATTR_RO(bcr);
  126. static ssize_t dcr_show(struct device *dev,
  127. struct device_attribute *da,
  128. char *buf)
  129. {
  130. struct i3c_bus *bus = dev_to_i3cbus(dev);
  131. struct i3c_dev_desc *desc;
  132. ssize_t ret;
  133. i3c_bus_normaluse_lock(bus);
  134. desc = dev_to_i3cdesc(dev);
  135. ret = sprintf(buf, "%x\n", desc->info.dcr);
  136. i3c_bus_normaluse_unlock(bus);
  137. return ret;
  138. }
  139. static DEVICE_ATTR_RO(dcr);
  140. static ssize_t pid_show(struct device *dev,
  141. struct device_attribute *da,
  142. char *buf)
  143. {
  144. struct i3c_bus *bus = dev_to_i3cbus(dev);
  145. struct i3c_dev_desc *desc;
  146. ssize_t ret;
  147. i3c_bus_normaluse_lock(bus);
  148. desc = dev_to_i3cdesc(dev);
  149. ret = sprintf(buf, "%llx\n", desc->info.pid);
  150. i3c_bus_normaluse_unlock(bus);
  151. return ret;
  152. }
  153. static DEVICE_ATTR_RO(pid);
  154. static ssize_t dynamic_address_show(struct device *dev,
  155. struct device_attribute *da,
  156. char *buf)
  157. {
  158. struct i3c_bus *bus = dev_to_i3cbus(dev);
  159. struct i3c_dev_desc *desc;
  160. ssize_t ret;
  161. i3c_bus_normaluse_lock(bus);
  162. desc = dev_to_i3cdesc(dev);
  163. ret = sprintf(buf, "%02x\n", desc->info.dyn_addr);
  164. i3c_bus_normaluse_unlock(bus);
  165. return ret;
  166. }
  167. static DEVICE_ATTR_RO(dynamic_address);
  168. static const char * const hdrcap_strings[] = {
  169. "hdr-ddr", "hdr-tsp", "hdr-tsl",
  170. };
  171. static ssize_t hdrcap_show(struct device *dev,
  172. struct device_attribute *da,
  173. char *buf)
  174. {
  175. struct i3c_bus *bus = dev_to_i3cbus(dev);
  176. struct i3c_dev_desc *desc;
  177. ssize_t offset = 0, ret;
  178. unsigned long caps;
  179. int mode;
  180. i3c_bus_normaluse_lock(bus);
  181. desc = dev_to_i3cdesc(dev);
  182. caps = desc->info.hdr_cap;
  183. for_each_set_bit(mode, &caps, 8) {
  184. if (mode >= ARRAY_SIZE(hdrcap_strings))
  185. break;
  186. if (!hdrcap_strings[mode])
  187. continue;
  188. ret = sprintf(buf + offset, offset ? " %s" : "%s",
  189. hdrcap_strings[mode]);
  190. if (ret < 0)
  191. goto out;
  192. offset += ret;
  193. }
  194. ret = sprintf(buf + offset, "\n");
  195. if (ret < 0)
  196. goto out;
  197. ret = offset + ret;
  198. out:
  199. i3c_bus_normaluse_unlock(bus);
  200. return ret;
  201. }
  202. static DEVICE_ATTR_RO(hdrcap);
  203. static ssize_t modalias_show(struct device *dev,
  204. struct device_attribute *da, char *buf)
  205. {
  206. struct i3c_device *i3c = dev_to_i3cdev(dev);
  207. struct i3c_device_info devinfo;
  208. u16 manuf, part, ext;
  209. i3c_device_get_info(i3c, &devinfo);
  210. manuf = I3C_PID_MANUF_ID(devinfo.pid);
  211. part = I3C_PID_PART_ID(devinfo.pid);
  212. ext = I3C_PID_EXTRA_INFO(devinfo.pid);
  213. if (I3C_PID_RND_LOWER_32BITS(devinfo.pid))
  214. return sprintf(buf, "i3c:dcr%02Xmanuf%04X", devinfo.dcr,
  215. manuf);
  216. return sprintf(buf, "i3c:dcr%02Xmanuf%04Xpart%04Xext%04X",
  217. devinfo.dcr, manuf, part, ext);
  218. }
  219. static DEVICE_ATTR_RO(modalias);
  220. static struct attribute *i3c_device_attrs[] = {
  221. &dev_attr_bcr.attr,
  222. &dev_attr_dcr.attr,
  223. &dev_attr_pid.attr,
  224. &dev_attr_dynamic_address.attr,
  225. &dev_attr_hdrcap.attr,
  226. &dev_attr_modalias.attr,
  227. NULL,
  228. };
  229. ATTRIBUTE_GROUPS(i3c_device);
  230. static int i3c_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  231. {
  232. struct i3c_device *i3cdev = dev_to_i3cdev(dev);
  233. struct i3c_device_info devinfo;
  234. u16 manuf, part, ext;
  235. i3c_device_get_info(i3cdev, &devinfo);
  236. manuf = I3C_PID_MANUF_ID(devinfo.pid);
  237. part = I3C_PID_PART_ID(devinfo.pid);
  238. ext = I3C_PID_EXTRA_INFO(devinfo.pid);
  239. if (I3C_PID_RND_LOWER_32BITS(devinfo.pid))
  240. return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X",
  241. devinfo.dcr, manuf);
  242. return add_uevent_var(env,
  243. "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04Xext%04X",
  244. devinfo.dcr, manuf, part, ext);
  245. }
  246. static const struct device_type i3c_device_type = {
  247. .groups = i3c_device_groups,
  248. .uevent = i3c_device_uevent,
  249. };
  250. static int i3c_device_match(struct device *dev, struct device_driver *drv)
  251. {
  252. struct i3c_device *i3cdev;
  253. struct i3c_driver *i3cdrv;
  254. if (dev->type != &i3c_device_type)
  255. return 0;
  256. i3cdev = dev_to_i3cdev(dev);
  257. i3cdrv = drv_to_i3cdrv(drv);
  258. if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
  259. return 1;
  260. return 0;
  261. }
  262. static int i3c_device_probe(struct device *dev)
  263. {
  264. struct i3c_device *i3cdev = dev_to_i3cdev(dev);
  265. struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
  266. return driver->probe(i3cdev);
  267. }
  268. static int i3c_device_remove(struct device *dev)
  269. {
  270. struct i3c_device *i3cdev = dev_to_i3cdev(dev);
  271. struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
  272. int ret;
  273. ret = driver->remove(i3cdev);
  274. if (ret)
  275. return ret;
  276. i3c_device_free_ibi(i3cdev);
  277. return ret;
  278. }
  279. struct bus_type i3c_bus_type = {
  280. .name = "i3c",
  281. .match = i3c_device_match,
  282. .probe = i3c_device_probe,
  283. .remove = i3c_device_remove,
  284. };
  285. static enum i3c_addr_slot_status
  286. i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr)
  287. {
  288. int status, bitpos = addr * 2;
  289. if (addr > I2C_MAX_ADDR)
  290. return I3C_ADDR_SLOT_RSVD;
  291. status = bus->addrslots[bitpos / BITS_PER_LONG];
  292. status >>= bitpos % BITS_PER_LONG;
  293. return status & I3C_ADDR_SLOT_STATUS_MASK;
  294. }
  295. static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
  296. enum i3c_addr_slot_status status)
  297. {
  298. int bitpos = addr * 2;
  299. unsigned long *ptr;
  300. if (addr > I2C_MAX_ADDR)
  301. return;
  302. ptr = bus->addrslots + (bitpos / BITS_PER_LONG);
  303. *ptr &= ~((unsigned long)I3C_ADDR_SLOT_STATUS_MASK <<
  304. (bitpos % BITS_PER_LONG));
  305. *ptr |= (unsigned long)status << (bitpos % BITS_PER_LONG);
  306. }
  307. static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr)
  308. {
  309. enum i3c_addr_slot_status status;
  310. status = i3c_bus_get_addr_slot_status(bus, addr);
  311. return status == I3C_ADDR_SLOT_FREE;
  312. }
  313. static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr)
  314. {
  315. enum i3c_addr_slot_status status;
  316. u8 addr;
  317. for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
  318. status = i3c_bus_get_addr_slot_status(bus, addr);
  319. if (status == I3C_ADDR_SLOT_FREE)
  320. return addr;
  321. }
  322. return -ENOMEM;
  323. }
  324. static void i3c_bus_init_addrslots(struct i3c_bus *bus)
  325. {
  326. int i;
  327. /* Addresses 0 to 7 are reserved. */
  328. for (i = 0; i < 8; i++)
  329. i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD);
  330. /*
  331. * Reserve broadcast address and all addresses that might collide
  332. * with the broadcast address when facing a single bit error.
  333. */
  334. i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR,
  335. I3C_ADDR_SLOT_RSVD);
  336. for (i = 0; i < 7; i++)
  337. i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i),
  338. I3C_ADDR_SLOT_RSVD);
  339. }
  340. static void i3c_bus_cleanup(struct i3c_bus *i3cbus)
  341. {
  342. mutex_lock(&i3c_core_lock);
  343. idr_remove(&i3c_bus_idr, i3cbus->id);
  344. mutex_unlock(&i3c_core_lock);
  345. }
  346. static int i3c_bus_init(struct i3c_bus *i3cbus)
  347. {
  348. int ret;
  349. init_rwsem(&i3cbus->lock);
  350. INIT_LIST_HEAD(&i3cbus->devs.i2c);
  351. INIT_LIST_HEAD(&i3cbus->devs.i3c);
  352. i3c_bus_init_addrslots(i3cbus);
  353. i3cbus->mode = I3C_BUS_MODE_PURE;
  354. mutex_lock(&i3c_core_lock);
  355. ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL);
  356. mutex_unlock(&i3c_core_lock);
  357. if (ret < 0)
  358. return ret;
  359. i3cbus->id = ret;
  360. return 0;
  361. }
  362. static const char * const i3c_bus_mode_strings[] = {
  363. [I3C_BUS_MODE_PURE] = "pure",
  364. [I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",
  365. [I3C_BUS_MODE_MIXED_LIMITED] = "mixed-limited",
  366. [I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",
  367. };
  368. static ssize_t mode_show(struct device *dev,
  369. struct device_attribute *da,
  370. char *buf)
  371. {
  372. struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
  373. ssize_t ret;
  374. i3c_bus_normaluse_lock(i3cbus);
  375. if (i3cbus->mode < 0 ||
  376. i3cbus->mode >= ARRAY_SIZE(i3c_bus_mode_strings) ||
  377. !i3c_bus_mode_strings[i3cbus->mode])
  378. ret = sprintf(buf, "unknown\n");
  379. else
  380. ret = sprintf(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]);
  381. i3c_bus_normaluse_unlock(i3cbus);
  382. return ret;
  383. }
  384. static DEVICE_ATTR_RO(mode);
  385. static ssize_t current_master_show(struct device *dev,
  386. struct device_attribute *da,
  387. char *buf)
  388. {
  389. struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
  390. ssize_t ret;
  391. i3c_bus_normaluse_lock(i3cbus);
  392. ret = sprintf(buf, "%d-%llx\n", i3cbus->id,
  393. i3cbus->cur_master->info.pid);
  394. i3c_bus_normaluse_unlock(i3cbus);
  395. return ret;
  396. }
  397. static DEVICE_ATTR_RO(current_master);
  398. static ssize_t i3c_scl_frequency_show(struct device *dev,
  399. struct device_attribute *da,
  400. char *buf)
  401. {
  402. struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
  403. ssize_t ret;
  404. i3c_bus_normaluse_lock(i3cbus);
  405. ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c);
  406. i3c_bus_normaluse_unlock(i3cbus);
  407. return ret;
  408. }
  409. static DEVICE_ATTR_RO(i3c_scl_frequency);
  410. static ssize_t i2c_scl_frequency_show(struct device *dev,
  411. struct device_attribute *da,
  412. char *buf)
  413. {
  414. struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
  415. ssize_t ret;
  416. i3c_bus_normaluse_lock(i3cbus);
  417. ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i2c);
  418. i3c_bus_normaluse_unlock(i3cbus);
  419. return ret;
  420. }
  421. static DEVICE_ATTR_RO(i2c_scl_frequency);
  422. static struct attribute *i3c_masterdev_attrs[] = {
  423. &dev_attr_mode.attr,
  424. &dev_attr_current_master.attr,
  425. &dev_attr_i3c_scl_frequency.attr,
  426. &dev_attr_i2c_scl_frequency.attr,
  427. &dev_attr_bcr.attr,
  428. &dev_attr_dcr.attr,
  429. &dev_attr_pid.attr,
  430. &dev_attr_dynamic_address.attr,
  431. &dev_attr_hdrcap.attr,
  432. NULL,
  433. };
  434. ATTRIBUTE_GROUPS(i3c_masterdev);
  435. static void i3c_masterdev_release(struct device *dev)
  436. {
  437. struct i3c_master_controller *master = dev_to_i3cmaster(dev);
  438. struct i3c_bus *bus = dev_to_i3cbus(dev);
  439. if (master->wq)
  440. destroy_workqueue(master->wq);
  441. WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c));
  442. i3c_bus_cleanup(bus);
  443. of_node_put(dev->of_node);
  444. }
  445. static const struct device_type i3c_masterdev_type = {
  446. .groups = i3c_masterdev_groups,
  447. };
  448. static int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode,
  449. unsigned long max_i2c_scl_rate)
  450. {
  451. struct i3c_master_controller *master = i3c_bus_to_i3c_master(i3cbus);
  452. i3cbus->mode = mode;
  453. switch (i3cbus->mode) {
  454. case I3C_BUS_MODE_PURE:
  455. if (!i3cbus->scl_rate.i3c)
  456. i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
  457. break;
  458. case I3C_BUS_MODE_MIXED_FAST:
  459. case I3C_BUS_MODE_MIXED_LIMITED:
  460. if (!i3cbus->scl_rate.i3c)
  461. i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
  462. if (!i3cbus->scl_rate.i2c)
  463. i3cbus->scl_rate.i2c = max_i2c_scl_rate;
  464. break;
  465. case I3C_BUS_MODE_MIXED_SLOW:
  466. if (!i3cbus->scl_rate.i2c)
  467. i3cbus->scl_rate.i2c = max_i2c_scl_rate;
  468. if (!i3cbus->scl_rate.i3c ||
  469. i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c)
  470. i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c;
  471. break;
  472. default:
  473. return -EINVAL;
  474. }
  475. dev_dbg(&master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n",
  476. i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c);
  477. /*
  478. * I3C/I2C frequency may have been overridden, check that user-provided
  479. * values are not exceeding max possible frequency.
  480. */
  481. if (i3cbus->scl_rate.i3c > I3C_BUS_MAX_I3C_SCL_RATE ||
  482. i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_RATE)
  483. return -EINVAL;
  484. return 0;
  485. }
  486. static struct i3c_master_controller *
  487. i2c_adapter_to_i3c_master(struct i2c_adapter *adap)
  488. {
  489. return container_of(adap, struct i3c_master_controller, i2c);
  490. }
  491. static struct i2c_adapter *
  492. i3c_master_to_i2c_adapter(struct i3c_master_controller *master)
  493. {
  494. return &master->i2c;
  495. }
  496. static void i3c_master_free_i2c_dev(struct i2c_dev_desc *dev)
  497. {
  498. kfree(dev);
  499. }
  500. static struct i2c_dev_desc *
  501. i3c_master_alloc_i2c_dev(struct i3c_master_controller *master,
  502. const struct i2c_dev_boardinfo *boardinfo)
  503. {
  504. struct i2c_dev_desc *dev;
  505. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  506. if (!dev)
  507. return ERR_PTR(-ENOMEM);
  508. dev->common.master = master;
  509. dev->boardinfo = boardinfo;
  510. dev->addr = boardinfo->base.addr;
  511. dev->lvr = boardinfo->lvr;
  512. return dev;
  513. }
  514. static void *i3c_ccc_cmd_dest_init(struct i3c_ccc_cmd_dest *dest, u8 addr,
  515. u16 payloadlen)
  516. {
  517. dest->addr = addr;
  518. dest->payload.len = payloadlen;
  519. if (payloadlen)
  520. dest->payload.data = kzalloc(payloadlen, GFP_KERNEL);
  521. else
  522. dest->payload.data = NULL;
  523. return dest->payload.data;
  524. }
  525. static void i3c_ccc_cmd_dest_cleanup(struct i3c_ccc_cmd_dest *dest)
  526. {
  527. kfree(dest->payload.data);
  528. }
  529. static void i3c_ccc_cmd_init(struct i3c_ccc_cmd *cmd, bool rnw, u8 id,
  530. struct i3c_ccc_cmd_dest *dests,
  531. unsigned int ndests)
  532. {
  533. cmd->rnw = rnw ? 1 : 0;
  534. cmd->id = id;
  535. cmd->dests = dests;
  536. cmd->ndests = ndests;
  537. cmd->err = I3C_ERROR_UNKNOWN;
  538. }
  539. static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master,
  540. struct i3c_ccc_cmd *cmd)
  541. {
  542. int ret;
  543. if (!cmd || !master)
  544. return -EINVAL;
  545. if (WARN_ON(master->init_done &&
  546. !rwsem_is_locked(&master->bus.lock)))
  547. return -EINVAL;
  548. if (!master->ops->send_ccc_cmd)
  549. return -ENOTSUPP;
  550. if ((cmd->id & I3C_CCC_DIRECT) && (!cmd->dests || !cmd->ndests))
  551. return -EINVAL;
  552. if (master->ops->supports_ccc_cmd &&
  553. !master->ops->supports_ccc_cmd(master, cmd))
  554. return -ENOTSUPP;
  555. ret = master->ops->send_ccc_cmd(master, cmd);
  556. if (ret) {
  557. if (cmd->err != I3C_ERROR_UNKNOWN)
  558. return cmd->err;
  559. return ret;
  560. }
  561. return 0;
  562. }
  563. static struct i2c_dev_desc *
  564. i3c_master_find_i2c_dev_by_addr(const struct i3c_master_controller *master,
  565. u16 addr)
  566. {
  567. struct i2c_dev_desc *dev;
  568. i3c_bus_for_each_i2cdev(&master->bus, dev) {
  569. if (dev->boardinfo->base.addr == addr)
  570. return dev;
  571. }
  572. return NULL;
  573. }
  574. /**
  575. * i3c_master_get_free_addr() - get a free address on the bus
  576. * @master: I3C master object
  577. * @start_addr: where to start searching
  578. *
  579. * This function must be called with the bus lock held in write mode.
  580. *
  581. * Return: the first free address starting at @start_addr (included) or -ENOMEM
  582. * if there's no more address available.
  583. */
  584. int i3c_master_get_free_addr(struct i3c_master_controller *master,
  585. u8 start_addr)
  586. {
  587. return i3c_bus_get_free_addr(&master->bus, start_addr);
  588. }
  589. EXPORT_SYMBOL_GPL(i3c_master_get_free_addr);
  590. static void i3c_device_release(struct device *dev)
  591. {
  592. struct i3c_device *i3cdev = dev_to_i3cdev(dev);
  593. WARN_ON(i3cdev->desc);
  594. of_node_put(i3cdev->dev.of_node);
  595. kfree(i3cdev);
  596. }
  597. static void i3c_master_free_i3c_dev(struct i3c_dev_desc *dev)
  598. {
  599. kfree(dev);
  600. }
  601. static struct i3c_dev_desc *
  602. i3c_master_alloc_i3c_dev(struct i3c_master_controller *master,
  603. const struct i3c_device_info *info)
  604. {
  605. struct i3c_dev_desc *dev;
  606. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  607. if (!dev)
  608. return ERR_PTR(-ENOMEM);
  609. dev->common.master = master;
  610. dev->info = *info;
  611. mutex_init(&dev->ibi_lock);
  612. return dev;
  613. }
  614. static int i3c_master_rstdaa_locked(struct i3c_master_controller *master,
  615. u8 addr)
  616. {
  617. enum i3c_addr_slot_status addrstat;
  618. struct i3c_ccc_cmd_dest dest;
  619. struct i3c_ccc_cmd cmd;
  620. int ret;
  621. if (!master)
  622. return -EINVAL;
  623. addrstat = i3c_bus_get_addr_slot_status(&master->bus, addr);
  624. if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV)
  625. return -EINVAL;
  626. i3c_ccc_cmd_dest_init(&dest, addr, 0);
  627. i3c_ccc_cmd_init(&cmd, false,
  628. I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR),
  629. &dest, 1);
  630. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  631. i3c_ccc_cmd_dest_cleanup(&dest);
  632. return ret;
  633. }
  634. /**
  635. * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
  636. * procedure
  637. * @master: master used to send frames on the bus
  638. *
  639. * Send a ENTDAA CCC command to start a DAA procedure.
  640. *
  641. * Note that this function only sends the ENTDAA CCC command, all the logic
  642. * behind dynamic address assignment has to be handled in the I3C master
  643. * driver.
  644. *
  645. * This function must be called with the bus lock held in write mode.
  646. *
  647. * Return: 0 in case of success, a positive I3C error code if the error is
  648. * one of the official Mx error codes, and a negative error code otherwise.
  649. */
  650. int i3c_master_entdaa_locked(struct i3c_master_controller *master)
  651. {
  652. struct i3c_ccc_cmd_dest dest;
  653. struct i3c_ccc_cmd cmd;
  654. int ret;
  655. i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0);
  656. i3c_ccc_cmd_init(&cmd, false, I3C_CCC_ENTDAA, &dest, 1);
  657. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  658. i3c_ccc_cmd_dest_cleanup(&dest);
  659. return ret;
  660. }
  661. EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);
  662. static int i3c_master_enec_disec_locked(struct i3c_master_controller *master,
  663. u8 addr, bool enable, u8 evts)
  664. {
  665. struct i3c_ccc_events *events;
  666. struct i3c_ccc_cmd_dest dest;
  667. struct i3c_ccc_cmd cmd;
  668. int ret;
  669. events = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*events));
  670. if (!events)
  671. return -ENOMEM;
  672. events->events = evts;
  673. i3c_ccc_cmd_init(&cmd, false,
  674. enable ?
  675. I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR) :
  676. I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR),
  677. &dest, 1);
  678. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  679. i3c_ccc_cmd_dest_cleanup(&dest);
  680. return ret;
  681. }
  682. /**
  683. * i3c_master_disec_locked() - send a DISEC CCC command
  684. * @master: master used to send frames on the bus
  685. * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
  686. * @evts: events to disable
  687. *
  688. * Send a DISEC CCC command to disable some or all events coming from a
  689. * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
  690. *
  691. * This function must be called with the bus lock held in write mode.
  692. *
  693. * Return: 0 in case of success, a positive I3C error code if the error is
  694. * one of the official Mx error codes, and a negative error code otherwise.
  695. */
  696. int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
  697. u8 evts)
  698. {
  699. return i3c_master_enec_disec_locked(master, addr, false, evts);
  700. }
  701. EXPORT_SYMBOL_GPL(i3c_master_disec_locked);
  702. /**
  703. * i3c_master_enec_locked() - send an ENEC CCC command
  704. * @master: master used to send frames on the bus
  705. * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
  706. * @evts: events to disable
  707. *
  708. * Sends an ENEC CCC command to enable some or all events coming from a
  709. * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
  710. *
  711. * This function must be called with the bus lock held in write mode.
  712. *
  713. * Return: 0 in case of success, a positive I3C error code if the error is
  714. * one of the official Mx error codes, and a negative error code otherwise.
  715. */
  716. int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
  717. u8 evts)
  718. {
  719. return i3c_master_enec_disec_locked(master, addr, true, evts);
  720. }
  721. EXPORT_SYMBOL_GPL(i3c_master_enec_locked);
  722. /**
  723. * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
  724. * @master: master used to send frames on the bus
  725. *
  726. * Send a DEFSLVS CCC command containing all the devices known to the @master.
  727. * This is useful when you have secondary masters on the bus to propagate
  728. * device information.
  729. *
  730. * This should be called after all I3C devices have been discovered (in other
  731. * words, after the DAA procedure has finished) and instantiated in
  732. * &i3c_master_controller_ops->bus_init().
  733. * It should also be called if a master ACKed an Hot-Join request and assigned
  734. * a dynamic address to the device joining the bus.
  735. *
  736. * This function must be called with the bus lock held in write mode.
  737. *
  738. * Return: 0 in case of success, a positive I3C error code if the error is
  739. * one of the official Mx error codes, and a negative error code otherwise.
  740. */
  741. int i3c_master_defslvs_locked(struct i3c_master_controller *master)
  742. {
  743. struct i3c_ccc_defslvs *defslvs;
  744. struct i3c_ccc_dev_desc *desc;
  745. struct i3c_ccc_cmd_dest dest;
  746. struct i3c_dev_desc *i3cdev;
  747. struct i2c_dev_desc *i2cdev;
  748. struct i3c_ccc_cmd cmd;
  749. struct i3c_bus *bus;
  750. bool send = false;
  751. int ndevs = 0, ret;
  752. if (!master)
  753. return -EINVAL;
  754. bus = i3c_master_get_bus(master);
  755. i3c_bus_for_each_i3cdev(bus, i3cdev) {
  756. ndevs++;
  757. if (i3cdev == master->this)
  758. continue;
  759. if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) ==
  760. I3C_BCR_I3C_MASTER)
  761. send = true;
  762. }
  763. /* No other master on the bus, skip DEFSLVS. */
  764. if (!send)
  765. return 0;
  766. i3c_bus_for_each_i2cdev(bus, i2cdev)
  767. ndevs++;
  768. defslvs = i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR,
  769. struct_size(defslvs, slaves,
  770. ndevs - 1));
  771. if (!defslvs)
  772. return -ENOMEM;
  773. defslvs->count = ndevs;
  774. defslvs->master.bcr = master->this->info.bcr;
  775. defslvs->master.dcr = master->this->info.dcr;
  776. defslvs->master.dyn_addr = master->this->info.dyn_addr << 1;
  777. defslvs->master.static_addr = I3C_BROADCAST_ADDR << 1;
  778. desc = defslvs->slaves;
  779. i3c_bus_for_each_i2cdev(bus, i2cdev) {
  780. desc->lvr = i2cdev->lvr;
  781. desc->static_addr = i2cdev->addr << 1;
  782. desc++;
  783. }
  784. i3c_bus_for_each_i3cdev(bus, i3cdev) {
  785. /* Skip the I3C dev representing this master. */
  786. if (i3cdev == master->this)
  787. continue;
  788. desc->bcr = i3cdev->info.bcr;
  789. desc->dcr = i3cdev->info.dcr;
  790. desc->dyn_addr = i3cdev->info.dyn_addr << 1;
  791. desc->static_addr = i3cdev->info.static_addr << 1;
  792. desc++;
  793. }
  794. i3c_ccc_cmd_init(&cmd, false, I3C_CCC_DEFSLVS, &dest, 1);
  795. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  796. i3c_ccc_cmd_dest_cleanup(&dest);
  797. return ret;
  798. }
  799. EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
  800. static int i3c_master_setda_locked(struct i3c_master_controller *master,
  801. u8 oldaddr, u8 newaddr, bool setdasa)
  802. {
  803. struct i3c_ccc_cmd_dest dest;
  804. struct i3c_ccc_setda *setda;
  805. struct i3c_ccc_cmd cmd;
  806. int ret;
  807. if (!oldaddr || !newaddr)
  808. return -EINVAL;
  809. setda = i3c_ccc_cmd_dest_init(&dest, oldaddr, sizeof(*setda));
  810. if (!setda)
  811. return -ENOMEM;
  812. setda->addr = newaddr << 1;
  813. i3c_ccc_cmd_init(&cmd, false,
  814. setdasa ? I3C_CCC_SETDASA : I3C_CCC_SETNEWDA,
  815. &dest, 1);
  816. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  817. i3c_ccc_cmd_dest_cleanup(&dest);
  818. return ret;
  819. }
  820. static int i3c_master_setdasa_locked(struct i3c_master_controller *master,
  821. u8 static_addr, u8 dyn_addr)
  822. {
  823. return i3c_master_setda_locked(master, static_addr, dyn_addr, true);
  824. }
  825. static int i3c_master_setnewda_locked(struct i3c_master_controller *master,
  826. u8 oldaddr, u8 newaddr)
  827. {
  828. return i3c_master_setda_locked(master, oldaddr, newaddr, false);
  829. }
  830. static int i3c_master_getmrl_locked(struct i3c_master_controller *master,
  831. struct i3c_device_info *info)
  832. {
  833. struct i3c_ccc_cmd_dest dest;
  834. struct i3c_ccc_mrl *mrl;
  835. struct i3c_ccc_cmd cmd;
  836. int ret;
  837. mrl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mrl));
  838. if (!mrl)
  839. return -ENOMEM;
  840. /*
  841. * When the device does not have IBI payload GETMRL only returns 2
  842. * bytes of data.
  843. */
  844. if (!(info->bcr & I3C_BCR_IBI_PAYLOAD))
  845. dest.payload.len -= 1;
  846. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMRL, &dest, 1);
  847. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  848. if (ret)
  849. goto out;
  850. switch (dest.payload.len) {
  851. case 3:
  852. info->max_ibi_len = mrl->ibi_len;
  853. fallthrough;
  854. case 2:
  855. info->max_read_len = be16_to_cpu(mrl->read_len);
  856. break;
  857. default:
  858. ret = -EIO;
  859. goto out;
  860. }
  861. out:
  862. i3c_ccc_cmd_dest_cleanup(&dest);
  863. return ret;
  864. }
  865. static int i3c_master_getmwl_locked(struct i3c_master_controller *master,
  866. struct i3c_device_info *info)
  867. {
  868. struct i3c_ccc_cmd_dest dest;
  869. struct i3c_ccc_mwl *mwl;
  870. struct i3c_ccc_cmd cmd;
  871. int ret;
  872. mwl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mwl));
  873. if (!mwl)
  874. return -ENOMEM;
  875. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMWL, &dest, 1);
  876. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  877. if (ret)
  878. goto out;
  879. if (dest.payload.len != sizeof(*mwl)) {
  880. ret = -EIO;
  881. goto out;
  882. }
  883. info->max_write_len = be16_to_cpu(mwl->len);
  884. out:
  885. i3c_ccc_cmd_dest_cleanup(&dest);
  886. return ret;
  887. }
  888. static int i3c_master_getmxds_locked(struct i3c_master_controller *master,
  889. struct i3c_device_info *info)
  890. {
  891. struct i3c_ccc_getmxds *getmaxds;
  892. struct i3c_ccc_cmd_dest dest;
  893. struct i3c_ccc_cmd cmd;
  894. int ret;
  895. getmaxds = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr,
  896. sizeof(*getmaxds));
  897. if (!getmaxds)
  898. return -ENOMEM;
  899. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1);
  900. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  901. if (ret)
  902. goto out;
  903. if (dest.payload.len != 2 && dest.payload.len != 5) {
  904. ret = -EIO;
  905. goto out;
  906. }
  907. info->max_read_ds = getmaxds->maxrd;
  908. info->max_write_ds = getmaxds->maxwr;
  909. if (dest.payload.len == 5)
  910. info->max_read_turnaround = getmaxds->maxrdturn[0] |
  911. ((u32)getmaxds->maxrdturn[1] << 8) |
  912. ((u32)getmaxds->maxrdturn[2] << 16);
  913. out:
  914. i3c_ccc_cmd_dest_cleanup(&dest);
  915. return ret;
  916. }
  917. static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master,
  918. struct i3c_device_info *info)
  919. {
  920. struct i3c_ccc_gethdrcap *gethdrcap;
  921. struct i3c_ccc_cmd_dest dest;
  922. struct i3c_ccc_cmd cmd;
  923. int ret;
  924. gethdrcap = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr,
  925. sizeof(*gethdrcap));
  926. if (!gethdrcap)
  927. return -ENOMEM;
  928. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETHDRCAP, &dest, 1);
  929. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  930. if (ret)
  931. goto out;
  932. if (dest.payload.len != 1) {
  933. ret = -EIO;
  934. goto out;
  935. }
  936. info->hdr_cap = gethdrcap->modes;
  937. out:
  938. i3c_ccc_cmd_dest_cleanup(&dest);
  939. return ret;
  940. }
  941. static int i3c_master_getpid_locked(struct i3c_master_controller *master,
  942. struct i3c_device_info *info)
  943. {
  944. struct i3c_ccc_getpid *getpid;
  945. struct i3c_ccc_cmd_dest dest;
  946. struct i3c_ccc_cmd cmd;
  947. int ret, i;
  948. getpid = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getpid));
  949. if (!getpid)
  950. return -ENOMEM;
  951. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETPID, &dest, 1);
  952. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  953. if (ret)
  954. goto out;
  955. info->pid = 0;
  956. for (i = 0; i < sizeof(getpid->pid); i++) {
  957. int sft = (sizeof(getpid->pid) - i - 1) * 8;
  958. info->pid |= (u64)getpid->pid[i] << sft;
  959. }
  960. out:
  961. i3c_ccc_cmd_dest_cleanup(&dest);
  962. return ret;
  963. }
  964. static int i3c_master_getbcr_locked(struct i3c_master_controller *master,
  965. struct i3c_device_info *info)
  966. {
  967. struct i3c_ccc_getbcr *getbcr;
  968. struct i3c_ccc_cmd_dest dest;
  969. struct i3c_ccc_cmd cmd;
  970. int ret;
  971. getbcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getbcr));
  972. if (!getbcr)
  973. return -ENOMEM;
  974. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETBCR, &dest, 1);
  975. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  976. if (ret)
  977. goto out;
  978. info->bcr = getbcr->bcr;
  979. out:
  980. i3c_ccc_cmd_dest_cleanup(&dest);
  981. return ret;
  982. }
  983. static int i3c_master_getdcr_locked(struct i3c_master_controller *master,
  984. struct i3c_device_info *info)
  985. {
  986. struct i3c_ccc_getdcr *getdcr;
  987. struct i3c_ccc_cmd_dest dest;
  988. struct i3c_ccc_cmd cmd;
  989. int ret;
  990. getdcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getdcr));
  991. if (!getdcr)
  992. return -ENOMEM;
  993. i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETDCR, &dest, 1);
  994. ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
  995. if (ret)
  996. goto out;
  997. info->dcr = getdcr->dcr;
  998. out:
  999. i3c_ccc_cmd_dest_cleanup(&dest);
  1000. return ret;
  1001. }
  1002. static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev)
  1003. {
  1004. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  1005. enum i3c_addr_slot_status slot_status;
  1006. int ret;
  1007. if (!dev->info.dyn_addr)
  1008. return -EINVAL;
  1009. slot_status = i3c_bus_get_addr_slot_status(&master->bus,
  1010. dev->info.dyn_addr);
  1011. if (slot_status == I3C_ADDR_SLOT_RSVD ||
  1012. slot_status == I3C_ADDR_SLOT_I2C_DEV)
  1013. return -EINVAL;
  1014. ret = i3c_master_getpid_locked(master, &dev->info);
  1015. if (ret)
  1016. return ret;
  1017. ret = i3c_master_getbcr_locked(master, &dev->info);
  1018. if (ret)
  1019. return ret;
  1020. ret = i3c_master_getdcr_locked(master, &dev->info);
  1021. if (ret)
  1022. return ret;
  1023. if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) {
  1024. ret = i3c_master_getmxds_locked(master, &dev->info);
  1025. if (ret)
  1026. return ret;
  1027. }
  1028. if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
  1029. dev->info.max_ibi_len = 1;
  1030. i3c_master_getmrl_locked(master, &dev->info);
  1031. i3c_master_getmwl_locked(master, &dev->info);
  1032. if (dev->info.bcr & I3C_BCR_HDR_CAP) {
  1033. ret = i3c_master_gethdrcap_locked(master, &dev->info);
  1034. if (ret)
  1035. return ret;
  1036. }
  1037. return 0;
  1038. }
  1039. static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev)
  1040. {
  1041. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  1042. if (dev->info.static_addr)
  1043. i3c_bus_set_addr_slot_status(&master->bus,
  1044. dev->info.static_addr,
  1045. I3C_ADDR_SLOT_FREE);
  1046. if (dev->info.dyn_addr)
  1047. i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
  1048. I3C_ADDR_SLOT_FREE);
  1049. if (dev->boardinfo && dev->boardinfo->init_dyn_addr)
  1050. i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
  1051. I3C_ADDR_SLOT_FREE);
  1052. }
  1053. static int i3c_master_get_i3c_addrs(struct i3c_dev_desc *dev)
  1054. {
  1055. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  1056. enum i3c_addr_slot_status status;
  1057. if (!dev->info.static_addr && !dev->info.dyn_addr)
  1058. return 0;
  1059. if (dev->info.static_addr) {
  1060. status = i3c_bus_get_addr_slot_status(&master->bus,
  1061. dev->info.static_addr);
  1062. if (status != I3C_ADDR_SLOT_FREE)
  1063. return -EBUSY;
  1064. i3c_bus_set_addr_slot_status(&master->bus,
  1065. dev->info.static_addr,
  1066. I3C_ADDR_SLOT_I3C_DEV);
  1067. }
  1068. /*
  1069. * ->init_dyn_addr should have been reserved before that, so, if we're
  1070. * trying to apply a pre-reserved dynamic address, we should not try
  1071. * to reserve the address slot a second time.
  1072. */
  1073. if (dev->info.dyn_addr &&
  1074. (!dev->boardinfo ||
  1075. dev->boardinfo->init_dyn_addr != dev->info.dyn_addr)) {
  1076. status = i3c_bus_get_addr_slot_status(&master->bus,
  1077. dev->info.dyn_addr);
  1078. if (status != I3C_ADDR_SLOT_FREE)
  1079. goto err_release_static_addr;
  1080. i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
  1081. I3C_ADDR_SLOT_I3C_DEV);
  1082. }
  1083. return 0;
  1084. err_release_static_addr:
  1085. if (dev->info.static_addr)
  1086. i3c_bus_set_addr_slot_status(&master->bus,
  1087. dev->info.static_addr,
  1088. I3C_ADDR_SLOT_FREE);
  1089. return -EBUSY;
  1090. }
  1091. static int i3c_master_attach_i3c_dev(struct i3c_master_controller *master,
  1092. struct i3c_dev_desc *dev)
  1093. {
  1094. int ret;
  1095. /*
  1096. * We don't attach devices to the controller until they are
  1097. * addressable on the bus.
  1098. */
  1099. if (!dev->info.static_addr && !dev->info.dyn_addr)
  1100. return 0;
  1101. ret = i3c_master_get_i3c_addrs(dev);
  1102. if (ret)
  1103. return ret;
  1104. /* Do not attach the master device itself. */
  1105. if (master->this != dev && master->ops->attach_i3c_dev) {
  1106. ret = master->ops->attach_i3c_dev(dev);
  1107. if (ret) {
  1108. i3c_master_put_i3c_addrs(dev);
  1109. return ret;
  1110. }
  1111. }
  1112. list_add_tail(&dev->common.node, &master->bus.devs.i3c);
  1113. return 0;
  1114. }
  1115. static int i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
  1116. u8 old_dyn_addr)
  1117. {
  1118. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  1119. enum i3c_addr_slot_status status;
  1120. int ret;
  1121. if (dev->info.dyn_addr != old_dyn_addr &&
  1122. (!dev->boardinfo ||
  1123. dev->info.dyn_addr != dev->boardinfo->init_dyn_addr)) {
  1124. status = i3c_bus_get_addr_slot_status(&master->bus,
  1125. dev->info.dyn_addr);
  1126. if (status != I3C_ADDR_SLOT_FREE)
  1127. return -EBUSY;
  1128. i3c_bus_set_addr_slot_status(&master->bus,
  1129. dev->info.dyn_addr,
  1130. I3C_ADDR_SLOT_I3C_DEV);
  1131. }
  1132. if (master->ops->reattach_i3c_dev) {
  1133. ret = master->ops->reattach_i3c_dev(dev, old_dyn_addr);
  1134. if (ret) {
  1135. i3c_master_put_i3c_addrs(dev);
  1136. return ret;
  1137. }
  1138. }
  1139. return 0;
  1140. }
  1141. static void i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
  1142. {
  1143. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  1144. /* Do not detach the master device itself. */
  1145. if (master->this != dev && master->ops->detach_i3c_dev)
  1146. master->ops->detach_i3c_dev(dev);
  1147. i3c_master_put_i3c_addrs(dev);
  1148. list_del(&dev->common.node);
  1149. }
  1150. static int i3c_master_attach_i2c_dev(struct i3c_master_controller *master,
  1151. struct i2c_dev_desc *dev)
  1152. {
  1153. int ret;
  1154. if (master->ops->attach_i2c_dev) {
  1155. ret = master->ops->attach_i2c_dev(dev);
  1156. if (ret)
  1157. return ret;
  1158. }
  1159. list_add_tail(&dev->common.node, &master->bus.devs.i2c);
  1160. return 0;
  1161. }
  1162. static void i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
  1163. {
  1164. struct i3c_master_controller *master = i2c_dev_get_master(dev);
  1165. list_del(&dev->common.node);
  1166. if (master->ops->detach_i2c_dev)
  1167. master->ops->detach_i2c_dev(dev);
  1168. }
  1169. static int i3c_master_early_i3c_dev_add(struct i3c_master_controller *master,
  1170. struct i3c_dev_boardinfo *boardinfo)
  1171. {
  1172. struct i3c_device_info info = {
  1173. .static_addr = boardinfo->static_addr,
  1174. };
  1175. struct i3c_dev_desc *i3cdev;
  1176. int ret;
  1177. i3cdev = i3c_master_alloc_i3c_dev(master, &info);
  1178. if (IS_ERR(i3cdev))
  1179. return -ENOMEM;
  1180. i3cdev->boardinfo = boardinfo;
  1181. ret = i3c_master_attach_i3c_dev(master, i3cdev);
  1182. if (ret)
  1183. goto err_free_dev;
  1184. ret = i3c_master_setdasa_locked(master, i3cdev->info.static_addr,
  1185. i3cdev->boardinfo->init_dyn_addr);
  1186. if (ret)
  1187. goto err_detach_dev;
  1188. i3cdev->info.dyn_addr = i3cdev->boardinfo->init_dyn_addr;
  1189. ret = i3c_master_reattach_i3c_dev(i3cdev, 0);
  1190. if (ret)
  1191. goto err_rstdaa;
  1192. ret = i3c_master_retrieve_dev_info(i3cdev);
  1193. if (ret)
  1194. goto err_rstdaa;
  1195. return 0;
  1196. err_rstdaa:
  1197. i3c_master_rstdaa_locked(master, i3cdev->boardinfo->init_dyn_addr);
  1198. err_detach_dev:
  1199. i3c_master_detach_i3c_dev(i3cdev);
  1200. err_free_dev:
  1201. i3c_master_free_i3c_dev(i3cdev);
  1202. return ret;
  1203. }
  1204. static void
  1205. i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
  1206. {
  1207. struct i3c_dev_desc *desc;
  1208. int ret;
  1209. if (!master->init_done)
  1210. return;
  1211. i3c_bus_for_each_i3cdev(&master->bus, desc) {
  1212. if (desc->dev || !desc->info.dyn_addr || desc == master->this)
  1213. continue;
  1214. desc->dev = kzalloc(sizeof(*desc->dev), GFP_KERNEL);
  1215. if (!desc->dev)
  1216. continue;
  1217. desc->dev->bus = &master->bus;
  1218. desc->dev->desc = desc;
  1219. desc->dev->dev.parent = &master->dev;
  1220. desc->dev->dev.type = &i3c_device_type;
  1221. desc->dev->dev.bus = &i3c_bus_type;
  1222. desc->dev->dev.release = i3c_device_release;
  1223. dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id,
  1224. desc->info.pid);
  1225. if (desc->boardinfo)
  1226. desc->dev->dev.of_node = desc->boardinfo->of_node;
  1227. ret = device_register(&desc->dev->dev);
  1228. if (ret)
  1229. dev_err(&master->dev,
  1230. "Failed to add I3C device (err = %d)\n", ret);
  1231. }
  1232. }
  1233. /**
  1234. * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment)
  1235. * @master: master doing the DAA
  1236. *
  1237. * This function is instantiating an I3C device object and adding it to the
  1238. * I3C device list. All device information are automatically retrieved using
  1239. * standard CCC commands.
  1240. *
  1241. * The I3C device object is returned in case the master wants to attach
  1242. * private data to it using i3c_dev_set_master_data().
  1243. *
  1244. * This function must be called with the bus lock held in write mode.
  1245. *
  1246. * Return: a 0 in case of success, an negative error code otherwise.
  1247. */
  1248. int i3c_master_do_daa(struct i3c_master_controller *master)
  1249. {
  1250. int ret;
  1251. i3c_bus_maintenance_lock(&master->bus);
  1252. ret = master->ops->do_daa(master);
  1253. i3c_bus_maintenance_unlock(&master->bus);
  1254. if (ret)
  1255. return ret;
  1256. i3c_bus_normaluse_lock(&master->bus);
  1257. i3c_master_register_new_i3c_devs(master);
  1258. i3c_bus_normaluse_unlock(&master->bus);
  1259. return 0;
  1260. }
  1261. EXPORT_SYMBOL_GPL(i3c_master_do_daa);
  1262. /**
  1263. * i3c_master_set_info() - set master device information
  1264. * @master: master used to send frames on the bus
  1265. * @info: I3C device information
  1266. *
  1267. * Set master device info. This should be called from
  1268. * &i3c_master_controller_ops->bus_init().
  1269. *
  1270. * Not all &i3c_device_info fields are meaningful for a master device.
  1271. * Here is a list of fields that should be properly filled:
  1272. *
  1273. * - &i3c_device_info->dyn_addr
  1274. * - &i3c_device_info->bcr
  1275. * - &i3c_device_info->dcr
  1276. * - &i3c_device_info->pid
  1277. * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in
  1278. * &i3c_device_info->bcr
  1279. *
  1280. * This function must be called with the bus lock held in maintenance mode.
  1281. *
  1282. * Return: 0 if @info contains valid information (not every piece of
  1283. * information can be checked, but we can at least make sure @info->dyn_addr
  1284. * and @info->bcr are correct), -EINVAL otherwise.
  1285. */
  1286. int i3c_master_set_info(struct i3c_master_controller *master,
  1287. const struct i3c_device_info *info)
  1288. {
  1289. struct i3c_dev_desc *i3cdev;
  1290. int ret;
  1291. if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr))
  1292. return -EINVAL;
  1293. if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER &&
  1294. master->secondary)
  1295. return -EINVAL;
  1296. if (master->this)
  1297. return -EINVAL;
  1298. i3cdev = i3c_master_alloc_i3c_dev(master, info);
  1299. if (IS_ERR(i3cdev))
  1300. return PTR_ERR(i3cdev);
  1301. master->this = i3cdev;
  1302. master->bus.cur_master = master->this;
  1303. ret = i3c_master_attach_i3c_dev(master, i3cdev);
  1304. if (ret)
  1305. goto err_free_dev;
  1306. return 0;
  1307. err_free_dev:
  1308. i3c_master_free_i3c_dev(i3cdev);
  1309. return ret;
  1310. }
  1311. EXPORT_SYMBOL_GPL(i3c_master_set_info);
  1312. static void i3c_master_detach_free_devs(struct i3c_master_controller *master)
  1313. {
  1314. struct i3c_dev_desc *i3cdev, *i3ctmp;
  1315. struct i2c_dev_desc *i2cdev, *i2ctmp;
  1316. list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c,
  1317. common.node) {
  1318. i3c_master_detach_i3c_dev(i3cdev);
  1319. if (i3cdev->boardinfo && i3cdev->boardinfo->init_dyn_addr)
  1320. i3c_bus_set_addr_slot_status(&master->bus,
  1321. i3cdev->boardinfo->init_dyn_addr,
  1322. I3C_ADDR_SLOT_FREE);
  1323. i3c_master_free_i3c_dev(i3cdev);
  1324. }
  1325. list_for_each_entry_safe(i2cdev, i2ctmp, &master->bus.devs.i2c,
  1326. common.node) {
  1327. i3c_master_detach_i2c_dev(i2cdev);
  1328. i3c_bus_set_addr_slot_status(&master->bus,
  1329. i2cdev->addr,
  1330. I3C_ADDR_SLOT_FREE);
  1331. i3c_master_free_i2c_dev(i2cdev);
  1332. }
  1333. }
  1334. /**
  1335. * i3c_master_bus_init() - initialize an I3C bus
  1336. * @master: main master initializing the bus
  1337. *
  1338. * This function is following all initialisation steps described in the I3C
  1339. * specification:
  1340. *
  1341. * 1. Attach I2C devs to the master so that the master can fill its internal
  1342. * device table appropriately
  1343. *
  1344. * 2. Call &i3c_master_controller_ops->bus_init() method to initialize
  1345. * the master controller. That's usually where the bus mode is selected
  1346. * (pure bus or mixed fast/slow bus)
  1347. *
  1348. * 3. Instruct all devices on the bus to drop their dynamic address. This is
  1349. * particularly important when the bus was previously configured by someone
  1350. * else (for example the bootloader)
  1351. *
  1352. * 4. Disable all slave events.
  1353. *
  1354. * 5. Reserve address slots for I3C devices with init_dyn_addr. And if devices
  1355. * also have static_addr, try to pre-assign dynamic addresses requested by
  1356. * the FW with SETDASA and attach corresponding statically defined I3C
  1357. * devices to the master.
  1358. *
  1359. * 6. Do a DAA (Dynamic Address Assignment) to assign dynamic addresses to all
  1360. * remaining I3C devices
  1361. *
  1362. * Once this is done, all I3C and I2C devices should be usable.
  1363. *
  1364. * Return: a 0 in case of success, an negative error code otherwise.
  1365. */
  1366. static int i3c_master_bus_init(struct i3c_master_controller *master)
  1367. {
  1368. enum i3c_addr_slot_status status;
  1369. struct i2c_dev_boardinfo *i2cboardinfo;
  1370. struct i3c_dev_boardinfo *i3cboardinfo;
  1371. struct i2c_dev_desc *i2cdev;
  1372. int ret;
  1373. /*
  1374. * First attach all devices with static definitions provided by the
  1375. * FW.
  1376. */
  1377. list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) {
  1378. status = i3c_bus_get_addr_slot_status(&master->bus,
  1379. i2cboardinfo->base.addr);
  1380. if (status != I3C_ADDR_SLOT_FREE) {
  1381. ret = -EBUSY;
  1382. goto err_detach_devs;
  1383. }
  1384. i3c_bus_set_addr_slot_status(&master->bus,
  1385. i2cboardinfo->base.addr,
  1386. I3C_ADDR_SLOT_I2C_DEV);
  1387. i2cdev = i3c_master_alloc_i2c_dev(master, i2cboardinfo);
  1388. if (IS_ERR(i2cdev)) {
  1389. ret = PTR_ERR(i2cdev);
  1390. goto err_detach_devs;
  1391. }
  1392. ret = i3c_master_attach_i2c_dev(master, i2cdev);
  1393. if (ret) {
  1394. i3c_master_free_i2c_dev(i2cdev);
  1395. goto err_detach_devs;
  1396. }
  1397. }
  1398. /*
  1399. * Now execute the controller specific ->bus_init() routine, which
  1400. * might configure its internal logic to match the bus limitations.
  1401. */
  1402. ret = master->ops->bus_init(master);
  1403. if (ret)
  1404. goto err_detach_devs;
  1405. /*
  1406. * The master device should have been instantiated in ->bus_init(),
  1407. * complain if this was not the case.
  1408. */
  1409. if (!master->this) {
  1410. dev_err(&master->dev,
  1411. "master_set_info() was not called in ->bus_init()\n");
  1412. ret = -EINVAL;
  1413. goto err_bus_cleanup;
  1414. }
  1415. /*
  1416. * Reset all dynamic address that may have been assigned before
  1417. * (assigned by the bootloader for example).
  1418. */
  1419. ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
  1420. if (ret && ret != I3C_ERROR_M2)
  1421. goto err_bus_cleanup;
  1422. /* Disable all slave events before starting DAA. */
  1423. ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
  1424. I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
  1425. I3C_CCC_EVENT_HJ);
  1426. if (ret && ret != I3C_ERROR_M2)
  1427. goto err_bus_cleanup;
  1428. /*
  1429. * Reserve init_dyn_addr first, and then try to pre-assign dynamic
  1430. * address and retrieve device information if needed.
  1431. * In case pre-assign dynamic address fails, setting dynamic address to
  1432. * the requested init_dyn_addr is retried after DAA is done in
  1433. * i3c_master_add_i3c_dev_locked().
  1434. */
  1435. list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) {
  1436. /*
  1437. * We don't reserve a dynamic address for devices that
  1438. * don't explicitly request one.
  1439. */
  1440. if (!i3cboardinfo->init_dyn_addr)
  1441. continue;
  1442. ret = i3c_bus_get_addr_slot_status(&master->bus,
  1443. i3cboardinfo->init_dyn_addr);
  1444. if (ret != I3C_ADDR_SLOT_FREE) {
  1445. ret = -EBUSY;
  1446. goto err_rstdaa;
  1447. }
  1448. i3c_bus_set_addr_slot_status(&master->bus,
  1449. i3cboardinfo->init_dyn_addr,
  1450. I3C_ADDR_SLOT_I3C_DEV);
  1451. /*
  1452. * Only try to create/attach devices that have a static
  1453. * address. Other devices will be created/attached when
  1454. * DAA happens, and the requested dynamic address will
  1455. * be set using SETNEWDA once those devices become
  1456. * addressable.
  1457. */
  1458. if (i3cboardinfo->static_addr)
  1459. i3c_master_early_i3c_dev_add(master, i3cboardinfo);
  1460. }
  1461. ret = i3c_master_do_daa(master);
  1462. if (ret)
  1463. goto err_rstdaa;
  1464. return 0;
  1465. err_rstdaa:
  1466. i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
  1467. err_bus_cleanup:
  1468. if (master->ops->bus_cleanup)
  1469. master->ops->bus_cleanup(master);
  1470. err_detach_devs:
  1471. i3c_master_detach_free_devs(master);
  1472. return ret;
  1473. }
  1474. static void i3c_master_bus_cleanup(struct i3c_master_controller *master)
  1475. {
  1476. if (master->ops->bus_cleanup)
  1477. master->ops->bus_cleanup(master);
  1478. i3c_master_detach_free_devs(master);
  1479. }
  1480. static void i3c_master_attach_boardinfo(struct i3c_dev_desc *i3cdev)
  1481. {
  1482. struct i3c_master_controller *master = i3cdev->common.master;
  1483. struct i3c_dev_boardinfo *i3cboardinfo;
  1484. list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) {
  1485. if (i3cdev->info.pid != i3cboardinfo->pid)
  1486. continue;
  1487. i3cdev->boardinfo = i3cboardinfo;
  1488. i3cdev->info.static_addr = i3cboardinfo->static_addr;
  1489. return;
  1490. }
  1491. }
  1492. static struct i3c_dev_desc *
  1493. i3c_master_search_i3c_dev_duplicate(struct i3c_dev_desc *refdev)
  1494. {
  1495. struct i3c_master_controller *master = i3c_dev_get_master(refdev);
  1496. struct i3c_dev_desc *i3cdev;
  1497. i3c_bus_for_each_i3cdev(&master->bus, i3cdev) {
  1498. if (i3cdev != refdev && i3cdev->info.pid == refdev->info.pid)
  1499. return i3cdev;
  1500. }
  1501. return NULL;
  1502. }
  1503. /**
  1504. * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus
  1505. * @master: master used to send frames on the bus
  1506. * @addr: I3C slave dynamic address assigned to the device
  1507. *
  1508. * This function is instantiating an I3C device object and adding it to the
  1509. * I3C device list. All device information are automatically retrieved using
  1510. * standard CCC commands.
  1511. *
  1512. * The I3C device object is returned in case the master wants to attach
  1513. * private data to it using i3c_dev_set_master_data().
  1514. *
  1515. * This function must be called with the bus lock held in write mode.
  1516. *
  1517. * Return: a 0 in case of success, an negative error code otherwise.
  1518. */
  1519. int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master,
  1520. u8 addr)
  1521. {
  1522. struct i3c_device_info info = { .dyn_addr = addr };
  1523. struct i3c_dev_desc *newdev, *olddev;
  1524. u8 old_dyn_addr = addr, expected_dyn_addr;
  1525. struct i3c_ibi_setup ibireq = { };
  1526. bool enable_ibi = false;
  1527. int ret;
  1528. if (!master)
  1529. return -EINVAL;
  1530. newdev = i3c_master_alloc_i3c_dev(master, &info);
  1531. if (IS_ERR(newdev))
  1532. return PTR_ERR(newdev);
  1533. ret = i3c_master_attach_i3c_dev(master, newdev);
  1534. if (ret)
  1535. goto err_free_dev;
  1536. ret = i3c_master_retrieve_dev_info(newdev);
  1537. if (ret)
  1538. goto err_detach_dev;
  1539. i3c_master_attach_boardinfo(newdev);
  1540. olddev = i3c_master_search_i3c_dev_duplicate(newdev);
  1541. if (olddev) {
  1542. newdev->dev = olddev->dev;
  1543. if (newdev->dev)
  1544. newdev->dev->desc = newdev;
  1545. /*
  1546. * We need to restore the IBI state too, so let's save the
  1547. * IBI information and try to restore them after olddev has
  1548. * been detached+released and its IBI has been stopped and
  1549. * the associated resources have been freed.
  1550. */
  1551. mutex_lock(&olddev->ibi_lock);
  1552. if (olddev->ibi) {
  1553. ibireq.handler = olddev->ibi->handler;
  1554. ibireq.max_payload_len = olddev->ibi->max_payload_len;
  1555. ibireq.num_slots = olddev->ibi->num_slots;
  1556. if (olddev->ibi->enabled) {
  1557. enable_ibi = true;
  1558. i3c_dev_disable_ibi_locked(olddev);
  1559. }
  1560. i3c_dev_free_ibi_locked(olddev);
  1561. }
  1562. mutex_unlock(&olddev->ibi_lock);
  1563. old_dyn_addr = olddev->info.dyn_addr;
  1564. i3c_master_detach_i3c_dev(olddev);
  1565. i3c_master_free_i3c_dev(olddev);
  1566. }
  1567. ret = i3c_master_reattach_i3c_dev(newdev, old_dyn_addr);
  1568. if (ret)
  1569. goto err_detach_dev;
  1570. /*
  1571. * Depending on our previous state, the expected dynamic address might
  1572. * differ:
  1573. * - if the device already had a dynamic address assigned, let's try to
  1574. * re-apply this one
  1575. * - if the device did not have a dynamic address and the firmware
  1576. * requested a specific address, pick this one
  1577. * - in any other case, keep the address automatically assigned by the
  1578. * master
  1579. */
  1580. if (old_dyn_addr && old_dyn_addr != newdev->info.dyn_addr)
  1581. expected_dyn_addr = old_dyn_addr;
  1582. else if (newdev->boardinfo && newdev->boardinfo->init_dyn_addr)
  1583. expected_dyn_addr = newdev->boardinfo->init_dyn_addr;
  1584. else
  1585. expected_dyn_addr = newdev->info.dyn_addr;
  1586. if (newdev->info.dyn_addr != expected_dyn_addr) {
  1587. /*
  1588. * Try to apply the expected dynamic address. If it fails, keep
  1589. * the address assigned by the master.
  1590. */
  1591. ret = i3c_master_setnewda_locked(master,
  1592. newdev->info.dyn_addr,
  1593. expected_dyn_addr);
  1594. if (!ret) {
  1595. old_dyn_addr = newdev->info.dyn_addr;
  1596. newdev->info.dyn_addr = expected_dyn_addr;
  1597. i3c_master_reattach_i3c_dev(newdev, old_dyn_addr);
  1598. } else {
  1599. dev_err(&master->dev,
  1600. "Failed to assign reserved/old address to device %d%llx",
  1601. master->bus.id, newdev->info.pid);
  1602. }
  1603. }
  1604. /*
  1605. * Now is time to try to restore the IBI setup. If we're lucky,
  1606. * everything works as before, otherwise, all we can do is complain.
  1607. * FIXME: maybe we should add callback to inform the driver that it
  1608. * should request the IBI again instead of trying to hide that from
  1609. * him.
  1610. */
  1611. if (ibireq.handler) {
  1612. mutex_lock(&newdev->ibi_lock);
  1613. ret = i3c_dev_request_ibi_locked(newdev, &ibireq);
  1614. if (ret) {
  1615. dev_err(&master->dev,
  1616. "Failed to request IBI on device %d-%llx",
  1617. master->bus.id, newdev->info.pid);
  1618. } else if (enable_ibi) {
  1619. ret = i3c_dev_enable_ibi_locked(newdev);
  1620. if (ret)
  1621. dev_err(&master->dev,
  1622. "Failed to re-enable IBI on device %d-%llx",
  1623. master->bus.id, newdev->info.pid);
  1624. }
  1625. mutex_unlock(&newdev->ibi_lock);
  1626. }
  1627. return 0;
  1628. err_detach_dev:
  1629. if (newdev->dev && newdev->dev->desc)
  1630. newdev->dev->desc = NULL;
  1631. i3c_master_detach_i3c_dev(newdev);
  1632. err_free_dev:
  1633. i3c_master_free_i3c_dev(newdev);
  1634. return ret;
  1635. }
  1636. EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked);
  1637. #define OF_I3C_REG1_IS_I2C_DEV BIT(31)
  1638. static int
  1639. of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
  1640. struct device_node *node, u32 *reg)
  1641. {
  1642. struct i2c_dev_boardinfo *boardinfo;
  1643. struct device *dev = &master->dev;
  1644. int ret;
  1645. boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL);
  1646. if (!boardinfo)
  1647. return -ENOMEM;
  1648. ret = of_i2c_get_board_info(dev, node, &boardinfo->base);
  1649. if (ret)
  1650. return ret;
  1651. /*
  1652. * The I3C Specification does not clearly say I2C devices with 10-bit
  1653. * address are supported. These devices can't be passed properly through
  1654. * DEFSLVS command.
  1655. */
  1656. if (boardinfo->base.flags & I2C_CLIENT_TEN) {
  1657. dev_err(dev, "I2C device with 10 bit address not supported.");
  1658. return -ENOTSUPP;
  1659. }
  1660. /* LVR is encoded in reg[2]. */
  1661. boardinfo->lvr = reg[2];
  1662. list_add_tail(&boardinfo->node, &master->boardinfo.i2c);
  1663. of_node_get(node);
  1664. return 0;
  1665. }
  1666. static int
  1667. of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
  1668. struct device_node *node, u32 *reg)
  1669. {
  1670. struct i3c_dev_boardinfo *boardinfo;
  1671. struct device *dev = &master->dev;
  1672. enum i3c_addr_slot_status addrstatus;
  1673. u32 init_dyn_addr = 0;
  1674. boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL);
  1675. if (!boardinfo)
  1676. return -ENOMEM;
  1677. if (reg[0]) {
  1678. if (reg[0] > I3C_MAX_ADDR)
  1679. return -EINVAL;
  1680. addrstatus = i3c_bus_get_addr_slot_status(&master->bus,
  1681. reg[0]);
  1682. if (addrstatus != I3C_ADDR_SLOT_FREE)
  1683. return -EINVAL;
  1684. }
  1685. boardinfo->static_addr = reg[0];
  1686. if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) {
  1687. if (init_dyn_addr > I3C_MAX_ADDR)
  1688. return -EINVAL;
  1689. addrstatus = i3c_bus_get_addr_slot_status(&master->bus,
  1690. init_dyn_addr);
  1691. if (addrstatus != I3C_ADDR_SLOT_FREE)
  1692. return -EINVAL;
  1693. }
  1694. boardinfo->pid = ((u64)reg[1] << 32) | reg[2];
  1695. if ((boardinfo->pid & GENMASK_ULL(63, 48)) ||
  1696. I3C_PID_RND_LOWER_32BITS(boardinfo->pid))
  1697. return -EINVAL;
  1698. boardinfo->init_dyn_addr = init_dyn_addr;
  1699. boardinfo->of_node = of_node_get(node);
  1700. list_add_tail(&boardinfo->node, &master->boardinfo.i3c);
  1701. return 0;
  1702. }
  1703. static int of_i3c_master_add_dev(struct i3c_master_controller *master,
  1704. struct device_node *node)
  1705. {
  1706. u32 reg[3];
  1707. int ret;
  1708. if (!master || !node)
  1709. return -EINVAL;
  1710. ret = of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg));
  1711. if (ret)
  1712. return ret;
  1713. /*
  1714. * The manufacturer ID can't be 0. If reg[1] == 0 that means we're
  1715. * dealing with an I2C device.
  1716. */
  1717. if (!reg[1])
  1718. ret = of_i3c_master_add_i2c_boardinfo(master, node, reg);
  1719. else
  1720. ret = of_i3c_master_add_i3c_boardinfo(master, node, reg);
  1721. return ret;
  1722. }
  1723. static int of_populate_i3c_bus(struct i3c_master_controller *master)
  1724. {
  1725. struct device *dev = &master->dev;
  1726. struct device_node *i3cbus_np = dev->of_node;
  1727. struct device_node *node;
  1728. int ret;
  1729. u32 val;
  1730. if (!i3cbus_np)
  1731. return 0;
  1732. for_each_available_child_of_node(i3cbus_np, node) {
  1733. ret = of_i3c_master_add_dev(master, node);
  1734. if (ret) {
  1735. of_node_put(node);
  1736. return ret;
  1737. }
  1738. }
  1739. /*
  1740. * The user might want to limit I2C and I3C speed in case some devices
  1741. * on the bus are not supporting typical rates, or if the bus topology
  1742. * prevents it from using max possible rate.
  1743. */
  1744. if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val))
  1745. master->bus.scl_rate.i2c = val;
  1746. if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val))
  1747. master->bus.scl_rate.i3c = val;
  1748. return 0;
  1749. }
  1750. static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
  1751. struct i2c_msg *xfers, int nxfers)
  1752. {
  1753. struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
  1754. struct i2c_dev_desc *dev;
  1755. int i, ret;
  1756. u16 addr;
  1757. if (!xfers || !master || nxfers <= 0)
  1758. return -EINVAL;
  1759. if (!master->ops->i2c_xfers)
  1760. return -ENOTSUPP;
  1761. /* Doing transfers to different devices is not supported. */
  1762. addr = xfers[0].addr;
  1763. for (i = 1; i < nxfers; i++) {
  1764. if (addr != xfers[i].addr)
  1765. return -ENOTSUPP;
  1766. }
  1767. i3c_bus_normaluse_lock(&master->bus);
  1768. dev = i3c_master_find_i2c_dev_by_addr(master, addr);
  1769. if (!dev)
  1770. ret = -ENOENT;
  1771. else
  1772. ret = master->ops->i2c_xfers(dev, xfers, nxfers);
  1773. i3c_bus_normaluse_unlock(&master->bus);
  1774. return ret ? ret : nxfers;
  1775. }
  1776. static u32 i3c_master_i2c_funcs(struct i2c_adapter *adapter)
  1777. {
  1778. return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
  1779. }
  1780. static const struct i2c_algorithm i3c_master_i2c_algo = {
  1781. .master_xfer = i3c_master_i2c_adapter_xfer,
  1782. .functionality = i3c_master_i2c_funcs,
  1783. };
  1784. static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
  1785. {
  1786. struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master);
  1787. struct i2c_dev_desc *i2cdev;
  1788. int ret;
  1789. adap->dev.parent = master->dev.parent;
  1790. adap->owner = master->dev.parent->driver->owner;
  1791. adap->algo = &i3c_master_i2c_algo;
  1792. strncpy(adap->name, dev_name(master->dev.parent), sizeof(adap->name));
  1793. /* FIXME: Should we allow i3c masters to override these values? */
  1794. adap->timeout = 1000;
  1795. adap->retries = 3;
  1796. ret = i2c_add_adapter(adap);
  1797. if (ret)
  1798. return ret;
  1799. /*
  1800. * We silently ignore failures here. The bus should keep working
  1801. * correctly even if one or more i2c devices are not registered.
  1802. */
  1803. i3c_bus_for_each_i2cdev(&master->bus, i2cdev)
  1804. i2cdev->dev = i2c_new_client_device(adap, &i2cdev->boardinfo->base);
  1805. return 0;
  1806. }
  1807. static void i3c_master_i2c_adapter_cleanup(struct i3c_master_controller *master)
  1808. {
  1809. struct i2c_dev_desc *i2cdev;
  1810. i2c_del_adapter(&master->i2c);
  1811. i3c_bus_for_each_i2cdev(&master->bus, i2cdev)
  1812. i2cdev->dev = NULL;
  1813. }
  1814. static void i3c_master_unregister_i3c_devs(struct i3c_master_controller *master)
  1815. {
  1816. struct i3c_dev_desc *i3cdev;
  1817. i3c_bus_for_each_i3cdev(&master->bus, i3cdev) {
  1818. if (!i3cdev->dev)
  1819. continue;
  1820. i3cdev->dev->desc = NULL;
  1821. if (device_is_registered(&i3cdev->dev->dev))
  1822. device_unregister(&i3cdev->dev->dev);
  1823. else
  1824. put_device(&i3cdev->dev->dev);
  1825. i3cdev->dev = NULL;
  1826. }
  1827. }
  1828. /**
  1829. * i3c_master_queue_ibi() - Queue an IBI
  1830. * @dev: the device this IBI is coming from
  1831. * @slot: the IBI slot used to store the payload
  1832. *
  1833. * Queue an IBI to the controller workqueue. The IBI handler attached to
  1834. * the dev will be called from a workqueue context.
  1835. */
  1836. void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot)
  1837. {
  1838. atomic_inc(&dev->ibi->pending_ibis);
  1839. queue_work(dev->common.master->wq, &slot->work);
  1840. }
  1841. EXPORT_SYMBOL_GPL(i3c_master_queue_ibi);
  1842. static void i3c_master_handle_ibi(struct work_struct *work)
  1843. {
  1844. struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot,
  1845. work);
  1846. struct i3c_dev_desc *dev = slot->dev;
  1847. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  1848. struct i3c_ibi_payload payload;
  1849. payload.data = slot->data;
  1850. payload.len = slot->len;
  1851. if (dev->dev)
  1852. dev->ibi->handler(dev->dev, &payload);
  1853. master->ops->recycle_ibi_slot(dev, slot);
  1854. if (atomic_dec_and_test(&dev->ibi->pending_ibis))
  1855. complete(&dev->ibi->all_ibis_handled);
  1856. }
  1857. static void i3c_master_init_ibi_slot(struct i3c_dev_desc *dev,
  1858. struct i3c_ibi_slot *slot)
  1859. {
  1860. slot->dev = dev;
  1861. INIT_WORK(&slot->work, i3c_master_handle_ibi);
  1862. }
  1863. struct i3c_generic_ibi_slot {
  1864. struct list_head node;
  1865. struct i3c_ibi_slot base;
  1866. };
  1867. struct i3c_generic_ibi_pool {
  1868. spinlock_t lock;
  1869. unsigned int num_slots;
  1870. struct i3c_generic_ibi_slot *slots;
  1871. void *payload_buf;
  1872. struct list_head free_slots;
  1873. struct list_head pending;
  1874. };
  1875. /**
  1876. * i3c_generic_ibi_free_pool() - Free a generic IBI pool
  1877. * @pool: the IBI pool to free
  1878. *
  1879. * Free all IBI slots allated by a generic IBI pool.
  1880. */
  1881. void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool)
  1882. {
  1883. struct i3c_generic_ibi_slot *slot;
  1884. unsigned int nslots = 0;
  1885. while (!list_empty(&pool->free_slots)) {
  1886. slot = list_first_entry(&pool->free_slots,
  1887. struct i3c_generic_ibi_slot, node);
  1888. list_del(&slot->node);
  1889. nslots++;
  1890. }
  1891. /*
  1892. * If the number of freed slots is not equal to the number of allocated
  1893. * slots we have a leak somewhere.
  1894. */
  1895. WARN_ON(nslots != pool->num_slots);
  1896. kfree(pool->payload_buf);
  1897. kfree(pool->slots);
  1898. kfree(pool);
  1899. }
  1900. EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool);
  1901. /**
  1902. * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool
  1903. * @dev: the device this pool will be used for
  1904. * @req: IBI setup request describing what the device driver expects
  1905. *
  1906. * Create a generic IBI pool based on the information provided in @req.
  1907. *
  1908. * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise.
  1909. */
  1910. struct i3c_generic_ibi_pool *
  1911. i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev,
  1912. const struct i3c_ibi_setup *req)
  1913. {
  1914. struct i3c_generic_ibi_pool *pool;
  1915. struct i3c_generic_ibi_slot *slot;
  1916. unsigned int i;
  1917. int ret;
  1918. pool = kzalloc(sizeof(*pool), GFP_KERNEL);
  1919. if (!pool)
  1920. return ERR_PTR(-ENOMEM);
  1921. spin_lock_init(&pool->lock);
  1922. INIT_LIST_HEAD(&pool->free_slots);
  1923. INIT_LIST_HEAD(&pool->pending);
  1924. pool->slots = kcalloc(req->num_slots, sizeof(*slot), GFP_KERNEL);
  1925. if (!pool->slots) {
  1926. ret = -ENOMEM;
  1927. goto err_free_pool;
  1928. }
  1929. if (req->max_payload_len) {
  1930. pool->payload_buf = kcalloc(req->num_slots,
  1931. req->max_payload_len, GFP_KERNEL);
  1932. if (!pool->payload_buf) {
  1933. ret = -ENOMEM;
  1934. goto err_free_pool;
  1935. }
  1936. }
  1937. for (i = 0; i < req->num_slots; i++) {
  1938. slot = &pool->slots[i];
  1939. i3c_master_init_ibi_slot(dev, &slot->base);
  1940. if (req->max_payload_len)
  1941. slot->base.data = pool->payload_buf +
  1942. (i * req->max_payload_len);
  1943. list_add_tail(&slot->node, &pool->free_slots);
  1944. pool->num_slots++;
  1945. }
  1946. return pool;
  1947. err_free_pool:
  1948. i3c_generic_ibi_free_pool(pool);
  1949. return ERR_PTR(ret);
  1950. }
  1951. EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool);
  1952. /**
  1953. * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool
  1954. * @pool: the pool to query an IBI slot on
  1955. *
  1956. * Search for a free slot in a generic IBI pool.
  1957. * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot()
  1958. * when it's no longer needed.
  1959. *
  1960. * Return: a pointer to a free slot, or NULL if there's no free slot available.
  1961. */
  1962. struct i3c_ibi_slot *
  1963. i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool)
  1964. {
  1965. struct i3c_generic_ibi_slot *slot;
  1966. unsigned long flags;
  1967. spin_lock_irqsave(&pool->lock, flags);
  1968. slot = list_first_entry_or_null(&pool->free_slots,
  1969. struct i3c_generic_ibi_slot, node);
  1970. if (slot)
  1971. list_del(&slot->node);
  1972. spin_unlock_irqrestore(&pool->lock, flags);
  1973. return slot ? &slot->base : NULL;
  1974. }
  1975. EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot);
  1976. /**
  1977. * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool
  1978. * @pool: the pool to return the IBI slot to
  1979. * @s: IBI slot to recycle
  1980. *
  1981. * Add an IBI slot back to its generic IBI pool. Should be called from the
  1982. * master driver struct_master_controller_ops->recycle_ibi() method.
  1983. */
  1984. void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
  1985. struct i3c_ibi_slot *s)
  1986. {
  1987. struct i3c_generic_ibi_slot *slot;
  1988. unsigned long flags;
  1989. if (!s)
  1990. return;
  1991. slot = container_of(s, struct i3c_generic_ibi_slot, base);
  1992. spin_lock_irqsave(&pool->lock, flags);
  1993. list_add_tail(&slot->node, &pool->free_slots);
  1994. spin_unlock_irqrestore(&pool->lock, flags);
  1995. }
  1996. EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot);
  1997. static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops)
  1998. {
  1999. if (!ops || !ops->bus_init || !ops->priv_xfers ||
  2000. !ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers)
  2001. return -EINVAL;
  2002. if (ops->request_ibi &&
  2003. (!ops->enable_ibi || !ops->disable_ibi || !ops->free_ibi ||
  2004. !ops->recycle_ibi_slot))
  2005. return -EINVAL;
  2006. return 0;
  2007. }
  2008. /**
  2009. * i3c_master_register() - register an I3C master
  2010. * @master: master used to send frames on the bus
  2011. * @parent: the parent device (the one that provides this I3C master
  2012. * controller)
  2013. * @ops: the master controller operations
  2014. * @secondary: true if you are registering a secondary master. Will return
  2015. * -ENOTSUPP if set to true since secondary masters are not yet
  2016. * supported
  2017. *
  2018. * This function takes care of everything for you:
  2019. *
  2020. * - creates and initializes the I3C bus
  2021. * - populates the bus with static I2C devs if @parent->of_node is not
  2022. * NULL
  2023. * - registers all I3C devices added by the controller during bus
  2024. * initialization
  2025. * - registers the I2C adapter and all I2C devices
  2026. *
  2027. * Return: 0 in case of success, a negative error code otherwise.
  2028. */
  2029. int i3c_master_register(struct i3c_master_controller *master,
  2030. struct device *parent,
  2031. const struct i3c_master_controller_ops *ops,
  2032. bool secondary)
  2033. {
  2034. unsigned long i2c_scl_rate = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
  2035. struct i3c_bus *i3cbus = i3c_master_get_bus(master);
  2036. enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
  2037. struct i2c_dev_boardinfo *i2cbi;
  2038. int ret;
  2039. /* We do not support secondary masters yet. */
  2040. if (secondary)
  2041. return -ENOTSUPP;
  2042. ret = i3c_master_check_ops(ops);
  2043. if (ret)
  2044. return ret;
  2045. master->dev.parent = parent;
  2046. master->dev.of_node = of_node_get(parent->of_node);
  2047. master->dev.bus = &i3c_bus_type;
  2048. master->dev.type = &i3c_masterdev_type;
  2049. master->dev.release = i3c_masterdev_release;
  2050. master->ops = ops;
  2051. master->secondary = secondary;
  2052. INIT_LIST_HEAD(&master->boardinfo.i2c);
  2053. INIT_LIST_HEAD(&master->boardinfo.i3c);
  2054. ret = i3c_bus_init(i3cbus);
  2055. if (ret)
  2056. return ret;
  2057. device_initialize(&master->dev);
  2058. dev_set_name(&master->dev, "i3c-%d", i3cbus->id);
  2059. ret = of_populate_i3c_bus(master);
  2060. if (ret)
  2061. goto err_put_dev;
  2062. list_for_each_entry(i2cbi, &master->boardinfo.i2c, node) {
  2063. switch (i2cbi->lvr & I3C_LVR_I2C_INDEX_MASK) {
  2064. case I3C_LVR_I2C_INDEX(0):
  2065. if (mode < I3C_BUS_MODE_MIXED_FAST)
  2066. mode = I3C_BUS_MODE_MIXED_FAST;
  2067. break;
  2068. case I3C_LVR_I2C_INDEX(1):
  2069. if (mode < I3C_BUS_MODE_MIXED_LIMITED)
  2070. mode = I3C_BUS_MODE_MIXED_LIMITED;
  2071. break;
  2072. case I3C_LVR_I2C_INDEX(2):
  2073. if (mode < I3C_BUS_MODE_MIXED_SLOW)
  2074. mode = I3C_BUS_MODE_MIXED_SLOW;
  2075. break;
  2076. default:
  2077. ret = -EINVAL;
  2078. goto err_put_dev;
  2079. }
  2080. if (i2cbi->lvr & I3C_LVR_I2C_FM_MODE)
  2081. i2c_scl_rate = I3C_BUS_I2C_FM_SCL_RATE;
  2082. }
  2083. ret = i3c_bus_set_mode(i3cbus, mode, i2c_scl_rate);
  2084. if (ret)
  2085. goto err_put_dev;
  2086. master->wq = alloc_workqueue("%s", 0, 0, dev_name(parent));
  2087. if (!master->wq) {
  2088. ret = -ENOMEM;
  2089. goto err_put_dev;
  2090. }
  2091. ret = i3c_master_bus_init(master);
  2092. if (ret)
  2093. goto err_put_dev;
  2094. ret = device_add(&master->dev);
  2095. if (ret)
  2096. goto err_cleanup_bus;
  2097. /*
  2098. * Expose our I3C bus as an I2C adapter so that I2C devices are exposed
  2099. * through the I2C subsystem.
  2100. */
  2101. ret = i3c_master_i2c_adapter_init(master);
  2102. if (ret)
  2103. goto err_del_dev;
  2104. /*
  2105. * We're done initializing the bus and the controller, we can now
  2106. * register I3C devices discovered during the initial DAA.
  2107. */
  2108. master->init_done = true;
  2109. i3c_bus_normaluse_lock(&master->bus);
  2110. i3c_master_register_new_i3c_devs(master);
  2111. i3c_bus_normaluse_unlock(&master->bus);
  2112. return 0;
  2113. err_del_dev:
  2114. device_del(&master->dev);
  2115. err_cleanup_bus:
  2116. i3c_master_bus_cleanup(master);
  2117. err_put_dev:
  2118. put_device(&master->dev);
  2119. return ret;
  2120. }
  2121. EXPORT_SYMBOL_GPL(i3c_master_register);
  2122. /**
  2123. * i3c_master_unregister() - unregister an I3C master
  2124. * @master: master used to send frames on the bus
  2125. *
  2126. * Basically undo everything done in i3c_master_register().
  2127. *
  2128. * Return: 0 in case of success, a negative error code otherwise.
  2129. */
  2130. int i3c_master_unregister(struct i3c_master_controller *master)
  2131. {
  2132. i3c_master_i2c_adapter_cleanup(master);
  2133. i3c_master_unregister_i3c_devs(master);
  2134. i3c_master_bus_cleanup(master);
  2135. device_unregister(&master->dev);
  2136. return 0;
  2137. }
  2138. EXPORT_SYMBOL_GPL(i3c_master_unregister);
  2139. int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev,
  2140. struct i3c_priv_xfer *xfers,
  2141. int nxfers)
  2142. {
  2143. struct i3c_master_controller *master;
  2144. if (!dev)
  2145. return -ENOENT;
  2146. master = i3c_dev_get_master(dev);
  2147. if (!master || !xfers)
  2148. return -EINVAL;
  2149. if (!master->ops->priv_xfers)
  2150. return -ENOTSUPP;
  2151. return master->ops->priv_xfers(dev, xfers, nxfers);
  2152. }
  2153. int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev)
  2154. {
  2155. struct i3c_master_controller *master;
  2156. int ret;
  2157. if (!dev->ibi)
  2158. return -EINVAL;
  2159. master = i3c_dev_get_master(dev);
  2160. ret = master->ops->disable_ibi(dev);
  2161. if (ret)
  2162. return ret;
  2163. reinit_completion(&dev->ibi->all_ibis_handled);
  2164. if (atomic_read(&dev->ibi->pending_ibis))
  2165. wait_for_completion(&dev->ibi->all_ibis_handled);
  2166. dev->ibi->enabled = false;
  2167. return 0;
  2168. }
  2169. int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev)
  2170. {
  2171. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  2172. int ret;
  2173. if (!dev->ibi)
  2174. return -EINVAL;
  2175. ret = master->ops->enable_ibi(dev);
  2176. if (!ret)
  2177. dev->ibi->enabled = true;
  2178. return ret;
  2179. }
  2180. int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
  2181. const struct i3c_ibi_setup *req)
  2182. {
  2183. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  2184. struct i3c_device_ibi_info *ibi;
  2185. int ret;
  2186. if (!master->ops->request_ibi)
  2187. return -ENOTSUPP;
  2188. if (dev->ibi)
  2189. return -EBUSY;
  2190. ibi = kzalloc(sizeof(*ibi), GFP_KERNEL);
  2191. if (!ibi)
  2192. return -ENOMEM;
  2193. atomic_set(&ibi->pending_ibis, 0);
  2194. init_completion(&ibi->all_ibis_handled);
  2195. ibi->handler = req->handler;
  2196. ibi->max_payload_len = req->max_payload_len;
  2197. ibi->num_slots = req->num_slots;
  2198. dev->ibi = ibi;
  2199. ret = master->ops->request_ibi(dev, req);
  2200. if (ret) {
  2201. kfree(ibi);
  2202. dev->ibi = NULL;
  2203. }
  2204. return ret;
  2205. }
  2206. void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev)
  2207. {
  2208. struct i3c_master_controller *master = i3c_dev_get_master(dev);
  2209. if (!dev->ibi)
  2210. return;
  2211. if (WARN_ON(dev->ibi->enabled))
  2212. WARN_ON(i3c_dev_disable_ibi_locked(dev));
  2213. master->ops->free_ibi(dev);
  2214. kfree(dev->ibi);
  2215. dev->ibi = NULL;
  2216. }
  2217. static int __init i3c_init(void)
  2218. {
  2219. return bus_register(&i3c_bus_type);
  2220. }
  2221. subsys_initcall(i3c_init);
  2222. static void __exit i3c_exit(void)
  2223. {
  2224. idr_destroy(&i3c_bus_idr);
  2225. bus_unregister(&i3c_bus_type);
  2226. }
  2227. module_exit(i3c_exit);
  2228. MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
  2229. MODULE_DESCRIPTION("I3C core");
  2230. MODULE_LICENSE("GPL v2");