xgene-hwmon.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * APM X-Gene SoC Hardware Monitoring Driver
  4. *
  5. * Copyright (c) 2016, Applied Micro Circuits Corporation
  6. * Author: Loc Ho <lho@apm.com>
  7. * Hoan Tran <hotran@apm.com>
  8. *
  9. * This driver provides the following features:
  10. * - Retrieve CPU total power (uW)
  11. * - Retrieve IO total power (uW)
  12. * - Retrieve SoC temperature (milli-degree C) and alarm
  13. */
  14. #include <linux/acpi.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/hwmon.h>
  17. #include <linux/hwmon-sysfs.h>
  18. #include <linux/io.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kfifo.h>
  21. #include <linux/mailbox_controller.h>
  22. #include <linux/mailbox_client.h>
  23. #include <linux/module.h>
  24. #include <linux/of.h>
  25. #include <linux/platform_device.h>
  26. #include <acpi/pcc.h>
  27. /* SLIMpro message defines */
  28. #define MSG_TYPE_DBG 0
  29. #define MSG_TYPE_ERR 7
  30. #define MSG_TYPE_PWRMGMT 9
  31. #define MSG_TYPE(v) (((v) & 0xF0000000) >> 28)
  32. #define MSG_TYPE_SET(v) (((v) << 28) & 0xF0000000)
  33. #define MSG_SUBTYPE(v) (((v) & 0x0F000000) >> 24)
  34. #define MSG_SUBTYPE_SET(v) (((v) << 24) & 0x0F000000)
  35. #define DBG_SUBTYPE_SENSOR_READ 4
  36. #define SENSOR_RD_MSG 0x04FFE902
  37. #define SENSOR_RD_EN_ADDR(a) ((a) & 0x000FFFFF)
  38. #define PMD_PWR_REG 0x20
  39. #define PMD_PWR_MW_REG 0x26
  40. #define SOC_PWR_REG 0x21
  41. #define SOC_PWR_MW_REG 0x27
  42. #define SOC_TEMP_REG 0x10
  43. #define TEMP_NEGATIVE_BIT 8
  44. #define SENSOR_INVALID_DATA BIT(15)
  45. #define PWRMGMT_SUBTYPE_TPC 1
  46. #define TPC_ALARM 2
  47. #define TPC_GET_ALARM 3
  48. #define TPC_CMD(v) (((v) & 0x00FF0000) >> 16)
  49. #define TPC_CMD_SET(v) (((v) << 16) & 0x00FF0000)
  50. #define TPC_EN_MSG(hndl, cmd, type) \
  51. (MSG_TYPE_SET(MSG_TYPE_PWRMGMT) | \
  52. MSG_SUBTYPE_SET(hndl) | TPC_CMD_SET(cmd) | type)
  53. /* PCC defines */
  54. #define PCC_SIGNATURE_MASK 0x50424300
  55. #define PCCC_GENERATE_DB_INT BIT(15)
  56. #define PCCS_CMD_COMPLETE BIT(0)
  57. #define PCCS_SCI_DOORBEL BIT(1)
  58. #define PCCS_PLATFORM_NOTIFICATION BIT(3)
  59. /*
  60. * Arbitrary retries in case the remote processor is slow to respond
  61. * to PCC commands
  62. */
  63. #define PCC_NUM_RETRIES 500
  64. #define ASYNC_MSG_FIFO_SIZE 16
  65. #define MBOX_OP_TIMEOUTMS 1000
  66. #define WATT_TO_mWATT(x) ((x) * 1000)
  67. #define mWATT_TO_uWATT(x) ((x) * 1000)
  68. #define CELSIUS_TO_mCELSIUS(x) ((x) * 1000)
  69. #define to_xgene_hwmon_dev(cl) \
  70. container_of(cl, struct xgene_hwmon_dev, mbox_client)
  71. enum xgene_hwmon_version {
  72. XGENE_HWMON_V1 = 0,
  73. XGENE_HWMON_V2 = 1,
  74. };
  75. struct slimpro_resp_msg {
  76. u32 msg;
  77. u32 param1;
  78. u32 param2;
  79. } __packed;
  80. struct xgene_hwmon_dev {
  81. struct device *dev;
  82. struct mbox_chan *mbox_chan;
  83. struct mbox_client mbox_client;
  84. int mbox_idx;
  85. spinlock_t kfifo_lock;
  86. struct mutex rd_mutex;
  87. struct completion rd_complete;
  88. int resp_pending;
  89. struct slimpro_resp_msg sync_msg;
  90. struct work_struct workq;
  91. struct kfifo_rec_ptr_1 async_msg_fifo;
  92. struct device *hwmon_dev;
  93. bool temp_critical_alarm;
  94. phys_addr_t comm_base_addr;
  95. void *pcc_comm_addr;
  96. u64 usecs_lat;
  97. };
  98. /*
  99. * This function tests and clears a bitmask then returns its old value
  100. */
  101. static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask)
  102. {
  103. u16 ret, val;
  104. val = le16_to_cpu(READ_ONCE(*addr));
  105. ret = val & mask;
  106. val &= ~mask;
  107. WRITE_ONCE(*addr, cpu_to_le16(val));
  108. return ret;
  109. }
  110. static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev *ctx, u32 *msg)
  111. {
  112. struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
  113. u32 *ptr = (void *)(generic_comm_base + 1);
  114. int rc, i;
  115. u16 val;
  116. mutex_lock(&ctx->rd_mutex);
  117. init_completion(&ctx->rd_complete);
  118. ctx->resp_pending = true;
  119. /* Write signature for subspace */
  120. WRITE_ONCE(generic_comm_base->signature,
  121. cpu_to_le32(PCC_SIGNATURE_MASK | ctx->mbox_idx));
  122. /* Write to the shared command region */
  123. WRITE_ONCE(generic_comm_base->command,
  124. cpu_to_le16(MSG_TYPE(msg[0]) | PCCC_GENERATE_DB_INT));
  125. /* Flip CMD COMPLETE bit */
  126. val = le16_to_cpu(READ_ONCE(generic_comm_base->status));
  127. val &= ~PCCS_CMD_COMPLETE;
  128. WRITE_ONCE(generic_comm_base->status, cpu_to_le16(val));
  129. /* Copy the message to the PCC comm space */
  130. for (i = 0; i < sizeof(struct slimpro_resp_msg) / 4; i++)
  131. WRITE_ONCE(ptr[i], cpu_to_le32(msg[i]));
  132. /* Ring the doorbell */
  133. rc = mbox_send_message(ctx->mbox_chan, msg);
  134. if (rc < 0) {
  135. dev_err(ctx->dev, "Mailbox send error %d\n", rc);
  136. goto err;
  137. }
  138. if (!wait_for_completion_timeout(&ctx->rd_complete,
  139. usecs_to_jiffies(ctx->usecs_lat))) {
  140. dev_err(ctx->dev, "Mailbox operation timed out\n");
  141. rc = -ETIMEDOUT;
  142. goto err;
  143. }
  144. /* Check for error message */
  145. if (MSG_TYPE(ctx->sync_msg.msg) == MSG_TYPE_ERR) {
  146. rc = -EINVAL;
  147. goto err;
  148. }
  149. msg[0] = ctx->sync_msg.msg;
  150. msg[1] = ctx->sync_msg.param1;
  151. msg[2] = ctx->sync_msg.param2;
  152. err:
  153. mbox_chan_txdone(ctx->mbox_chan, 0);
  154. ctx->resp_pending = false;
  155. mutex_unlock(&ctx->rd_mutex);
  156. return rc;
  157. }
  158. static int xgene_hwmon_rd(struct xgene_hwmon_dev *ctx, u32 *msg)
  159. {
  160. int rc;
  161. mutex_lock(&ctx->rd_mutex);
  162. init_completion(&ctx->rd_complete);
  163. ctx->resp_pending = true;
  164. rc = mbox_send_message(ctx->mbox_chan, msg);
  165. if (rc < 0) {
  166. dev_err(ctx->dev, "Mailbox send error %d\n", rc);
  167. goto err;
  168. }
  169. if (!wait_for_completion_timeout(&ctx->rd_complete,
  170. msecs_to_jiffies(MBOX_OP_TIMEOUTMS))) {
  171. dev_err(ctx->dev, "Mailbox operation timed out\n");
  172. rc = -ETIMEDOUT;
  173. goto err;
  174. }
  175. /* Check for error message */
  176. if (MSG_TYPE(ctx->sync_msg.msg) == MSG_TYPE_ERR) {
  177. rc = -EINVAL;
  178. goto err;
  179. }
  180. msg[0] = ctx->sync_msg.msg;
  181. msg[1] = ctx->sync_msg.param1;
  182. msg[2] = ctx->sync_msg.param2;
  183. err:
  184. ctx->resp_pending = false;
  185. mutex_unlock(&ctx->rd_mutex);
  186. return rc;
  187. }
  188. static int xgene_hwmon_reg_map_rd(struct xgene_hwmon_dev *ctx, u32 addr,
  189. u32 *data)
  190. {
  191. u32 msg[3];
  192. int rc;
  193. msg[0] = SENSOR_RD_MSG;
  194. msg[1] = SENSOR_RD_EN_ADDR(addr);
  195. msg[2] = 0;
  196. if (acpi_disabled)
  197. rc = xgene_hwmon_rd(ctx, msg);
  198. else
  199. rc = xgene_hwmon_pcc_rd(ctx, msg);
  200. if (rc < 0)
  201. return rc;
  202. /*
  203. * Check if sensor data is valid.
  204. */
  205. if (msg[1] & SENSOR_INVALID_DATA)
  206. return -ENODATA;
  207. *data = msg[1];
  208. return rc;
  209. }
  210. static int xgene_hwmon_get_notification_msg(struct xgene_hwmon_dev *ctx,
  211. u32 *amsg)
  212. {
  213. u32 msg[3];
  214. int rc;
  215. msg[0] = TPC_EN_MSG(PWRMGMT_SUBTYPE_TPC, TPC_GET_ALARM, 0);
  216. msg[1] = 0;
  217. msg[2] = 0;
  218. rc = xgene_hwmon_pcc_rd(ctx, msg);
  219. if (rc < 0)
  220. return rc;
  221. amsg[0] = msg[0];
  222. amsg[1] = msg[1];
  223. amsg[2] = msg[2];
  224. return rc;
  225. }
  226. static int xgene_hwmon_get_cpu_pwr(struct xgene_hwmon_dev *ctx, u32 *val)
  227. {
  228. u32 watt, mwatt;
  229. int rc;
  230. rc = xgene_hwmon_reg_map_rd(ctx, PMD_PWR_REG, &watt);
  231. if (rc < 0)
  232. return rc;
  233. rc = xgene_hwmon_reg_map_rd(ctx, PMD_PWR_MW_REG, &mwatt);
  234. if (rc < 0)
  235. return rc;
  236. *val = WATT_TO_mWATT(watt) + mwatt;
  237. return 0;
  238. }
  239. static int xgene_hwmon_get_io_pwr(struct xgene_hwmon_dev *ctx, u32 *val)
  240. {
  241. u32 watt, mwatt;
  242. int rc;
  243. rc = xgene_hwmon_reg_map_rd(ctx, SOC_PWR_REG, &watt);
  244. if (rc < 0)
  245. return rc;
  246. rc = xgene_hwmon_reg_map_rd(ctx, SOC_PWR_MW_REG, &mwatt);
  247. if (rc < 0)
  248. return rc;
  249. *val = WATT_TO_mWATT(watt) + mwatt;
  250. return 0;
  251. }
  252. static int xgene_hwmon_get_temp(struct xgene_hwmon_dev *ctx, u32 *val)
  253. {
  254. return xgene_hwmon_reg_map_rd(ctx, SOC_TEMP_REG, val);
  255. }
  256. /*
  257. * Sensor temperature/power functions
  258. */
  259. static ssize_t temp1_input_show(struct device *dev,
  260. struct device_attribute *attr,
  261. char *buf)
  262. {
  263. struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
  264. int rc, temp;
  265. u32 val;
  266. rc = xgene_hwmon_get_temp(ctx, &val);
  267. if (rc < 0)
  268. return rc;
  269. temp = sign_extend32(val, TEMP_NEGATIVE_BIT);
  270. return snprintf(buf, PAGE_SIZE, "%d\n", CELSIUS_TO_mCELSIUS(temp));
  271. }
  272. static ssize_t temp1_label_show(struct device *dev,
  273. struct device_attribute *attr,
  274. char *buf)
  275. {
  276. return snprintf(buf, PAGE_SIZE, "SoC Temperature\n");
  277. }
  278. static ssize_t temp1_critical_alarm_show(struct device *dev,
  279. struct device_attribute *devattr,
  280. char *buf)
  281. {
  282. struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
  283. return snprintf(buf, PAGE_SIZE, "%d\n", ctx->temp_critical_alarm);
  284. }
  285. static ssize_t power1_label_show(struct device *dev,
  286. struct device_attribute *attr,
  287. char *buf)
  288. {
  289. return snprintf(buf, PAGE_SIZE, "CPU power\n");
  290. }
  291. static ssize_t power2_label_show(struct device *dev,
  292. struct device_attribute *attr,
  293. char *buf)
  294. {
  295. return snprintf(buf, PAGE_SIZE, "IO power\n");
  296. }
  297. static ssize_t power1_input_show(struct device *dev,
  298. struct device_attribute *attr,
  299. char *buf)
  300. {
  301. struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
  302. u32 val;
  303. int rc;
  304. rc = xgene_hwmon_get_cpu_pwr(ctx, &val);
  305. if (rc < 0)
  306. return rc;
  307. return snprintf(buf, PAGE_SIZE, "%u\n", mWATT_TO_uWATT(val));
  308. }
  309. static ssize_t power2_input_show(struct device *dev,
  310. struct device_attribute *attr,
  311. char *buf)
  312. {
  313. struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
  314. u32 val;
  315. int rc;
  316. rc = xgene_hwmon_get_io_pwr(ctx, &val);
  317. if (rc < 0)
  318. return rc;
  319. return snprintf(buf, PAGE_SIZE, "%u\n", mWATT_TO_uWATT(val));
  320. }
  321. static DEVICE_ATTR_RO(temp1_label);
  322. static DEVICE_ATTR_RO(temp1_input);
  323. static DEVICE_ATTR_RO(temp1_critical_alarm);
  324. static DEVICE_ATTR_RO(power1_label);
  325. static DEVICE_ATTR_RO(power1_input);
  326. static DEVICE_ATTR_RO(power2_label);
  327. static DEVICE_ATTR_RO(power2_input);
  328. static struct attribute *xgene_hwmon_attrs[] = {
  329. &dev_attr_temp1_label.attr,
  330. &dev_attr_temp1_input.attr,
  331. &dev_attr_temp1_critical_alarm.attr,
  332. &dev_attr_power1_label.attr,
  333. &dev_attr_power1_input.attr,
  334. &dev_attr_power2_label.attr,
  335. &dev_attr_power2_input.attr,
  336. NULL,
  337. };
  338. ATTRIBUTE_GROUPS(xgene_hwmon);
  339. static int xgene_hwmon_tpc_alarm(struct xgene_hwmon_dev *ctx,
  340. struct slimpro_resp_msg *amsg)
  341. {
  342. ctx->temp_critical_alarm = !!amsg->param2;
  343. sysfs_notify(&ctx->dev->kobj, NULL, "temp1_critical_alarm");
  344. return 0;
  345. }
  346. static void xgene_hwmon_process_pwrmsg(struct xgene_hwmon_dev *ctx,
  347. struct slimpro_resp_msg *amsg)
  348. {
  349. if ((MSG_SUBTYPE(amsg->msg) == PWRMGMT_SUBTYPE_TPC) &&
  350. (TPC_CMD(amsg->msg) == TPC_ALARM))
  351. xgene_hwmon_tpc_alarm(ctx, amsg);
  352. }
  353. /*
  354. * This function is called to process async work queue
  355. */
  356. static void xgene_hwmon_evt_work(struct work_struct *work)
  357. {
  358. struct slimpro_resp_msg amsg;
  359. struct xgene_hwmon_dev *ctx;
  360. int ret;
  361. ctx = container_of(work, struct xgene_hwmon_dev, workq);
  362. while (kfifo_out_spinlocked(&ctx->async_msg_fifo, &amsg,
  363. sizeof(struct slimpro_resp_msg),
  364. &ctx->kfifo_lock)) {
  365. /*
  366. * If PCC, send a consumer command to Platform to get info
  367. * If Slimpro Mailbox, get message from specific FIFO
  368. */
  369. if (!acpi_disabled) {
  370. ret = xgene_hwmon_get_notification_msg(ctx,
  371. (u32 *)&amsg);
  372. if (ret < 0)
  373. continue;
  374. }
  375. if (MSG_TYPE(amsg.msg) == MSG_TYPE_PWRMGMT)
  376. xgene_hwmon_process_pwrmsg(ctx, &amsg);
  377. }
  378. }
  379. static int xgene_hwmon_rx_ready(struct xgene_hwmon_dev *ctx, void *msg)
  380. {
  381. if (IS_ERR_OR_NULL(ctx->hwmon_dev) && !ctx->resp_pending) {
  382. /* Enqueue to the FIFO */
  383. kfifo_in_spinlocked(&ctx->async_msg_fifo, msg,
  384. sizeof(struct slimpro_resp_msg),
  385. &ctx->kfifo_lock);
  386. return -ENODEV;
  387. }
  388. return 0;
  389. }
  390. /*
  391. * This function is called when the SLIMpro Mailbox received a message
  392. */
  393. static void xgene_hwmon_rx_cb(struct mbox_client *cl, void *msg)
  394. {
  395. struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl);
  396. /*
  397. * While the driver registers with the mailbox framework, an interrupt
  398. * can be pending before the probe function completes its
  399. * initialization. If such condition occurs, just queue up the message
  400. * as the driver is not ready for servicing the callback.
  401. */
  402. if (xgene_hwmon_rx_ready(ctx, msg) < 0)
  403. return;
  404. /*
  405. * Response message format:
  406. * msg[0] is the return code of the operation
  407. * msg[1] is the first parameter word
  408. * msg[2] is the second parameter word
  409. *
  410. * As message only supports dword size, just assign it.
  411. */
  412. /* Check for sync query */
  413. if (ctx->resp_pending &&
  414. ((MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_ERR) ||
  415. (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_DBG &&
  416. MSG_SUBTYPE(((u32 *)msg)[0]) == DBG_SUBTYPE_SENSOR_READ) ||
  417. (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_PWRMGMT &&
  418. MSG_SUBTYPE(((u32 *)msg)[0]) == PWRMGMT_SUBTYPE_TPC &&
  419. TPC_CMD(((u32 *)msg)[0]) == TPC_ALARM))) {
  420. ctx->sync_msg.msg = ((u32 *)msg)[0];
  421. ctx->sync_msg.param1 = ((u32 *)msg)[1];
  422. ctx->sync_msg.param2 = ((u32 *)msg)[2];
  423. /* Operation waiting for response */
  424. complete(&ctx->rd_complete);
  425. return;
  426. }
  427. /* Enqueue to the FIFO */
  428. kfifo_in_spinlocked(&ctx->async_msg_fifo, msg,
  429. sizeof(struct slimpro_resp_msg), &ctx->kfifo_lock);
  430. /* Schedule the bottom handler */
  431. schedule_work(&ctx->workq);
  432. }
  433. /*
  434. * This function is called when the PCC Mailbox received a message
  435. */
  436. static void xgene_hwmon_pcc_rx_cb(struct mbox_client *cl, void *msg)
  437. {
  438. struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl);
  439. struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
  440. struct slimpro_resp_msg amsg;
  441. /*
  442. * While the driver registers with the mailbox framework, an interrupt
  443. * can be pending before the probe function completes its
  444. * initialization. If such condition occurs, just queue up the message
  445. * as the driver is not ready for servicing the callback.
  446. */
  447. if (xgene_hwmon_rx_ready(ctx, &amsg) < 0)
  448. return;
  449. msg = generic_comm_base + 1;
  450. /* Check if platform sends interrupt */
  451. if (!xgene_word_tst_and_clr(&generic_comm_base->status,
  452. PCCS_SCI_DOORBEL))
  453. return;
  454. /*
  455. * Response message format:
  456. * msg[0] is the return code of the operation
  457. * msg[1] is the first parameter word
  458. * msg[2] is the second parameter word
  459. *
  460. * As message only supports dword size, just assign it.
  461. */
  462. /* Check for sync query */
  463. if (ctx->resp_pending &&
  464. ((MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_ERR) ||
  465. (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_DBG &&
  466. MSG_SUBTYPE(((u32 *)msg)[0]) == DBG_SUBTYPE_SENSOR_READ) ||
  467. (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_PWRMGMT &&
  468. MSG_SUBTYPE(((u32 *)msg)[0]) == PWRMGMT_SUBTYPE_TPC &&
  469. TPC_CMD(((u32 *)msg)[0]) == TPC_ALARM))) {
  470. /* Check if platform completes command */
  471. if (xgene_word_tst_and_clr(&generic_comm_base->status,
  472. PCCS_CMD_COMPLETE)) {
  473. ctx->sync_msg.msg = ((u32 *)msg)[0];
  474. ctx->sync_msg.param1 = ((u32 *)msg)[1];
  475. ctx->sync_msg.param2 = ((u32 *)msg)[2];
  476. /* Operation waiting for response */
  477. complete(&ctx->rd_complete);
  478. return;
  479. }
  480. }
  481. /*
  482. * Platform notifies interrupt to OSPM.
  483. * OPSM schedules a consumer command to get this information
  484. * in a workqueue. Platform must wait until OSPM has issued
  485. * a consumer command that serves this notification.
  486. */
  487. /* Enqueue to the FIFO */
  488. kfifo_in_spinlocked(&ctx->async_msg_fifo, &amsg,
  489. sizeof(struct slimpro_resp_msg), &ctx->kfifo_lock);
  490. /* Schedule the bottom handler */
  491. schedule_work(&ctx->workq);
  492. }
  493. static void xgene_hwmon_tx_done(struct mbox_client *cl, void *msg, int ret)
  494. {
  495. if (ret) {
  496. dev_dbg(cl->dev, "TX did not complete: CMD sent:%x, ret:%d\n",
  497. *(u16 *)msg, ret);
  498. } else {
  499. dev_dbg(cl->dev, "TX completed. CMD sent:%x, ret:%d\n",
  500. *(u16 *)msg, ret);
  501. }
  502. }
  503. #ifdef CONFIG_ACPI
  504. static const struct acpi_device_id xgene_hwmon_acpi_match[] = {
  505. {"APMC0D29", XGENE_HWMON_V1},
  506. {"APMC0D8A", XGENE_HWMON_V2},
  507. {},
  508. };
  509. MODULE_DEVICE_TABLE(acpi, xgene_hwmon_acpi_match);
  510. #endif
  511. static int xgene_hwmon_probe(struct platform_device *pdev)
  512. {
  513. struct xgene_hwmon_dev *ctx;
  514. struct mbox_client *cl;
  515. int rc;
  516. ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
  517. if (!ctx)
  518. return -ENOMEM;
  519. ctx->dev = &pdev->dev;
  520. platform_set_drvdata(pdev, ctx);
  521. cl = &ctx->mbox_client;
  522. spin_lock_init(&ctx->kfifo_lock);
  523. mutex_init(&ctx->rd_mutex);
  524. rc = kfifo_alloc(&ctx->async_msg_fifo,
  525. sizeof(struct slimpro_resp_msg) * ASYNC_MSG_FIFO_SIZE,
  526. GFP_KERNEL);
  527. if (rc)
  528. return -ENOMEM;
  529. INIT_WORK(&ctx->workq, xgene_hwmon_evt_work);
  530. /* Request mailbox channel */
  531. cl->dev = &pdev->dev;
  532. cl->tx_done = xgene_hwmon_tx_done;
  533. cl->tx_block = false;
  534. cl->tx_tout = MBOX_OP_TIMEOUTMS;
  535. cl->knows_txdone = false;
  536. if (acpi_disabled) {
  537. cl->rx_callback = xgene_hwmon_rx_cb;
  538. ctx->mbox_chan = mbox_request_channel(cl, 0);
  539. if (IS_ERR(ctx->mbox_chan)) {
  540. dev_err(&pdev->dev,
  541. "SLIMpro mailbox channel request failed\n");
  542. rc = -ENODEV;
  543. goto out_mbox_free;
  544. }
  545. } else {
  546. struct acpi_pcct_hw_reduced *cppc_ss;
  547. const struct acpi_device_id *acpi_id;
  548. int version;
  549. acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
  550. &pdev->dev);
  551. if (!acpi_id)
  552. return -EINVAL;
  553. version = (int)acpi_id->driver_data;
  554. if (device_property_read_u32(&pdev->dev, "pcc-channel",
  555. &ctx->mbox_idx)) {
  556. dev_err(&pdev->dev, "no pcc-channel property\n");
  557. rc = -ENODEV;
  558. goto out_mbox_free;
  559. }
  560. cl->rx_callback = xgene_hwmon_pcc_rx_cb;
  561. ctx->mbox_chan = pcc_mbox_request_channel(cl, ctx->mbox_idx);
  562. if (IS_ERR(ctx->mbox_chan)) {
  563. dev_err(&pdev->dev,
  564. "PPC channel request failed\n");
  565. rc = -ENODEV;
  566. goto out_mbox_free;
  567. }
  568. /*
  569. * The PCC mailbox controller driver should
  570. * have parsed the PCCT (global table of all
  571. * PCC channels) and stored pointers to the
  572. * subspace communication region in con_priv.
  573. */
  574. cppc_ss = ctx->mbox_chan->con_priv;
  575. if (!cppc_ss) {
  576. dev_err(&pdev->dev, "PPC subspace not found\n");
  577. rc = -ENODEV;
  578. goto out;
  579. }
  580. if (!ctx->mbox_chan->mbox->txdone_irq) {
  581. dev_err(&pdev->dev, "PCC IRQ not supported\n");
  582. rc = -ENODEV;
  583. goto out;
  584. }
  585. /*
  586. * This is the shared communication region
  587. * for the OS and Platform to communicate over.
  588. */
  589. ctx->comm_base_addr = cppc_ss->base_address;
  590. if (ctx->comm_base_addr) {
  591. if (version == XGENE_HWMON_V2)
  592. ctx->pcc_comm_addr = (void __force *)ioremap(
  593. ctx->comm_base_addr,
  594. cppc_ss->length);
  595. else
  596. ctx->pcc_comm_addr = memremap(
  597. ctx->comm_base_addr,
  598. cppc_ss->length,
  599. MEMREMAP_WB);
  600. } else {
  601. dev_err(&pdev->dev, "Failed to get PCC comm region\n");
  602. rc = -ENODEV;
  603. goto out;
  604. }
  605. if (!ctx->pcc_comm_addr) {
  606. dev_err(&pdev->dev,
  607. "Failed to ioremap PCC comm region\n");
  608. rc = -ENOMEM;
  609. goto out;
  610. }
  611. /*
  612. * cppc_ss->latency is just a Nominal value. In reality
  613. * the remote processor could be much slower to reply.
  614. * So add an arbitrary amount of wait on top of Nominal.
  615. */
  616. ctx->usecs_lat = PCC_NUM_RETRIES * cppc_ss->latency;
  617. }
  618. ctx->hwmon_dev = hwmon_device_register_with_groups(ctx->dev,
  619. "apm_xgene",
  620. ctx,
  621. xgene_hwmon_groups);
  622. if (IS_ERR(ctx->hwmon_dev)) {
  623. dev_err(&pdev->dev, "Failed to register HW monitor device\n");
  624. rc = PTR_ERR(ctx->hwmon_dev);
  625. goto out;
  626. }
  627. /*
  628. * Schedule the bottom handler if there is a pending message.
  629. */
  630. schedule_work(&ctx->workq);
  631. dev_info(&pdev->dev, "APM X-Gene SoC HW monitor driver registered\n");
  632. return 0;
  633. out:
  634. if (acpi_disabled)
  635. mbox_free_channel(ctx->mbox_chan);
  636. else
  637. pcc_mbox_free_channel(ctx->mbox_chan);
  638. out_mbox_free:
  639. kfifo_free(&ctx->async_msg_fifo);
  640. return rc;
  641. }
  642. static int xgene_hwmon_remove(struct platform_device *pdev)
  643. {
  644. struct xgene_hwmon_dev *ctx = platform_get_drvdata(pdev);
  645. hwmon_device_unregister(ctx->hwmon_dev);
  646. kfifo_free(&ctx->async_msg_fifo);
  647. if (acpi_disabled)
  648. mbox_free_channel(ctx->mbox_chan);
  649. else
  650. pcc_mbox_free_channel(ctx->mbox_chan);
  651. return 0;
  652. }
  653. static const struct of_device_id xgene_hwmon_of_match[] = {
  654. {.compatible = "apm,xgene-slimpro-hwmon"},
  655. {}
  656. };
  657. MODULE_DEVICE_TABLE(of, xgene_hwmon_of_match);
  658. static struct platform_driver xgene_hwmon_driver __refdata = {
  659. .probe = xgene_hwmon_probe,
  660. .remove = xgene_hwmon_remove,
  661. .driver = {
  662. .name = "xgene-slimpro-hwmon",
  663. .of_match_table = xgene_hwmon_of_match,
  664. .acpi_match_table = ACPI_PTR(xgene_hwmon_acpi_match),
  665. },
  666. };
  667. module_platform_driver(xgene_hwmon_driver);
  668. MODULE_DESCRIPTION("APM X-Gene SoC hardware monitor");
  669. MODULE_LICENSE("GPL");