w83627ehf.c 62 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * w83627ehf - Driver for the hardware monitoring functionality of
  4. * the Winbond W83627EHF Super-I/O chip
  5. * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
  6. * Copyright (C) 2006 Yuan Mu (Winbond),
  7. * Rudolf Marek <r.marek@assembler.cz>
  8. * David Hubbard <david.c.hubbard@gmail.com>
  9. * Daniel J Blueman <daniel.blueman@gmail.com>
  10. * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
  11. *
  12. * Shamelessly ripped from the w83627hf driver
  13. * Copyright (C) 2003 Mark Studebaker
  14. *
  15. * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
  16. * in testing and debugging this driver.
  17. *
  18. * This driver also supports the W83627EHG, which is the lead-free
  19. * version of the W83627EHF.
  20. *
  21. * Supports the following chips:
  22. *
  23. * Chip #vin #fan #pwm #temp chip IDs man ID
  24. * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
  25. * 0x8860 0xa1
  26. * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
  27. * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
  28. * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
  29. * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
  30. * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
  31. */
  32. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/jiffies.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/hwmon.h>
  39. #include <linux/hwmon-sysfs.h>
  40. #include <linux/hwmon-vid.h>
  41. #include <linux/err.h>
  42. #include <linux/mutex.h>
  43. #include <linux/acpi.h>
  44. #include <linux/io.h>
  45. #include "lm75.h"
  46. enum kinds {
  47. w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
  48. w83667hg, w83667hg_b,
  49. };
  50. /* used to set data->name = w83627ehf_device_names[data->sio_kind] */
  51. static const char * const w83627ehf_device_names[] = {
  52. "w83627ehf",
  53. "w83627dhg",
  54. "w83627dhg",
  55. "w83627uhg",
  56. "w83667hg",
  57. "w83667hg",
  58. };
  59. static unsigned short force_id;
  60. module_param(force_id, ushort, 0);
  61. MODULE_PARM_DESC(force_id, "Override the detected device ID");
  62. #define DRVNAME "w83627ehf"
  63. /*
  64. * Super-I/O constants and functions
  65. */
  66. #define W83627EHF_LD_HWM 0x0b
  67. #define W83667HG_LD_VID 0x0d
  68. #define SIO_REG_LDSEL 0x07 /* Logical device select */
  69. #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
  70. #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
  71. #define SIO_REG_ENABLE 0x30 /* Logical device enable */
  72. #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
  73. #define SIO_REG_VID_CTRL 0xF0 /* VID control */
  74. #define SIO_REG_VID_DATA 0xF1 /* VID data */
  75. #define SIO_W83627EHF_ID 0x8850
  76. #define SIO_W83627EHG_ID 0x8860
  77. #define SIO_W83627DHG_ID 0xa020
  78. #define SIO_W83627DHG_P_ID 0xb070
  79. #define SIO_W83627UHG_ID 0xa230
  80. #define SIO_W83667HG_ID 0xa510
  81. #define SIO_W83667HG_B_ID 0xb350
  82. #define SIO_ID_MASK 0xFFF0
  83. static inline void
  84. superio_outb(int ioreg, int reg, int val)
  85. {
  86. outb(reg, ioreg);
  87. outb(val, ioreg + 1);
  88. }
  89. static inline int
  90. superio_inb(int ioreg, int reg)
  91. {
  92. outb(reg, ioreg);
  93. return inb(ioreg + 1);
  94. }
  95. static inline void
  96. superio_select(int ioreg, int ld)
  97. {
  98. outb(SIO_REG_LDSEL, ioreg);
  99. outb(ld, ioreg + 1);
  100. }
  101. static inline int
  102. superio_enter(int ioreg)
  103. {
  104. if (!request_muxed_region(ioreg, 2, DRVNAME))
  105. return -EBUSY;
  106. outb(0x87, ioreg);
  107. outb(0x87, ioreg);
  108. return 0;
  109. }
  110. static inline void
  111. superio_exit(int ioreg)
  112. {
  113. outb(0xaa, ioreg);
  114. outb(0x02, ioreg);
  115. outb(0x02, ioreg + 1);
  116. release_region(ioreg, 2);
  117. }
  118. /*
  119. * ISA constants
  120. */
  121. #define IOREGION_ALIGNMENT (~7)
  122. #define IOREGION_OFFSET 5
  123. #define IOREGION_LENGTH 2
  124. #define ADDR_REG_OFFSET 0
  125. #define DATA_REG_OFFSET 1
  126. #define W83627EHF_REG_BANK 0x4E
  127. #define W83627EHF_REG_CONFIG 0x40
  128. /*
  129. * Not currently used:
  130. * REG_MAN_ID has the value 0x5ca3 for all supported chips.
  131. * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
  132. * REG_MAN_ID is at port 0x4f
  133. * REG_CHIP_ID is at port 0x58
  134. */
  135. static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
  136. static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
  137. /* The W83627EHF registers for nr=7,8,9 are in bank 5 */
  138. #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
  139. (0x554 + (((nr) - 7) * 2)))
  140. #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
  141. (0x555 + (((nr) - 7) * 2)))
  142. #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
  143. (0x550 + (nr) - 7))
  144. static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
  145. static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
  146. static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
  147. static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
  148. /* Fan clock dividers are spread over the following five registers */
  149. #define W83627EHF_REG_FANDIV1 0x47
  150. #define W83627EHF_REG_FANDIV2 0x4B
  151. #define W83627EHF_REG_VBAT 0x5D
  152. #define W83627EHF_REG_DIODE 0x59
  153. #define W83627EHF_REG_SMI_OVT 0x4C
  154. #define W83627EHF_REG_ALARM1 0x459
  155. #define W83627EHF_REG_ALARM2 0x45A
  156. #define W83627EHF_REG_ALARM3 0x45B
  157. #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
  158. #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
  159. /* SmartFan registers */
  160. #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
  161. #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
  162. /* DC or PWM output fan configuration */
  163. static const u8 W83627EHF_REG_PWM_ENABLE[] = {
  164. 0x04, /* SYS FAN0 output mode and PWM mode */
  165. 0x04, /* CPU FAN0 output mode and PWM mode */
  166. 0x12, /* AUX FAN mode */
  167. 0x62, /* CPU FAN1 mode */
  168. };
  169. static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
  170. static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
  171. /* FAN Duty Cycle, be used to control */
  172. static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
  173. static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
  174. static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
  175. /* Advanced Fan control, some values are common for all fans */
  176. static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
  177. static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
  178. static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
  179. static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
  180. = { 0xff, 0x67, 0xff, 0x69 };
  181. static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
  182. = { 0xff, 0x68, 0xff, 0x6a };
  183. static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
  184. static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
  185. = { 0x68, 0x6a, 0x6c };
  186. static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
  187. static const char *const w83667hg_b_temp_label[] = {
  188. "SYSTIN",
  189. "CPUTIN",
  190. "AUXTIN",
  191. "AMDTSI",
  192. "PECI Agent 1",
  193. "PECI Agent 2",
  194. "PECI Agent 3",
  195. "PECI Agent 4"
  196. };
  197. #define NUM_REG_TEMP ARRAY_SIZE(W83627EHF_REG_TEMP)
  198. static int is_word_sized(u16 reg)
  199. {
  200. return ((((reg & 0xff00) == 0x100
  201. || (reg & 0xff00) == 0x200)
  202. && ((reg & 0x00ff) == 0x50
  203. || (reg & 0x00ff) == 0x53
  204. || (reg & 0x00ff) == 0x55))
  205. || (reg & 0xfff0) == 0x630
  206. || reg == 0x640 || reg == 0x642
  207. || ((reg & 0xfff0) == 0x650
  208. && (reg & 0x000f) >= 0x06)
  209. || reg == 0x73 || reg == 0x75 || reg == 0x77
  210. );
  211. }
  212. /*
  213. * Conversions
  214. */
  215. /* 1 is PWM mode, output in ms */
  216. static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
  217. {
  218. return mode ? 100 * reg : 400 * reg;
  219. }
  220. static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
  221. {
  222. return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
  223. 1, 255);
  224. }
  225. static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
  226. {
  227. if (reg == 0 || reg == 255)
  228. return 0;
  229. return 1350000U / (reg << divreg);
  230. }
  231. static inline unsigned int
  232. div_from_reg(u8 reg)
  233. {
  234. return 1 << reg;
  235. }
  236. /*
  237. * Some of the voltage inputs have internal scaling, the tables below
  238. * contain 8 (the ADC LSB in mV) * scaling factor * 100
  239. */
  240. static const u16 scale_in_common[10] = {
  241. 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
  242. };
  243. static const u16 scale_in_w83627uhg[9] = {
  244. 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
  245. };
  246. static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
  247. {
  248. return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
  249. }
  250. static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
  251. {
  252. return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
  253. }
  254. /*
  255. * Data structures and manipulation thereof
  256. */
  257. struct w83627ehf_data {
  258. int addr; /* IO base of hw monitor block */
  259. const char *name;
  260. struct mutex lock;
  261. u16 reg_temp[NUM_REG_TEMP];
  262. u16 reg_temp_over[NUM_REG_TEMP];
  263. u16 reg_temp_hyst[NUM_REG_TEMP];
  264. u16 reg_temp_config[NUM_REG_TEMP];
  265. u8 temp_src[NUM_REG_TEMP];
  266. const char * const *temp_label;
  267. const u16 *REG_FAN_MAX_OUTPUT;
  268. const u16 *REG_FAN_STEP_OUTPUT;
  269. const u16 *scale_in;
  270. struct mutex update_lock;
  271. char valid; /* !=0 if following fields are valid */
  272. unsigned long last_updated; /* In jiffies */
  273. /* Register values */
  274. u8 bank; /* current register bank */
  275. u8 in_num; /* number of in inputs we have */
  276. u8 in[10]; /* Register value */
  277. u8 in_max[10]; /* Register value */
  278. u8 in_min[10]; /* Register value */
  279. unsigned int rpm[5];
  280. u16 fan_min[5];
  281. u8 fan_div[5];
  282. u8 has_fan; /* some fan inputs can be disabled */
  283. u8 has_fan_min; /* some fans don't have min register */
  284. u8 temp_type[3];
  285. s8 temp_offset[3];
  286. s16 temp[9];
  287. s16 temp_max[9];
  288. s16 temp_max_hyst[9];
  289. u32 alarms;
  290. u8 caseopen;
  291. u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
  292. u8 pwm_enable[4]; /* 1->manual
  293. * 2->thermal cruise mode (also called SmartFan I)
  294. * 3->fan speed cruise mode
  295. * 4->variable thermal cruise (also called
  296. * SmartFan III)
  297. * 5->enhanced variable thermal cruise (also called
  298. * SmartFan IV)
  299. */
  300. u8 pwm_enable_orig[4]; /* original value of pwm_enable */
  301. u8 pwm_num; /* number of pwm */
  302. u8 pwm[4];
  303. u8 target_temp[4];
  304. u8 tolerance[4];
  305. u8 fan_start_output[4]; /* minimum fan speed when spinning up */
  306. u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
  307. u8 fan_stop_time[4]; /* time at minimum before disabling fan */
  308. u8 fan_max_output[4]; /* maximum fan speed */
  309. u8 fan_step_output[4]; /* rate of change output value */
  310. u8 vid;
  311. u8 vrm;
  312. u16 have_temp;
  313. u16 have_temp_offset;
  314. u8 in6_skip:1;
  315. u8 temp3_val_only:1;
  316. u8 have_vid:1;
  317. #ifdef CONFIG_PM
  318. /* Remember extra register values over suspend/resume */
  319. u8 vbat;
  320. u8 fandiv1;
  321. u8 fandiv2;
  322. #endif
  323. };
  324. struct w83627ehf_sio_data {
  325. int sioreg;
  326. enum kinds kind;
  327. };
  328. /*
  329. * On older chips, only registers 0x50-0x5f are banked.
  330. * On more recent chips, all registers are banked.
  331. * Assume that is the case and set the bank number for each access.
  332. * Cache the bank number so it only needs to be set if it changes.
  333. */
  334. static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
  335. {
  336. u8 bank = reg >> 8;
  337. if (data->bank != bank) {
  338. outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
  339. outb_p(bank, data->addr + DATA_REG_OFFSET);
  340. data->bank = bank;
  341. }
  342. }
  343. static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
  344. {
  345. int res, word_sized = is_word_sized(reg);
  346. mutex_lock(&data->lock);
  347. w83627ehf_set_bank(data, reg);
  348. outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
  349. res = inb_p(data->addr + DATA_REG_OFFSET);
  350. if (word_sized) {
  351. outb_p((reg & 0xff) + 1,
  352. data->addr + ADDR_REG_OFFSET);
  353. res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
  354. }
  355. mutex_unlock(&data->lock);
  356. return res;
  357. }
  358. static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
  359. u16 value)
  360. {
  361. int word_sized = is_word_sized(reg);
  362. mutex_lock(&data->lock);
  363. w83627ehf_set_bank(data, reg);
  364. outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
  365. if (word_sized) {
  366. outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
  367. outb_p((reg & 0xff) + 1,
  368. data->addr + ADDR_REG_OFFSET);
  369. }
  370. outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
  371. mutex_unlock(&data->lock);
  372. return 0;
  373. }
  374. /* We left-align 8-bit temperature values to make the code simpler */
  375. static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
  376. {
  377. u16 res;
  378. res = w83627ehf_read_value(data, reg);
  379. if (!is_word_sized(reg))
  380. res <<= 8;
  381. return res;
  382. }
  383. static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
  384. u16 value)
  385. {
  386. if (!is_word_sized(reg))
  387. value >>= 8;
  388. return w83627ehf_write_value(data, reg, value);
  389. }
  390. /* This function assumes that the caller holds data->update_lock */
  391. static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
  392. {
  393. u8 reg;
  394. switch (nr) {
  395. case 0:
  396. reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
  397. | ((data->fan_div[0] & 0x03) << 4);
  398. /* fan5 input control bit is write only, compute the value */
  399. reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
  400. w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
  401. reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
  402. | ((data->fan_div[0] & 0x04) << 3);
  403. w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
  404. break;
  405. case 1:
  406. reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
  407. | ((data->fan_div[1] & 0x03) << 6);
  408. /* fan5 input control bit is write only, compute the value */
  409. reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
  410. w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
  411. reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
  412. | ((data->fan_div[1] & 0x04) << 4);
  413. w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
  414. break;
  415. case 2:
  416. reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
  417. | ((data->fan_div[2] & 0x03) << 6);
  418. w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
  419. reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
  420. | ((data->fan_div[2] & 0x04) << 5);
  421. w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
  422. break;
  423. case 3:
  424. reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
  425. | (data->fan_div[3] & 0x03);
  426. w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
  427. reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
  428. | ((data->fan_div[3] & 0x04) << 5);
  429. w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
  430. break;
  431. case 4:
  432. reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
  433. | ((data->fan_div[4] & 0x03) << 2)
  434. | ((data->fan_div[4] & 0x04) << 5);
  435. w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
  436. break;
  437. }
  438. }
  439. static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
  440. {
  441. int i;
  442. i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
  443. data->fan_div[0] = (i >> 4) & 0x03;
  444. data->fan_div[1] = (i >> 6) & 0x03;
  445. i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
  446. data->fan_div[2] = (i >> 6) & 0x03;
  447. i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
  448. data->fan_div[0] |= (i >> 3) & 0x04;
  449. data->fan_div[1] |= (i >> 4) & 0x04;
  450. data->fan_div[2] |= (i >> 5) & 0x04;
  451. if (data->has_fan & ((1 << 3) | (1 << 4))) {
  452. i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
  453. data->fan_div[3] = i & 0x03;
  454. data->fan_div[4] = ((i >> 2) & 0x03)
  455. | ((i >> 5) & 0x04);
  456. }
  457. if (data->has_fan & (1 << 3)) {
  458. i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
  459. data->fan_div[3] |= (i >> 5) & 0x04;
  460. }
  461. }
  462. static void w83627ehf_update_pwm(struct w83627ehf_data *data)
  463. {
  464. int i;
  465. int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
  466. for (i = 0; i < data->pwm_num; i++) {
  467. if (!(data->has_fan & (1 << i)))
  468. continue;
  469. /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
  470. if (i != 1) {
  471. pwmcfg = w83627ehf_read_value(data,
  472. W83627EHF_REG_PWM_ENABLE[i]);
  473. tolerance = w83627ehf_read_value(data,
  474. W83627EHF_REG_TOLERANCE[i]);
  475. }
  476. data->pwm_mode[i] =
  477. ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
  478. data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
  479. & 3) + 1;
  480. data->pwm[i] = w83627ehf_read_value(data, W83627EHF_REG_PWM[i]);
  481. data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
  482. }
  483. }
  484. static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
  485. {
  486. struct w83627ehf_data *data = dev_get_drvdata(dev);
  487. int i;
  488. mutex_lock(&data->update_lock);
  489. if (time_after(jiffies, data->last_updated + HZ + HZ/2)
  490. || !data->valid) {
  491. /* Fan clock dividers */
  492. w83627ehf_update_fan_div(data);
  493. /* Measured voltages and limits */
  494. for (i = 0; i < data->in_num; i++) {
  495. if ((i == 6) && data->in6_skip)
  496. continue;
  497. data->in[i] = w83627ehf_read_value(data,
  498. W83627EHF_REG_IN(i));
  499. data->in_min[i] = w83627ehf_read_value(data,
  500. W83627EHF_REG_IN_MIN(i));
  501. data->in_max[i] = w83627ehf_read_value(data,
  502. W83627EHF_REG_IN_MAX(i));
  503. }
  504. /* Measured fan speeds and limits */
  505. for (i = 0; i < 5; i++) {
  506. u16 reg;
  507. if (!(data->has_fan & (1 << i)))
  508. continue;
  509. reg = w83627ehf_read_value(data, W83627EHF_REG_FAN[i]);
  510. data->rpm[i] = fan_from_reg8(reg, data->fan_div[i]);
  511. if (data->has_fan_min & (1 << i))
  512. data->fan_min[i] = w83627ehf_read_value(data,
  513. W83627EHF_REG_FAN_MIN[i]);
  514. /*
  515. * If we failed to measure the fan speed and clock
  516. * divider can be increased, let's try that for next
  517. * time
  518. */
  519. if (reg >= 0xff && data->fan_div[i] < 0x07) {
  520. dev_dbg(dev,
  521. "Increasing fan%d clock divider from %u to %u\n",
  522. i + 1, div_from_reg(data->fan_div[i]),
  523. div_from_reg(data->fan_div[i] + 1));
  524. data->fan_div[i]++;
  525. w83627ehf_write_fan_div(data, i);
  526. /* Preserve min limit if possible */
  527. if ((data->has_fan_min & (1 << i))
  528. && data->fan_min[i] >= 2
  529. && data->fan_min[i] != 255)
  530. w83627ehf_write_value(data,
  531. W83627EHF_REG_FAN_MIN[i],
  532. (data->fan_min[i] /= 2));
  533. }
  534. }
  535. w83627ehf_update_pwm(data);
  536. for (i = 0; i < data->pwm_num; i++) {
  537. if (!(data->has_fan & (1 << i)))
  538. continue;
  539. data->fan_start_output[i] =
  540. w83627ehf_read_value(data,
  541. W83627EHF_REG_FAN_START_OUTPUT[i]);
  542. data->fan_stop_output[i] =
  543. w83627ehf_read_value(data,
  544. W83627EHF_REG_FAN_STOP_OUTPUT[i]);
  545. data->fan_stop_time[i] =
  546. w83627ehf_read_value(data,
  547. W83627EHF_REG_FAN_STOP_TIME[i]);
  548. if (data->REG_FAN_MAX_OUTPUT &&
  549. data->REG_FAN_MAX_OUTPUT[i] != 0xff)
  550. data->fan_max_output[i] =
  551. w83627ehf_read_value(data,
  552. data->REG_FAN_MAX_OUTPUT[i]);
  553. if (data->REG_FAN_STEP_OUTPUT &&
  554. data->REG_FAN_STEP_OUTPUT[i] != 0xff)
  555. data->fan_step_output[i] =
  556. w83627ehf_read_value(data,
  557. data->REG_FAN_STEP_OUTPUT[i]);
  558. data->target_temp[i] =
  559. w83627ehf_read_value(data,
  560. W83627EHF_REG_TARGET[i]) &
  561. (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
  562. }
  563. /* Measured temperatures and limits */
  564. for (i = 0; i < NUM_REG_TEMP; i++) {
  565. if (!(data->have_temp & (1 << i)))
  566. continue;
  567. data->temp[i] = w83627ehf_read_temp(data,
  568. data->reg_temp[i]);
  569. if (data->reg_temp_over[i])
  570. data->temp_max[i]
  571. = w83627ehf_read_temp(data,
  572. data->reg_temp_over[i]);
  573. if (data->reg_temp_hyst[i])
  574. data->temp_max_hyst[i]
  575. = w83627ehf_read_temp(data,
  576. data->reg_temp_hyst[i]);
  577. if (i > 2)
  578. continue;
  579. if (data->have_temp_offset & (1 << i))
  580. data->temp_offset[i]
  581. = w83627ehf_read_value(data,
  582. W83627EHF_REG_TEMP_OFFSET[i]);
  583. }
  584. data->alarms = w83627ehf_read_value(data,
  585. W83627EHF_REG_ALARM1) |
  586. (w83627ehf_read_value(data,
  587. W83627EHF_REG_ALARM2) << 8) |
  588. (w83627ehf_read_value(data,
  589. W83627EHF_REG_ALARM3) << 16);
  590. data->caseopen = w83627ehf_read_value(data,
  591. W83627EHF_REG_CASEOPEN_DET);
  592. data->last_updated = jiffies;
  593. data->valid = 1;
  594. }
  595. mutex_unlock(&data->update_lock);
  596. return data;
  597. }
  598. #define store_in_reg(REG, reg) \
  599. static int \
  600. store_in_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
  601. long val) \
  602. { \
  603. if (val < 0) \
  604. return -EINVAL; \
  605. mutex_lock(&data->update_lock); \
  606. data->in_##reg[channel] = in_to_reg(val, channel, data->scale_in); \
  607. w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
  608. data->in_##reg[channel]); \
  609. mutex_unlock(&data->update_lock); \
  610. return 0; \
  611. }
  612. store_in_reg(MIN, min)
  613. store_in_reg(MAX, max)
  614. static int
  615. store_fan_min(struct device *dev, struct w83627ehf_data *data, int channel,
  616. long val)
  617. {
  618. unsigned int reg;
  619. u8 new_div;
  620. if (val < 0)
  621. return -EINVAL;
  622. mutex_lock(&data->update_lock);
  623. if (!val) {
  624. /* No min limit, alarm disabled */
  625. data->fan_min[channel] = 255;
  626. new_div = data->fan_div[channel]; /* No change */
  627. dev_info(dev, "fan%u low limit and alarm disabled\n",
  628. channel + 1);
  629. } else if ((reg = 1350000U / val) >= 128 * 255) {
  630. /*
  631. * Speed below this value cannot possibly be represented,
  632. * even with the highest divider (128)
  633. */
  634. data->fan_min[channel] = 254;
  635. new_div = 7; /* 128 == (1 << 7) */
  636. dev_warn(dev,
  637. "fan%u low limit %lu below minimum %u, set to minimum\n",
  638. channel + 1, val, fan_from_reg8(254, 7));
  639. } else if (!reg) {
  640. /*
  641. * Speed above this value cannot possibly be represented,
  642. * even with the lowest divider (1)
  643. */
  644. data->fan_min[channel] = 1;
  645. new_div = 0; /* 1 == (1 << 0) */
  646. dev_warn(dev,
  647. "fan%u low limit %lu above maximum %u, set to maximum\n",
  648. channel + 1, val, fan_from_reg8(1, 0));
  649. } else {
  650. /*
  651. * Automatically pick the best divider, i.e. the one such
  652. * that the min limit will correspond to a register value
  653. * in the 96..192 range
  654. */
  655. new_div = 0;
  656. while (reg > 192 && new_div < 7) {
  657. reg >>= 1;
  658. new_div++;
  659. }
  660. data->fan_min[channel] = reg;
  661. }
  662. /*
  663. * Write both the fan clock divider (if it changed) and the new
  664. * fan min (unconditionally)
  665. */
  666. if (new_div != data->fan_div[channel]) {
  667. dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
  668. channel + 1, div_from_reg(data->fan_div[channel]),
  669. div_from_reg(new_div));
  670. data->fan_div[channel] = new_div;
  671. w83627ehf_write_fan_div(data, channel);
  672. /* Give the chip time to sample a new speed value */
  673. data->last_updated = jiffies;
  674. }
  675. w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
  676. data->fan_min[channel]);
  677. mutex_unlock(&data->update_lock);
  678. return 0;
  679. }
  680. #define store_temp_reg(addr, reg) \
  681. static int \
  682. store_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
  683. long val) \
  684. { \
  685. mutex_lock(&data->update_lock); \
  686. data->reg[channel] = LM75_TEMP_TO_REG(val); \
  687. w83627ehf_write_temp(data, data->addr[channel], data->reg[channel]); \
  688. mutex_unlock(&data->update_lock); \
  689. return 0; \
  690. }
  691. store_temp_reg(reg_temp_over, temp_max);
  692. store_temp_reg(reg_temp_hyst, temp_max_hyst);
  693. static int
  694. store_temp_offset(struct device *dev, struct w83627ehf_data *data, int channel,
  695. long val)
  696. {
  697. val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
  698. mutex_lock(&data->update_lock);
  699. data->temp_offset[channel] = val;
  700. w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
  701. mutex_unlock(&data->update_lock);
  702. return 0;
  703. }
  704. static int
  705. store_pwm_mode(struct device *dev, struct w83627ehf_data *data, int channel,
  706. long val)
  707. {
  708. u16 reg;
  709. if (val < 0 || val > 1)
  710. return -EINVAL;
  711. mutex_lock(&data->update_lock);
  712. reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[channel]);
  713. data->pwm_mode[channel] = val;
  714. reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[channel]);
  715. if (!val)
  716. reg |= 1 << W83627EHF_PWM_MODE_SHIFT[channel];
  717. w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
  718. mutex_unlock(&data->update_lock);
  719. return 0;
  720. }
  721. static int
  722. store_pwm(struct device *dev, struct w83627ehf_data *data, int channel,
  723. long val)
  724. {
  725. val = clamp_val(val, 0, 255);
  726. mutex_lock(&data->update_lock);
  727. data->pwm[channel] = val;
  728. w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
  729. mutex_unlock(&data->update_lock);
  730. return 0;
  731. }
  732. static int
  733. store_pwm_enable(struct device *dev, struct w83627ehf_data *data, int channel,
  734. long val)
  735. {
  736. u16 reg;
  737. if (!val || val < 0 ||
  738. (val > 4 && val != data->pwm_enable_orig[channel]))
  739. return -EINVAL;
  740. mutex_lock(&data->update_lock);
  741. data->pwm_enable[channel] = val;
  742. reg = w83627ehf_read_value(data,
  743. W83627EHF_REG_PWM_ENABLE[channel]);
  744. reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]);
  745. reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[channel];
  746. w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
  747. reg);
  748. mutex_unlock(&data->update_lock);
  749. return 0;
  750. }
  751. #define show_tol_temp(reg) \
  752. static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
  753. char *buf) \
  754. { \
  755. struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
  756. struct sensor_device_attribute *sensor_attr = \
  757. to_sensor_dev_attr(attr); \
  758. int nr = sensor_attr->index; \
  759. return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
  760. }
  761. show_tol_temp(tolerance)
  762. show_tol_temp(target_temp)
  763. static ssize_t
  764. store_target_temp(struct device *dev, struct device_attribute *attr,
  765. const char *buf, size_t count)
  766. {
  767. struct w83627ehf_data *data = dev_get_drvdata(dev);
  768. struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
  769. int nr = sensor_attr->index;
  770. long val;
  771. int err;
  772. err = kstrtol(buf, 10, &val);
  773. if (err < 0)
  774. return err;
  775. val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
  776. mutex_lock(&data->update_lock);
  777. data->target_temp[nr] = val;
  778. w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
  779. mutex_unlock(&data->update_lock);
  780. return count;
  781. }
  782. static ssize_t
  783. store_tolerance(struct device *dev, struct device_attribute *attr,
  784. const char *buf, size_t count)
  785. {
  786. struct w83627ehf_data *data = dev_get_drvdata(dev);
  787. struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
  788. int nr = sensor_attr->index;
  789. u16 reg;
  790. long val;
  791. int err;
  792. err = kstrtol(buf, 10, &val);
  793. if (err < 0)
  794. return err;
  795. /* Limit the temp to 0C - 15C */
  796. val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
  797. mutex_lock(&data->update_lock);
  798. reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
  799. if (nr == 1)
  800. reg = (reg & 0x0f) | (val << 4);
  801. else
  802. reg = (reg & 0xf0) | val;
  803. w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
  804. data->tolerance[nr] = val;
  805. mutex_unlock(&data->update_lock);
  806. return count;
  807. }
  808. static SENSOR_DEVICE_ATTR(pwm1_target, 0644, show_target_temp,
  809. store_target_temp, 0);
  810. static SENSOR_DEVICE_ATTR(pwm2_target, 0644, show_target_temp,
  811. store_target_temp, 1);
  812. static SENSOR_DEVICE_ATTR(pwm3_target, 0644, show_target_temp,
  813. store_target_temp, 2);
  814. static SENSOR_DEVICE_ATTR(pwm4_target, 0644, show_target_temp,
  815. store_target_temp, 3);
  816. static SENSOR_DEVICE_ATTR(pwm1_tolerance, 0644, show_tolerance,
  817. store_tolerance, 0);
  818. static SENSOR_DEVICE_ATTR(pwm2_tolerance, 0644, show_tolerance,
  819. store_tolerance, 1);
  820. static SENSOR_DEVICE_ATTR(pwm3_tolerance, 0644, show_tolerance,
  821. store_tolerance, 2);
  822. static SENSOR_DEVICE_ATTR(pwm4_tolerance, 0644, show_tolerance,
  823. store_tolerance, 3);
  824. /* Smart Fan registers */
  825. #define fan_functions(reg, REG) \
  826. static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
  827. char *buf) \
  828. { \
  829. struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
  830. struct sensor_device_attribute *sensor_attr = \
  831. to_sensor_dev_attr(attr); \
  832. int nr = sensor_attr->index; \
  833. return sprintf(buf, "%d\n", data->reg[nr]); \
  834. } \
  835. static ssize_t \
  836. store_##reg(struct device *dev, struct device_attribute *attr, \
  837. const char *buf, size_t count) \
  838. { \
  839. struct w83627ehf_data *data = dev_get_drvdata(dev); \
  840. struct sensor_device_attribute *sensor_attr = \
  841. to_sensor_dev_attr(attr); \
  842. int nr = sensor_attr->index; \
  843. unsigned long val; \
  844. int err; \
  845. err = kstrtoul(buf, 10, &val); \
  846. if (err < 0) \
  847. return err; \
  848. val = clamp_val(val, 1, 255); \
  849. mutex_lock(&data->update_lock); \
  850. data->reg[nr] = val; \
  851. w83627ehf_write_value(data, REG[nr], val); \
  852. mutex_unlock(&data->update_lock); \
  853. return count; \
  854. }
  855. fan_functions(fan_start_output, W83627EHF_REG_FAN_START_OUTPUT)
  856. fan_functions(fan_stop_output, W83627EHF_REG_FAN_STOP_OUTPUT)
  857. fan_functions(fan_max_output, data->REG_FAN_MAX_OUTPUT)
  858. fan_functions(fan_step_output, data->REG_FAN_STEP_OUTPUT)
  859. #define fan_time_functions(reg, REG) \
  860. static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
  861. char *buf) \
  862. { \
  863. struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
  864. struct sensor_device_attribute *sensor_attr = \
  865. to_sensor_dev_attr(attr); \
  866. int nr = sensor_attr->index; \
  867. return sprintf(buf, "%d\n", \
  868. step_time_from_reg(data->reg[nr], \
  869. data->pwm_mode[nr])); \
  870. } \
  871. \
  872. static ssize_t \
  873. store_##reg(struct device *dev, struct device_attribute *attr, \
  874. const char *buf, size_t count) \
  875. { \
  876. struct w83627ehf_data *data = dev_get_drvdata(dev); \
  877. struct sensor_device_attribute *sensor_attr = \
  878. to_sensor_dev_attr(attr); \
  879. int nr = sensor_attr->index; \
  880. unsigned long val; \
  881. int err; \
  882. err = kstrtoul(buf, 10, &val); \
  883. if (err < 0) \
  884. return err; \
  885. val = step_time_to_reg(val, data->pwm_mode[nr]); \
  886. mutex_lock(&data->update_lock); \
  887. data->reg[nr] = val; \
  888. w83627ehf_write_value(data, REG[nr], val); \
  889. mutex_unlock(&data->update_lock); \
  890. return count; \
  891. } \
  892. fan_time_functions(fan_stop_time, W83627EHF_REG_FAN_STOP_TIME)
  893. static SENSOR_DEVICE_ATTR(pwm4_stop_time, 0644, show_fan_stop_time,
  894. store_fan_stop_time, 3);
  895. static SENSOR_DEVICE_ATTR(pwm4_start_output, 0644, show_fan_start_output,
  896. store_fan_start_output, 3);
  897. static SENSOR_DEVICE_ATTR(pwm4_stop_output, 0644, show_fan_stop_output,
  898. store_fan_stop_output, 3);
  899. static SENSOR_DEVICE_ATTR(pwm4_max_output, 0644, show_fan_max_output,
  900. store_fan_max_output, 3);
  901. static SENSOR_DEVICE_ATTR(pwm4_step_output, 0644, show_fan_step_output,
  902. store_fan_step_output, 3);
  903. static SENSOR_DEVICE_ATTR(pwm3_stop_time, 0644, show_fan_stop_time,
  904. store_fan_stop_time, 2);
  905. static SENSOR_DEVICE_ATTR(pwm3_start_output, 0644, show_fan_start_output,
  906. store_fan_start_output, 2);
  907. static SENSOR_DEVICE_ATTR(pwm3_stop_output, 0644, show_fan_stop_output,
  908. store_fan_stop_output, 2);
  909. static SENSOR_DEVICE_ATTR(pwm1_stop_time, 0644, show_fan_stop_time,
  910. store_fan_stop_time, 0);
  911. static SENSOR_DEVICE_ATTR(pwm2_stop_time, 0644, show_fan_stop_time,
  912. store_fan_stop_time, 1);
  913. static SENSOR_DEVICE_ATTR(pwm1_start_output, 0644, show_fan_start_output,
  914. store_fan_start_output, 0);
  915. static SENSOR_DEVICE_ATTR(pwm2_start_output, 0644, show_fan_start_output,
  916. store_fan_start_output, 1);
  917. static SENSOR_DEVICE_ATTR(pwm1_stop_output, 0644, show_fan_stop_output,
  918. store_fan_stop_output, 0);
  919. static SENSOR_DEVICE_ATTR(pwm2_stop_output, 0644, show_fan_stop_output,
  920. store_fan_stop_output, 1);
  921. /*
  922. * pwm1 and pwm3 don't support max and step settings on all chips.
  923. * Need to check support while generating/removing attribute files.
  924. */
  925. static SENSOR_DEVICE_ATTR(pwm1_max_output, 0644, show_fan_max_output,
  926. store_fan_max_output, 0);
  927. static SENSOR_DEVICE_ATTR(pwm1_step_output, 0644, show_fan_step_output,
  928. store_fan_step_output, 0);
  929. static SENSOR_DEVICE_ATTR(pwm2_max_output, 0644, show_fan_max_output,
  930. store_fan_max_output, 1);
  931. static SENSOR_DEVICE_ATTR(pwm2_step_output, 0644, show_fan_step_output,
  932. store_fan_step_output, 1);
  933. static SENSOR_DEVICE_ATTR(pwm3_max_output, 0644, show_fan_max_output,
  934. store_fan_max_output, 2);
  935. static SENSOR_DEVICE_ATTR(pwm3_step_output, 0644, show_fan_step_output,
  936. store_fan_step_output, 2);
  937. static ssize_t
  938. cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
  939. {
  940. struct w83627ehf_data *data = dev_get_drvdata(dev);
  941. return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
  942. }
  943. DEVICE_ATTR_RO(cpu0_vid);
  944. /* Case open detection */
  945. static int
  946. clear_caseopen(struct device *dev, struct w83627ehf_data *data, int channel,
  947. long val)
  948. {
  949. const u16 mask = 0x80;
  950. u16 reg;
  951. if (val != 0 || channel != 0)
  952. return -EINVAL;
  953. mutex_lock(&data->update_lock);
  954. reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
  955. w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
  956. w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
  957. data->valid = 0; /* Force cache refresh */
  958. mutex_unlock(&data->update_lock);
  959. return 0;
  960. }
  961. static umode_t w83627ehf_attrs_visible(struct kobject *kobj,
  962. struct attribute *a, int n)
  963. {
  964. struct device *dev = container_of(kobj, struct device, kobj);
  965. struct w83627ehf_data *data = dev_get_drvdata(dev);
  966. struct device_attribute *devattr;
  967. struct sensor_device_attribute *sda;
  968. devattr = container_of(a, struct device_attribute, attr);
  969. /* Not sensor */
  970. if (devattr->show == cpu0_vid_show && data->have_vid)
  971. return a->mode;
  972. sda = (struct sensor_device_attribute *)devattr;
  973. if (sda->index < 2 &&
  974. (devattr->show == show_fan_stop_time ||
  975. devattr->show == show_fan_start_output ||
  976. devattr->show == show_fan_stop_output))
  977. return a->mode;
  978. if (sda->index < 3 &&
  979. (devattr->show == show_fan_max_output ||
  980. devattr->show == show_fan_step_output) &&
  981. data->REG_FAN_STEP_OUTPUT &&
  982. data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff)
  983. return a->mode;
  984. /* if fan3 and fan4 are enabled create the files for them */
  985. if (sda->index == 2 &&
  986. (data->has_fan & (1 << 2)) && data->pwm_num >= 3 &&
  987. (devattr->show == show_fan_stop_time ||
  988. devattr->show == show_fan_start_output ||
  989. devattr->show == show_fan_stop_output))
  990. return a->mode;
  991. if (sda->index == 3 &&
  992. (data->has_fan & (1 << 3)) && data->pwm_num >= 4 &&
  993. (devattr->show == show_fan_stop_time ||
  994. devattr->show == show_fan_start_output ||
  995. devattr->show == show_fan_stop_output ||
  996. devattr->show == show_fan_max_output ||
  997. devattr->show == show_fan_step_output))
  998. return a->mode;
  999. if ((devattr->show == show_target_temp ||
  1000. devattr->show == show_tolerance) &&
  1001. (data->has_fan & (1 << sda->index)) &&
  1002. sda->index < data->pwm_num)
  1003. return a->mode;
  1004. return 0;
  1005. }
  1006. /* These groups handle non-standard attributes used in this device */
  1007. static struct attribute *w83627ehf_attrs[] = {
  1008. &sensor_dev_attr_pwm1_stop_time.dev_attr.attr,
  1009. &sensor_dev_attr_pwm1_start_output.dev_attr.attr,
  1010. &sensor_dev_attr_pwm1_stop_output.dev_attr.attr,
  1011. &sensor_dev_attr_pwm1_max_output.dev_attr.attr,
  1012. &sensor_dev_attr_pwm1_step_output.dev_attr.attr,
  1013. &sensor_dev_attr_pwm1_target.dev_attr.attr,
  1014. &sensor_dev_attr_pwm1_tolerance.dev_attr.attr,
  1015. &sensor_dev_attr_pwm2_stop_time.dev_attr.attr,
  1016. &sensor_dev_attr_pwm2_start_output.dev_attr.attr,
  1017. &sensor_dev_attr_pwm2_stop_output.dev_attr.attr,
  1018. &sensor_dev_attr_pwm2_max_output.dev_attr.attr,
  1019. &sensor_dev_attr_pwm2_step_output.dev_attr.attr,
  1020. &sensor_dev_attr_pwm2_target.dev_attr.attr,
  1021. &sensor_dev_attr_pwm2_tolerance.dev_attr.attr,
  1022. &sensor_dev_attr_pwm3_stop_time.dev_attr.attr,
  1023. &sensor_dev_attr_pwm3_start_output.dev_attr.attr,
  1024. &sensor_dev_attr_pwm3_stop_output.dev_attr.attr,
  1025. &sensor_dev_attr_pwm3_max_output.dev_attr.attr,
  1026. &sensor_dev_attr_pwm3_step_output.dev_attr.attr,
  1027. &sensor_dev_attr_pwm3_target.dev_attr.attr,
  1028. &sensor_dev_attr_pwm3_tolerance.dev_attr.attr,
  1029. &sensor_dev_attr_pwm4_stop_time.dev_attr.attr,
  1030. &sensor_dev_attr_pwm4_start_output.dev_attr.attr,
  1031. &sensor_dev_attr_pwm4_stop_output.dev_attr.attr,
  1032. &sensor_dev_attr_pwm4_max_output.dev_attr.attr,
  1033. &sensor_dev_attr_pwm4_step_output.dev_attr.attr,
  1034. &sensor_dev_attr_pwm4_target.dev_attr.attr,
  1035. &sensor_dev_attr_pwm4_tolerance.dev_attr.attr,
  1036. &dev_attr_cpu0_vid.attr,
  1037. NULL
  1038. };
  1039. static const struct attribute_group w83627ehf_group = {
  1040. .attrs = w83627ehf_attrs,
  1041. .is_visible = w83627ehf_attrs_visible,
  1042. };
  1043. static const struct attribute_group *w83627ehf_groups[] = {
  1044. &w83627ehf_group,
  1045. NULL
  1046. };
  1047. /*
  1048. * Driver and device management
  1049. */
  1050. /* Get the monitoring functions started */
  1051. static inline void w83627ehf_init_device(struct w83627ehf_data *data,
  1052. enum kinds kind)
  1053. {
  1054. int i;
  1055. u8 tmp, diode;
  1056. /* Start monitoring is needed */
  1057. tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
  1058. if (!(tmp & 0x01))
  1059. w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
  1060. tmp | 0x01);
  1061. /* Enable temperature sensors if needed */
  1062. for (i = 0; i < NUM_REG_TEMP; i++) {
  1063. if (!(data->have_temp & (1 << i)))
  1064. continue;
  1065. if (!data->reg_temp_config[i])
  1066. continue;
  1067. tmp = w83627ehf_read_value(data,
  1068. data->reg_temp_config[i]);
  1069. if (tmp & 0x01)
  1070. w83627ehf_write_value(data,
  1071. data->reg_temp_config[i],
  1072. tmp & 0xfe);
  1073. }
  1074. /* Enable VBAT monitoring if needed */
  1075. tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
  1076. if (!(tmp & 0x01))
  1077. w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
  1078. /* Get thermal sensor types */
  1079. switch (kind) {
  1080. case w83627ehf:
  1081. diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
  1082. break;
  1083. case w83627uhg:
  1084. diode = 0x00;
  1085. break;
  1086. default:
  1087. diode = 0x70;
  1088. }
  1089. for (i = 0; i < 3; i++) {
  1090. const char *label = NULL;
  1091. if (data->temp_label)
  1092. label = data->temp_label[data->temp_src[i]];
  1093. /* Digital source overrides analog type */
  1094. if (label && strncmp(label, "PECI", 4) == 0)
  1095. data->temp_type[i] = 6;
  1096. else if (label && strncmp(label, "AMD", 3) == 0)
  1097. data->temp_type[i] = 5;
  1098. else if ((tmp & (0x02 << i)))
  1099. data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
  1100. else
  1101. data->temp_type[i] = 4; /* thermistor */
  1102. }
  1103. }
  1104. static void
  1105. w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
  1106. {
  1107. int i;
  1108. for (i = 0; i < n_temp; i++) {
  1109. data->reg_temp[i] = W83627EHF_REG_TEMP[i];
  1110. data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
  1111. data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
  1112. data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
  1113. }
  1114. }
  1115. static void
  1116. w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
  1117. struct w83627ehf_data *data)
  1118. {
  1119. int fan3pin, fan4pin, fan5pin, regval;
  1120. /* The W83627UHG is simple, only two fan inputs, no config */
  1121. if (sio_data->kind == w83627uhg) {
  1122. data->has_fan = 0x03; /* fan1 and fan2 */
  1123. data->has_fan_min = 0x03;
  1124. return;
  1125. }
  1126. /* fan4 and fan5 share some pins with the GPIO and serial flash */
  1127. if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
  1128. fan3pin = 1;
  1129. fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
  1130. fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
  1131. } else {
  1132. fan3pin = 1;
  1133. fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
  1134. fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
  1135. }
  1136. data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
  1137. data->has_fan |= (fan3pin << 2);
  1138. data->has_fan_min |= (fan3pin << 2);
  1139. /*
  1140. * It looks like fan4 and fan5 pins can be alternatively used
  1141. * as fan on/off switches, but fan5 control is write only :/
  1142. * We assume that if the serial interface is disabled, designers
  1143. * connected fan5 as input unless they are emitting log 1, which
  1144. * is not the default.
  1145. */
  1146. regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
  1147. if ((regval & (1 << 2)) && fan4pin) {
  1148. data->has_fan |= (1 << 3);
  1149. data->has_fan_min |= (1 << 3);
  1150. }
  1151. if (!(regval & (1 << 1)) && fan5pin) {
  1152. data->has_fan |= (1 << 4);
  1153. data->has_fan_min |= (1 << 4);
  1154. }
  1155. }
  1156. static umode_t
  1157. w83627ehf_is_visible(const void *drvdata, enum hwmon_sensor_types type,
  1158. u32 attr, int channel)
  1159. {
  1160. const struct w83627ehf_data *data = drvdata;
  1161. switch (type) {
  1162. case hwmon_temp:
  1163. /* channel 0.., name 1.. */
  1164. if (!(data->have_temp & (1 << channel)))
  1165. return 0;
  1166. if (attr == hwmon_temp_input)
  1167. return 0444;
  1168. if (attr == hwmon_temp_label) {
  1169. if (data->temp_label)
  1170. return 0444;
  1171. return 0;
  1172. }
  1173. if (channel == 2 && data->temp3_val_only)
  1174. return 0;
  1175. if (attr == hwmon_temp_max) {
  1176. if (data->reg_temp_over[channel])
  1177. return 0644;
  1178. else
  1179. return 0;
  1180. }
  1181. if (attr == hwmon_temp_max_hyst) {
  1182. if (data->reg_temp_hyst[channel])
  1183. return 0644;
  1184. else
  1185. return 0;
  1186. }
  1187. if (channel > 2)
  1188. return 0;
  1189. if (attr == hwmon_temp_alarm || attr == hwmon_temp_type)
  1190. return 0444;
  1191. if (attr == hwmon_temp_offset) {
  1192. if (data->have_temp_offset & (1 << channel))
  1193. return 0644;
  1194. else
  1195. return 0;
  1196. }
  1197. break;
  1198. case hwmon_fan:
  1199. /* channel 0.., name 1.. */
  1200. if (!(data->has_fan & (1 << channel)))
  1201. return 0;
  1202. if (attr == hwmon_fan_input || attr == hwmon_fan_alarm)
  1203. return 0444;
  1204. if (attr == hwmon_fan_div) {
  1205. return 0444;
  1206. }
  1207. if (attr == hwmon_fan_min) {
  1208. if (data->has_fan_min & (1 << channel))
  1209. return 0644;
  1210. else
  1211. return 0;
  1212. }
  1213. break;
  1214. case hwmon_in:
  1215. /* channel 0.., name 0.. */
  1216. if (channel >= data->in_num)
  1217. return 0;
  1218. if (channel == 6 && data->in6_skip)
  1219. return 0;
  1220. if (attr == hwmon_in_alarm || attr == hwmon_in_input)
  1221. return 0444;
  1222. if (attr == hwmon_in_min || attr == hwmon_in_max)
  1223. return 0644;
  1224. break;
  1225. case hwmon_pwm:
  1226. /* channel 0.., name 1.. */
  1227. if (!(data->has_fan & (1 << channel)) ||
  1228. channel >= data->pwm_num)
  1229. return 0;
  1230. if (attr == hwmon_pwm_mode || attr == hwmon_pwm_enable ||
  1231. attr == hwmon_pwm_input)
  1232. return 0644;
  1233. break;
  1234. case hwmon_intrusion:
  1235. return 0644;
  1236. default: /* Shouldn't happen */
  1237. return 0;
  1238. }
  1239. return 0; /* Shouldn't happen */
  1240. }
  1241. static int
  1242. w83627ehf_do_read_temp(struct w83627ehf_data *data, u32 attr,
  1243. int channel, long *val)
  1244. {
  1245. switch (attr) {
  1246. case hwmon_temp_input:
  1247. *val = LM75_TEMP_FROM_REG(data->temp[channel]);
  1248. return 0;
  1249. case hwmon_temp_max:
  1250. *val = LM75_TEMP_FROM_REG(data->temp_max[channel]);
  1251. return 0;
  1252. case hwmon_temp_max_hyst:
  1253. *val = LM75_TEMP_FROM_REG(data->temp_max_hyst[channel]);
  1254. return 0;
  1255. case hwmon_temp_offset:
  1256. *val = data->temp_offset[channel] * 1000;
  1257. return 0;
  1258. case hwmon_temp_type:
  1259. *val = (int)data->temp_type[channel];
  1260. return 0;
  1261. case hwmon_temp_alarm:
  1262. if (channel < 3) {
  1263. int bit[] = { 4, 5, 13 };
  1264. *val = (data->alarms >> bit[channel]) & 1;
  1265. return 0;
  1266. }
  1267. break;
  1268. default:
  1269. break;
  1270. }
  1271. return -EOPNOTSUPP;
  1272. }
  1273. static int
  1274. w83627ehf_do_read_in(struct w83627ehf_data *data, u32 attr,
  1275. int channel, long *val)
  1276. {
  1277. switch (attr) {
  1278. case hwmon_in_input:
  1279. *val = in_from_reg(data->in[channel], channel, data->scale_in);
  1280. return 0;
  1281. case hwmon_in_min:
  1282. *val = in_from_reg(data->in_min[channel], channel,
  1283. data->scale_in);
  1284. return 0;
  1285. case hwmon_in_max:
  1286. *val = in_from_reg(data->in_max[channel], channel,
  1287. data->scale_in);
  1288. return 0;
  1289. case hwmon_in_alarm:
  1290. if (channel < 10) {
  1291. int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 };
  1292. *val = (data->alarms >> bit[channel]) & 1;
  1293. return 0;
  1294. }
  1295. break;
  1296. default:
  1297. break;
  1298. }
  1299. return -EOPNOTSUPP;
  1300. }
  1301. static int
  1302. w83627ehf_do_read_fan(struct w83627ehf_data *data, u32 attr,
  1303. int channel, long *val)
  1304. {
  1305. switch (attr) {
  1306. case hwmon_fan_input:
  1307. *val = data->rpm[channel];
  1308. return 0;
  1309. case hwmon_fan_min:
  1310. *val = fan_from_reg8(data->fan_min[channel],
  1311. data->fan_div[channel]);
  1312. return 0;
  1313. case hwmon_fan_div:
  1314. *val = div_from_reg(data->fan_div[channel]);
  1315. return 0;
  1316. case hwmon_fan_alarm:
  1317. if (channel < 5) {
  1318. int bit[] = { 6, 7, 11, 10, 23 };
  1319. *val = (data->alarms >> bit[channel]) & 1;
  1320. return 0;
  1321. }
  1322. break;
  1323. default:
  1324. break;
  1325. }
  1326. return -EOPNOTSUPP;
  1327. }
  1328. static int
  1329. w83627ehf_do_read_pwm(struct w83627ehf_data *data, u32 attr,
  1330. int channel, long *val)
  1331. {
  1332. switch (attr) {
  1333. case hwmon_pwm_input:
  1334. *val = data->pwm[channel];
  1335. return 0;
  1336. case hwmon_pwm_enable:
  1337. *val = data->pwm_enable[channel];
  1338. return 0;
  1339. case hwmon_pwm_mode:
  1340. *val = data->pwm_enable[channel];
  1341. return 0;
  1342. default:
  1343. break;
  1344. }
  1345. return -EOPNOTSUPP;
  1346. }
  1347. static int
  1348. w83627ehf_do_read_intrusion(struct w83627ehf_data *data, u32 attr,
  1349. int channel, long *val)
  1350. {
  1351. if (attr != hwmon_intrusion_alarm || channel != 0)
  1352. return -EOPNOTSUPP; /* shouldn't happen */
  1353. *val = !!(data->caseopen & 0x10);
  1354. return 0;
  1355. }
  1356. static int
  1357. w83627ehf_read(struct device *dev, enum hwmon_sensor_types type,
  1358. u32 attr, int channel, long *val)
  1359. {
  1360. struct w83627ehf_data *data = w83627ehf_update_device(dev->parent);
  1361. switch (type) {
  1362. case hwmon_fan:
  1363. return w83627ehf_do_read_fan(data, attr, channel, val);
  1364. case hwmon_in:
  1365. return w83627ehf_do_read_in(data, attr, channel, val);
  1366. case hwmon_pwm:
  1367. return w83627ehf_do_read_pwm(data, attr, channel, val);
  1368. case hwmon_temp:
  1369. return w83627ehf_do_read_temp(data, attr, channel, val);
  1370. case hwmon_intrusion:
  1371. return w83627ehf_do_read_intrusion(data, attr, channel, val);
  1372. default:
  1373. break;
  1374. }
  1375. return -EOPNOTSUPP;
  1376. }
  1377. static int
  1378. w83627ehf_read_string(struct device *dev, enum hwmon_sensor_types type,
  1379. u32 attr, int channel, const char **str)
  1380. {
  1381. struct w83627ehf_data *data = dev_get_drvdata(dev);
  1382. switch (type) {
  1383. case hwmon_temp:
  1384. if (attr == hwmon_temp_label) {
  1385. *str = data->temp_label[data->temp_src[channel]];
  1386. return 0;
  1387. }
  1388. break;
  1389. default:
  1390. break;
  1391. }
  1392. /* Nothing else should be read as a string */
  1393. return -EOPNOTSUPP;
  1394. }
  1395. static int
  1396. w83627ehf_write(struct device *dev, enum hwmon_sensor_types type,
  1397. u32 attr, int channel, long val)
  1398. {
  1399. struct w83627ehf_data *data = dev_get_drvdata(dev);
  1400. if (type == hwmon_in && attr == hwmon_in_min)
  1401. return store_in_min(dev, data, channel, val);
  1402. if (type == hwmon_in && attr == hwmon_in_max)
  1403. return store_in_max(dev, data, channel, val);
  1404. if (type == hwmon_fan && attr == hwmon_fan_min)
  1405. return store_fan_min(dev, data, channel, val);
  1406. if (type == hwmon_temp && attr == hwmon_temp_max)
  1407. return store_temp_max(dev, data, channel, val);
  1408. if (type == hwmon_temp && attr == hwmon_temp_max_hyst)
  1409. return store_temp_max_hyst(dev, data, channel, val);
  1410. if (type == hwmon_temp && attr == hwmon_temp_offset)
  1411. return store_temp_offset(dev, data, channel, val);
  1412. if (type == hwmon_pwm && attr == hwmon_pwm_mode)
  1413. return store_pwm_mode(dev, data, channel, val);
  1414. if (type == hwmon_pwm && attr == hwmon_pwm_enable)
  1415. return store_pwm_enable(dev, data, channel, val);
  1416. if (type == hwmon_pwm && attr == hwmon_pwm_input)
  1417. return store_pwm(dev, data, channel, val);
  1418. if (type == hwmon_intrusion && attr == hwmon_intrusion_alarm)
  1419. return clear_caseopen(dev, data, channel, val);
  1420. return -EOPNOTSUPP;
  1421. }
  1422. static const struct hwmon_ops w83627ehf_ops = {
  1423. .is_visible = w83627ehf_is_visible,
  1424. .read = w83627ehf_read,
  1425. .read_string = w83627ehf_read_string,
  1426. .write = w83627ehf_write,
  1427. };
  1428. static const struct hwmon_channel_info *w83627ehf_info[] = {
  1429. HWMON_CHANNEL_INFO(fan,
  1430. HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
  1431. HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
  1432. HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
  1433. HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
  1434. HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN),
  1435. HWMON_CHANNEL_INFO(in,
  1436. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1437. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1438. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1439. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1440. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1441. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1442. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1443. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1444. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
  1445. HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN),
  1446. HWMON_CHANNEL_INFO(pwm,
  1447. HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
  1448. HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
  1449. HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
  1450. HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE),
  1451. HWMON_CHANNEL_INFO(temp,
  1452. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1453. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1454. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1455. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1456. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1457. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1458. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1459. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1460. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1461. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1462. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1463. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1464. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1465. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1466. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1467. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
  1468. HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
  1469. HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE),
  1470. HWMON_CHANNEL_INFO(intrusion,
  1471. HWMON_INTRUSION_ALARM),
  1472. NULL
  1473. };
  1474. static const struct hwmon_chip_info w83627ehf_chip_info = {
  1475. .ops = &w83627ehf_ops,
  1476. .info = w83627ehf_info,
  1477. };
  1478. static int w83627ehf_probe(struct platform_device *pdev)
  1479. {
  1480. struct device *dev = &pdev->dev;
  1481. struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
  1482. struct w83627ehf_data *data;
  1483. struct resource *res;
  1484. u8 en_vrm10;
  1485. int i, err = 0;
  1486. struct device *hwmon_dev;
  1487. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  1488. if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
  1489. err = -EBUSY;
  1490. dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
  1491. (unsigned long)res->start,
  1492. (unsigned long)res->start + IOREGION_LENGTH - 1);
  1493. goto exit;
  1494. }
  1495. data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
  1496. GFP_KERNEL);
  1497. if (!data) {
  1498. err = -ENOMEM;
  1499. goto exit_release;
  1500. }
  1501. data->addr = res->start;
  1502. mutex_init(&data->lock);
  1503. mutex_init(&data->update_lock);
  1504. data->name = w83627ehf_device_names[sio_data->kind];
  1505. data->bank = 0xff; /* Force initial bank selection */
  1506. platform_set_drvdata(pdev, data);
  1507. /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
  1508. data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
  1509. /* 667HG has 3 pwms, and 627UHG has only 2 */
  1510. switch (sio_data->kind) {
  1511. default:
  1512. data->pwm_num = 4;
  1513. break;
  1514. case w83667hg:
  1515. case w83667hg_b:
  1516. data->pwm_num = 3;
  1517. break;
  1518. case w83627uhg:
  1519. data->pwm_num = 2;
  1520. break;
  1521. }
  1522. /* Default to 3 temperature inputs, code below will adjust as needed */
  1523. data->have_temp = 0x07;
  1524. /* Deal with temperature register setup first. */
  1525. if (sio_data->kind == w83667hg_b) {
  1526. u8 reg;
  1527. w83627ehf_set_temp_reg_ehf(data, 4);
  1528. /*
  1529. * Temperature sources are selected with bank 0, registers 0x49
  1530. * and 0x4a.
  1531. */
  1532. reg = w83627ehf_read_value(data, 0x4a);
  1533. data->temp_src[0] = reg >> 5;
  1534. reg = w83627ehf_read_value(data, 0x49);
  1535. data->temp_src[1] = reg & 0x07;
  1536. data->temp_src[2] = (reg >> 4) & 0x07;
  1537. /*
  1538. * W83667HG-B has another temperature register at 0x7e.
  1539. * The temperature source is selected with register 0x7d.
  1540. * Support it if the source differs from already reported
  1541. * sources.
  1542. */
  1543. reg = w83627ehf_read_value(data, 0x7d);
  1544. reg &= 0x07;
  1545. if (reg != data->temp_src[0] && reg != data->temp_src[1]
  1546. && reg != data->temp_src[2]) {
  1547. data->temp_src[3] = reg;
  1548. data->have_temp |= 1 << 3;
  1549. }
  1550. /*
  1551. * Chip supports either AUXTIN or VIN3. Try to find out which
  1552. * one.
  1553. */
  1554. reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
  1555. if (data->temp_src[2] == 2 && (reg & 0x01))
  1556. data->have_temp &= ~(1 << 2);
  1557. if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
  1558. || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
  1559. data->in6_skip = 1;
  1560. data->temp_label = w83667hg_b_temp_label;
  1561. data->have_temp_offset = data->have_temp & 0x07;
  1562. for (i = 0; i < 3; i++) {
  1563. if (data->temp_src[i] > 2)
  1564. data->have_temp_offset &= ~(1 << i);
  1565. }
  1566. } else if (sio_data->kind == w83627uhg) {
  1567. u8 reg;
  1568. w83627ehf_set_temp_reg_ehf(data, 3);
  1569. /*
  1570. * Temperature sources for temp2 and temp3 are selected with
  1571. * bank 0, registers 0x49 and 0x4a.
  1572. */
  1573. data->temp_src[0] = 0; /* SYSTIN */
  1574. reg = w83627ehf_read_value(data, 0x49) & 0x07;
  1575. /* Adjust to have the same mapping as other source registers */
  1576. if (reg == 0)
  1577. data->temp_src[1] = 1;
  1578. else if (reg >= 2 && reg <= 5)
  1579. data->temp_src[1] = reg + 2;
  1580. else /* should never happen */
  1581. data->have_temp &= ~(1 << 1);
  1582. reg = w83627ehf_read_value(data, 0x4a);
  1583. data->temp_src[2] = reg >> 5;
  1584. /*
  1585. * Skip temp3 if source is invalid or the same as temp1
  1586. * or temp2.
  1587. */
  1588. if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
  1589. data->temp_src[2] == data->temp_src[0] ||
  1590. ((data->have_temp & (1 << 1)) &&
  1591. data->temp_src[2] == data->temp_src[1]))
  1592. data->have_temp &= ~(1 << 2);
  1593. else
  1594. data->temp3_val_only = 1; /* No limit regs */
  1595. data->in6_skip = 1; /* No VIN3 */
  1596. data->temp_label = w83667hg_b_temp_label;
  1597. data->have_temp_offset = data->have_temp & 0x03;
  1598. for (i = 0; i < 3; i++) {
  1599. if (data->temp_src[i] > 1)
  1600. data->have_temp_offset &= ~(1 << i);
  1601. }
  1602. } else {
  1603. w83627ehf_set_temp_reg_ehf(data, 3);
  1604. /* Temperature sources are fixed */
  1605. if (sio_data->kind == w83667hg) {
  1606. u8 reg;
  1607. /*
  1608. * Chip supports either AUXTIN or VIN3. Try to find
  1609. * out which one.
  1610. */
  1611. reg = w83627ehf_read_value(data,
  1612. W83627EHF_REG_TEMP_CONFIG[2]);
  1613. if (reg & 0x01)
  1614. data->have_temp &= ~(1 << 2);
  1615. else
  1616. data->in6_skip = 1;
  1617. }
  1618. data->have_temp_offset = data->have_temp & 0x07;
  1619. }
  1620. if (sio_data->kind == w83667hg_b) {
  1621. data->REG_FAN_MAX_OUTPUT =
  1622. W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
  1623. data->REG_FAN_STEP_OUTPUT =
  1624. W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
  1625. } else {
  1626. data->REG_FAN_MAX_OUTPUT =
  1627. W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
  1628. data->REG_FAN_STEP_OUTPUT =
  1629. W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
  1630. }
  1631. /* Setup input voltage scaling factors */
  1632. if (sio_data->kind == w83627uhg)
  1633. data->scale_in = scale_in_w83627uhg;
  1634. else
  1635. data->scale_in = scale_in_common;
  1636. /* Initialize the chip */
  1637. w83627ehf_init_device(data, sio_data->kind);
  1638. data->vrm = vid_which_vrm();
  1639. err = superio_enter(sio_data->sioreg);
  1640. if (err)
  1641. goto exit_release;
  1642. /* Read VID value */
  1643. if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
  1644. /*
  1645. * W83667HG has different pins for VID input and output, so
  1646. * we can get the VID input values directly at logical device D
  1647. * 0xe3.
  1648. */
  1649. superio_select(sio_data->sioreg, W83667HG_LD_VID);
  1650. data->vid = superio_inb(sio_data->sioreg, 0xe3);
  1651. data->have_vid = true;
  1652. } else if (sio_data->kind != w83627uhg) {
  1653. superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
  1654. if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
  1655. /*
  1656. * Set VID input sensibility if needed. In theory the
  1657. * BIOS should have set it, but in practice it's not
  1658. * always the case. We only do it for the W83627EHF/EHG
  1659. * because the W83627DHG is more complex in this
  1660. * respect.
  1661. */
  1662. if (sio_data->kind == w83627ehf) {
  1663. en_vrm10 = superio_inb(sio_data->sioreg,
  1664. SIO_REG_EN_VRM10);
  1665. if ((en_vrm10 & 0x08) && data->vrm == 90) {
  1666. dev_warn(dev,
  1667. "Setting VID input voltage to TTL\n");
  1668. superio_outb(sio_data->sioreg,
  1669. SIO_REG_EN_VRM10,
  1670. en_vrm10 & ~0x08);
  1671. } else if (!(en_vrm10 & 0x08)
  1672. && data->vrm == 100) {
  1673. dev_warn(dev,
  1674. "Setting VID input voltage to VRM10\n");
  1675. superio_outb(sio_data->sioreg,
  1676. SIO_REG_EN_VRM10,
  1677. en_vrm10 | 0x08);
  1678. }
  1679. }
  1680. data->vid = superio_inb(sio_data->sioreg,
  1681. SIO_REG_VID_DATA);
  1682. if (sio_data->kind == w83627ehf) /* 6 VID pins only */
  1683. data->vid &= 0x3f;
  1684. data->have_vid = true;
  1685. } else {
  1686. dev_info(dev,
  1687. "VID pins in output mode, CPU VID not available\n");
  1688. }
  1689. }
  1690. w83627ehf_check_fan_inputs(sio_data, data);
  1691. superio_exit(sio_data->sioreg);
  1692. /* Read fan clock dividers immediately */
  1693. w83627ehf_update_fan_div(data);
  1694. /* Read pwm data to save original values */
  1695. w83627ehf_update_pwm(data);
  1696. for (i = 0; i < data->pwm_num; i++)
  1697. data->pwm_enable_orig[i] = data->pwm_enable[i];
  1698. hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
  1699. data->name,
  1700. data,
  1701. &w83627ehf_chip_info,
  1702. w83627ehf_groups);
  1703. if (IS_ERR(hwmon_dev)) {
  1704. err = PTR_ERR(hwmon_dev);
  1705. goto exit_release;
  1706. }
  1707. return 0;
  1708. exit_release:
  1709. release_region(res->start, IOREGION_LENGTH);
  1710. exit:
  1711. return err;
  1712. }
  1713. static int w83627ehf_remove(struct platform_device *pdev)
  1714. {
  1715. struct w83627ehf_data *data = platform_get_drvdata(pdev);
  1716. release_region(data->addr, IOREGION_LENGTH);
  1717. return 0;
  1718. }
  1719. #ifdef CONFIG_PM
  1720. static int w83627ehf_suspend(struct device *dev)
  1721. {
  1722. struct w83627ehf_data *data = w83627ehf_update_device(dev);
  1723. mutex_lock(&data->update_lock);
  1724. data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
  1725. mutex_unlock(&data->update_lock);
  1726. return 0;
  1727. }
  1728. static int w83627ehf_resume(struct device *dev)
  1729. {
  1730. struct w83627ehf_data *data = dev_get_drvdata(dev);
  1731. int i;
  1732. mutex_lock(&data->update_lock);
  1733. data->bank = 0xff; /* Force initial bank selection */
  1734. /* Restore limits */
  1735. for (i = 0; i < data->in_num; i++) {
  1736. if ((i == 6) && data->in6_skip)
  1737. continue;
  1738. w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
  1739. data->in_min[i]);
  1740. w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
  1741. data->in_max[i]);
  1742. }
  1743. for (i = 0; i < 5; i++) {
  1744. if (!(data->has_fan_min & (1 << i)))
  1745. continue;
  1746. w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
  1747. data->fan_min[i]);
  1748. }
  1749. for (i = 0; i < NUM_REG_TEMP; i++) {
  1750. if (!(data->have_temp & (1 << i)))
  1751. continue;
  1752. if (data->reg_temp_over[i])
  1753. w83627ehf_write_temp(data, data->reg_temp_over[i],
  1754. data->temp_max[i]);
  1755. if (data->reg_temp_hyst[i])
  1756. w83627ehf_write_temp(data, data->reg_temp_hyst[i],
  1757. data->temp_max_hyst[i]);
  1758. if (i > 2)
  1759. continue;
  1760. if (data->have_temp_offset & (1 << i))
  1761. w83627ehf_write_value(data,
  1762. W83627EHF_REG_TEMP_OFFSET[i],
  1763. data->temp_offset[i]);
  1764. }
  1765. /* Restore other settings */
  1766. w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
  1767. /* Force re-reading all values */
  1768. data->valid = 0;
  1769. mutex_unlock(&data->update_lock);
  1770. return 0;
  1771. }
  1772. static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
  1773. .suspend = w83627ehf_suspend,
  1774. .resume = w83627ehf_resume,
  1775. .freeze = w83627ehf_suspend,
  1776. .restore = w83627ehf_resume,
  1777. };
  1778. #define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
  1779. #else
  1780. #define W83627EHF_DEV_PM_OPS NULL
  1781. #endif /* CONFIG_PM */
  1782. static struct platform_driver w83627ehf_driver = {
  1783. .driver = {
  1784. .name = DRVNAME,
  1785. .pm = W83627EHF_DEV_PM_OPS,
  1786. },
  1787. .probe = w83627ehf_probe,
  1788. .remove = w83627ehf_remove,
  1789. };
  1790. /* w83627ehf_find() looks for a '627 in the Super-I/O config space */
  1791. static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
  1792. struct w83627ehf_sio_data *sio_data)
  1793. {
  1794. static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
  1795. static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
  1796. static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
  1797. static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
  1798. static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
  1799. static const char sio_name_W83667HG[] __initconst = "W83667HG";
  1800. static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
  1801. u16 val;
  1802. const char *sio_name;
  1803. int err;
  1804. err = superio_enter(sioaddr);
  1805. if (err)
  1806. return err;
  1807. if (force_id)
  1808. val = force_id;
  1809. else
  1810. val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
  1811. | superio_inb(sioaddr, SIO_REG_DEVID + 1);
  1812. switch (val & SIO_ID_MASK) {
  1813. case SIO_W83627EHF_ID:
  1814. sio_data->kind = w83627ehf;
  1815. sio_name = sio_name_W83627EHF;
  1816. break;
  1817. case SIO_W83627EHG_ID:
  1818. sio_data->kind = w83627ehf;
  1819. sio_name = sio_name_W83627EHG;
  1820. break;
  1821. case SIO_W83627DHG_ID:
  1822. sio_data->kind = w83627dhg;
  1823. sio_name = sio_name_W83627DHG;
  1824. break;
  1825. case SIO_W83627DHG_P_ID:
  1826. sio_data->kind = w83627dhg_p;
  1827. sio_name = sio_name_W83627DHG_P;
  1828. break;
  1829. case SIO_W83627UHG_ID:
  1830. sio_data->kind = w83627uhg;
  1831. sio_name = sio_name_W83627UHG;
  1832. break;
  1833. case SIO_W83667HG_ID:
  1834. sio_data->kind = w83667hg;
  1835. sio_name = sio_name_W83667HG;
  1836. break;
  1837. case SIO_W83667HG_B_ID:
  1838. sio_data->kind = w83667hg_b;
  1839. sio_name = sio_name_W83667HG_B;
  1840. break;
  1841. default:
  1842. if (val != 0xffff)
  1843. pr_debug("unsupported chip ID: 0x%04x\n", val);
  1844. superio_exit(sioaddr);
  1845. return -ENODEV;
  1846. }
  1847. /* We have a known chip, find the HWM I/O address */
  1848. superio_select(sioaddr, W83627EHF_LD_HWM);
  1849. val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
  1850. | superio_inb(sioaddr, SIO_REG_ADDR + 1);
  1851. *addr = val & IOREGION_ALIGNMENT;
  1852. if (*addr == 0) {
  1853. pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
  1854. superio_exit(sioaddr);
  1855. return -ENODEV;
  1856. }
  1857. /* Activate logical device if needed */
  1858. val = superio_inb(sioaddr, SIO_REG_ENABLE);
  1859. if (!(val & 0x01)) {
  1860. pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
  1861. superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
  1862. }
  1863. superio_exit(sioaddr);
  1864. pr_info("Found %s chip at %#x\n", sio_name, *addr);
  1865. sio_data->sioreg = sioaddr;
  1866. return 0;
  1867. }
  1868. /*
  1869. * when Super-I/O functions move to a separate file, the Super-I/O
  1870. * bus will manage the lifetime of the device and this module will only keep
  1871. * track of the w83627ehf driver. But since we platform_device_alloc(), we
  1872. * must keep track of the device
  1873. */
  1874. static struct platform_device *pdev;
  1875. static int __init sensors_w83627ehf_init(void)
  1876. {
  1877. int err;
  1878. unsigned short address;
  1879. struct resource res;
  1880. struct w83627ehf_sio_data sio_data;
  1881. /*
  1882. * initialize sio_data->kind and sio_data->sioreg.
  1883. *
  1884. * when Super-I/O functions move to a separate file, the Super-I/O
  1885. * driver will probe 0x2e and 0x4e and auto-detect the presence of a
  1886. * w83627ehf hardware monitor, and call probe()
  1887. */
  1888. if (w83627ehf_find(0x2e, &address, &sio_data) &&
  1889. w83627ehf_find(0x4e, &address, &sio_data))
  1890. return -ENODEV;
  1891. err = platform_driver_register(&w83627ehf_driver);
  1892. if (err)
  1893. goto exit;
  1894. pdev = platform_device_alloc(DRVNAME, address);
  1895. if (!pdev) {
  1896. err = -ENOMEM;
  1897. pr_err("Device allocation failed\n");
  1898. goto exit_unregister;
  1899. }
  1900. err = platform_device_add_data(pdev, &sio_data,
  1901. sizeof(struct w83627ehf_sio_data));
  1902. if (err) {
  1903. pr_err("Platform data allocation failed\n");
  1904. goto exit_device_put;
  1905. }
  1906. memset(&res, 0, sizeof(res));
  1907. res.name = DRVNAME;
  1908. res.start = address + IOREGION_OFFSET;
  1909. res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
  1910. res.flags = IORESOURCE_IO;
  1911. err = acpi_check_resource_conflict(&res);
  1912. if (err)
  1913. goto exit_device_put;
  1914. err = platform_device_add_resources(pdev, &res, 1);
  1915. if (err) {
  1916. pr_err("Device resource addition failed (%d)\n", err);
  1917. goto exit_device_put;
  1918. }
  1919. /* platform_device_add calls probe() */
  1920. err = platform_device_add(pdev);
  1921. if (err) {
  1922. pr_err("Device addition failed (%d)\n", err);
  1923. goto exit_device_put;
  1924. }
  1925. return 0;
  1926. exit_device_put:
  1927. platform_device_put(pdev);
  1928. exit_unregister:
  1929. platform_driver_unregister(&w83627ehf_driver);
  1930. exit:
  1931. return err;
  1932. }
  1933. static void __exit sensors_w83627ehf_exit(void)
  1934. {
  1935. platform_device_unregister(pdev);
  1936. platform_driver_unregister(&w83627ehf_driver);
  1937. }
  1938. MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
  1939. MODULE_DESCRIPTION("W83627EHF driver");
  1940. MODULE_LICENSE("GPL");
  1941. module_init(sensors_w83627ehf_init);
  1942. module_exit(sensors_w83627ehf_exit);