npcm750-pwm-fan.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2014-2018 Nuvoton Technology corporation.
  3. #include <linux/clk.h>
  4. #include <linux/device.h>
  5. #include <linux/hwmon.h>
  6. #include <linux/hwmon-sysfs.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/sysfs.h>
  15. #include <linux/thermal.h>
  16. /* NPCM7XX PWM registers */
  17. #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
  18. #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
  19. #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
  20. #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
  21. #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
  22. (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
  23. #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \
  24. (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))
  25. #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \
  26. (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))
  27. #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)
  28. #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)
  29. #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)
  30. #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)
  31. #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)
  32. #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)
  33. #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)
  34. #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)
  35. #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)
  36. #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)
  37. #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)
  38. #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)
  39. #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)
  40. #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)
  41. /* Define the maximum PWM channel number */
  42. #define NPCM7XX_PWM_MAX_CHN_NUM 8
  43. #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
  44. #define NPCM7XX_PWM_MAX_MODULES 2
  45. /* Define the Counter Register, value = 100 for match 100% */
  46. #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255
  47. #define NPCM7XX_PWM_CMR_DEFAULT_NUM 255
  48. #define NPCM7XX_PWM_CMR_MAX 255
  49. /* default all PWM channels PRESCALE2 = 1 */
  50. #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4
  51. #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40
  52. #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400
  53. #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000
  54. #define PWM_OUTPUT_FREQ_25KHZ 25000
  55. #define PWN_CNT_DEFAULT 256
  56. #define MIN_PRESCALE1 2
  57. #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8
  58. #define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \
  59. NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \
  60. NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \
  61. NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)
  62. #define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
  63. NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
  64. NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
  65. NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
  66. /* NPCM7XX FAN Tacho registers */
  67. #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
  68. #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)
  69. #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)
  70. #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)
  71. #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)
  72. #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)
  73. #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)
  74. #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)
  75. #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)
  76. #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)
  77. #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)
  78. #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)
  79. #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)
  80. #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)
  81. #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)
  82. #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)
  83. #define NPCM7XX_FAN_TCKC_CLKX_NONE 0
  84. #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0)
  85. #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3)
  86. #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6)
  87. #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5)
  88. #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4)
  89. #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3)
  90. #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2)
  91. #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)
  92. #define NPCM7XX_FAN_TICLR_TFCLR BIT(5)
  93. #define NPCM7XX_FAN_TICLR_TECLR BIT(4)
  94. #define NPCM7XX_FAN_TICLR_TDCLR BIT(3)
  95. #define NPCM7XX_FAN_TICLR_TCCLR BIT(2)
  96. #define NPCM7XX_FAN_TICLR_TBCLR BIT(1)
  97. #define NPCM7XX_FAN_TICLR_TACLR BIT(0)
  98. #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)
  99. #define NPCM7XX_FAN_TIEN_TFIEN BIT(5)
  100. #define NPCM7XX_FAN_TIEN_TEIEN BIT(4)
  101. #define NPCM7XX_FAN_TIEN_TDIEN BIT(3)
  102. #define NPCM7XX_FAN_TIEN_TCIEN BIT(2)
  103. #define NPCM7XX_FAN_TIEN_TBIEN BIT(1)
  104. #define NPCM7XX_FAN_TIEN_TAIEN BIT(0)
  105. #define NPCM7XX_FAN_TICTRL_TFPND BIT(5)
  106. #define NPCM7XX_FAN_TICTRL_TEPND BIT(4)
  107. #define NPCM7XX_FAN_TICTRL_TDPND BIT(3)
  108. #define NPCM7XX_FAN_TICTRL_TCPND BIT(2)
  109. #define NPCM7XX_FAN_TICTRL_TBPND BIT(1)
  110. #define NPCM7XX_FAN_TICTRL_TAPND BIT(0)
  111. #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7)
  112. #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6)
  113. #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5)
  114. #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4)
  115. #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3)
  116. #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2)
  117. #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1)
  118. #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0)
  119. /* FAN General Definition */
  120. /* Define the maximum FAN channel number */
  121. #define NPCM7XX_FAN_MAX_MODULE 8
  122. #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2
  123. #define NPCM7XX_FAN_MAX_CHN_NUM 16
  124. /*
  125. * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
  126. * Timeout 94ms ~= 0x5000
  127. * (The minimum FAN speed could to support ~640RPM/pulse 1,
  128. * 320RPM/pulse 2, ...-- 10.6Hz)
  129. */
  130. #define NPCM7XX_FAN_TIMEOUT 0x5000
  131. #define NPCM7XX_FAN_TCNT 0xFFFF
  132. #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
  133. #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
  134. #define NPCM7XX_FAN_POLL_TIMER_200MS 200
  135. #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2
  136. #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0
  137. #define NPCM7XX_FAN_CLK_PRESCALE 255
  138. #define NPCM7XX_FAN_CMPA 0
  139. #define NPCM7XX_FAN_CMPB 1
  140. /* Obtain the fan number */
  141. #define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp))
  142. /* fan sample status */
  143. #define FAN_DISABLE 0xFF
  144. #define FAN_INIT 0x00
  145. #define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01
  146. #define FAN_ENOUGH_SAMPLE 0x02
  147. struct npcm7xx_fan_dev {
  148. u8 fan_st_flg;
  149. u8 fan_pls_per_rev;
  150. u16 fan_cnt;
  151. u32 fan_cnt_tmp;
  152. };
  153. struct npcm7xx_cooling_device {
  154. char name[THERMAL_NAME_LENGTH];
  155. struct npcm7xx_pwm_fan_data *data;
  156. struct thermal_cooling_device *tcdev;
  157. int pwm_port;
  158. u8 *cooling_levels;
  159. u8 max_state;
  160. u8 cur_state;
  161. };
  162. struct npcm7xx_pwm_fan_data {
  163. void __iomem *pwm_base;
  164. void __iomem *fan_base;
  165. unsigned long pwm_clk_freq;
  166. unsigned long fan_clk_freq;
  167. struct clk *pwm_clk;
  168. struct clk *fan_clk;
  169. struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES];
  170. spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];
  171. int fan_irq[NPCM7XX_FAN_MAX_MODULE];
  172. bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];
  173. bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];
  174. u32 input_clk_freq;
  175. struct timer_list fan_timer;
  176. struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];
  177. struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];
  178. u8 fan_select;
  179. };
  180. static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
  181. int channel, u16 val)
  182. {
  183. u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
  184. u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
  185. u32 tmp_buf, ctrl_en_bit, env_bit;
  186. /*
  187. * Config PWM Comparator register for setting duty cycle
  188. */
  189. mutex_lock(&data->pwm_lock[module]);
  190. /* write new CMR value */
  191. iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
  192. tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
  193. switch (pwm_ch) {
  194. case 0:
  195. ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
  196. env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;
  197. break;
  198. case 1:
  199. ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
  200. env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;
  201. break;
  202. case 2:
  203. ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
  204. env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;
  205. break;
  206. case 3:
  207. ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
  208. env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;
  209. break;
  210. default:
  211. mutex_unlock(&data->pwm_lock[module]);
  212. return -ENODEV;
  213. }
  214. if (val == 0) {
  215. /* Disable PWM */
  216. tmp_buf &= ~ctrl_en_bit;
  217. tmp_buf |= env_bit;
  218. } else {
  219. /* Enable PWM */
  220. tmp_buf |= ctrl_en_bit;
  221. tmp_buf &= ~env_bit;
  222. }
  223. iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
  224. mutex_unlock(&data->pwm_lock[module]);
  225. return 0;
  226. }
  227. static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
  228. u8 fan, u8 cmp)
  229. {
  230. u8 fan_id;
  231. u8 reg_mode;
  232. u8 reg_int;
  233. unsigned long flags;
  234. fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
  235. /* to check whether any fan tach is enable */
  236. if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
  237. /* reset status */
  238. spin_lock_irqsave(&data->fan_lock[fan], flags);
  239. data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
  240. reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  241. /*
  242. * the interrupt enable bits do not need to be cleared before
  243. * it sets, the interrupt enable bits are cleared only on reset.
  244. * the clock unit control register is behaving in the same
  245. * manner that the interrupt enable register behave.
  246. */
  247. if (cmp == NPCM7XX_FAN_CMPA) {
  248. /* enable interrupt */
  249. iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |
  250. NPCM7XX_FAN_TIEN_TEIEN),
  251. NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  252. reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
  253. | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
  254. fan));
  255. /* start to Capture */
  256. iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
  257. fan));
  258. } else {
  259. /* enable interrupt */
  260. iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |
  261. NPCM7XX_FAN_TIEN_TFIEN),
  262. NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  263. reg_mode =
  264. NPCM7XX_FAN_TCKC_CLK2_APB
  265. | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
  266. fan));
  267. /* start to Capture */
  268. iowrite8(reg_mode,
  269. NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
  270. }
  271. spin_unlock_irqrestore(&data->fan_lock[fan], flags);
  272. }
  273. }
  274. /*
  275. * Enable a background timer to poll fan tach value, (200ms * 4)
  276. * to polling all fan
  277. */
  278. static void npcm7xx_fan_polling(struct timer_list *t)
  279. {
  280. struct npcm7xx_pwm_fan_data *data;
  281. int i;
  282. data = from_timer(data, t, fan_timer);
  283. /*
  284. * Polling two module per one round,
  285. * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415
  286. */
  287. for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
  288. i = i + 4) {
  289. /* clear the flag and reset the counter (TCNT) */
  290. iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
  291. NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
  292. if (data->fan_present[i * 2]) {
  293. iowrite16(NPCM7XX_FAN_TCNT,
  294. NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
  295. npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
  296. }
  297. if (data->fan_present[(i * 2) + 1]) {
  298. iowrite16(NPCM7XX_FAN_TCNT,
  299. NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
  300. npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
  301. }
  302. }
  303. data->fan_select++;
  304. data->fan_select &= 0x3;
  305. /* reset the timer interval */
  306. data->fan_timer.expires = jiffies +
  307. msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
  308. add_timer(&data->fan_timer);
  309. }
  310. static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
  311. u8 fan, u8 cmp, u8 fan_id, u8 flag_int,
  312. u8 flag_mode, u8 flag_clear)
  313. {
  314. u8 reg_int;
  315. u8 reg_mode;
  316. u16 fan_cap;
  317. if (cmp == NPCM7XX_FAN_CMPA)
  318. fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
  319. else
  320. fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
  321. /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */
  322. iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
  323. if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
  324. /* First capture, drop it */
  325. data->fan_dev[fan_id].fan_st_flg =
  326. FAN_PREPARE_TO_GET_FIRST_CAPTURE;
  327. /* reset counter */
  328. data->fan_dev[fan_id].fan_cnt_tmp = 0;
  329. } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
  330. /*
  331. * collect the enough sample,
  332. * (ex: 2 pulse fan need to get 2 sample)
  333. */
  334. data->fan_dev[fan_id].fan_cnt_tmp +=
  335. (NPCM7XX_FAN_TCNT - fan_cap);
  336. data->fan_dev[fan_id].fan_st_flg++;
  337. } else {
  338. /* get enough sample or fan disable */
  339. if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
  340. data->fan_dev[fan_id].fan_cnt_tmp +=
  341. (NPCM7XX_FAN_TCNT - fan_cap);
  342. /* compute finial average cnt per pulse */
  343. data->fan_dev[fan_id].fan_cnt =
  344. data->fan_dev[fan_id].fan_cnt_tmp /
  345. FAN_ENOUGH_SAMPLE;
  346. data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
  347. }
  348. reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  349. /* disable interrupt */
  350. iowrite8((reg_int & ~flag_int),
  351. NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  352. reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
  353. /* stop capturing */
  354. iowrite8((reg_mode & ~flag_mode),
  355. NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
  356. }
  357. }
  358. static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
  359. u8 fan, u8 cmp, u8 flag)
  360. {
  361. u8 reg_int;
  362. u8 reg_mode;
  363. u8 flag_timeout;
  364. u8 flag_cap;
  365. u8 flag_clear;
  366. u8 flag_int;
  367. u8 flag_mode;
  368. u8 fan_id;
  369. fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
  370. if (cmp == NPCM7XX_FAN_CMPA) {
  371. flag_cap = NPCM7XX_FAN_TICTRL_TAPND;
  372. flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;
  373. flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;
  374. flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;
  375. flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;
  376. } else {
  377. flag_cap = NPCM7XX_FAN_TICTRL_TBPND;
  378. flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;
  379. flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;
  380. flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;
  381. flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;
  382. }
  383. if (flag & flag_timeout) {
  384. reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  385. /* disable interrupt */
  386. iowrite8((reg_int & ~flag_int),
  387. NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
  388. /* clear interrupt flag */
  389. iowrite8(flag_clear,
  390. NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
  391. reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
  392. /* stop capturing */
  393. iowrite8((reg_mode & ~flag_mode),
  394. NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
  395. /*
  396. * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't
  397. * connect or speed is lower than 10.6Hz (320RPM/pulse2).
  398. * In these situation, the RPM output should be zero.
  399. */
  400. data->fan_dev[fan_id].fan_cnt = 0;
  401. } else {
  402. /* input capture is occurred */
  403. if (flag & flag_cap)
  404. npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
  405. flag_mode, flag_clear);
  406. }
  407. }
  408. static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)
  409. {
  410. struct npcm7xx_pwm_fan_data *data = dev_id;
  411. unsigned long flags;
  412. int module;
  413. u8 flag;
  414. module = irq - data->fan_irq[0];
  415. spin_lock_irqsave(&data->fan_lock[module], flags);
  416. flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
  417. if (flag > 0) {
  418. npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
  419. npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
  420. spin_unlock_irqrestore(&data->fan_lock[module], flags);
  421. return IRQ_HANDLED;
  422. }
  423. spin_unlock_irqrestore(&data->fan_lock[module], flags);
  424. return IRQ_NONE;
  425. }
  426. static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
  427. long *val)
  428. {
  429. struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
  430. u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
  431. u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
  432. switch (attr) {
  433. case hwmon_pwm_input:
  434. *val = ioread32
  435. (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
  436. return 0;
  437. default:
  438. return -EOPNOTSUPP;
  439. }
  440. }
  441. static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
  442. long val)
  443. {
  444. struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
  445. int err;
  446. switch (attr) {
  447. case hwmon_pwm_input:
  448. if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)
  449. return -EINVAL;
  450. err = npcm7xx_pwm_config_set(data, channel, (u16)val);
  451. break;
  452. default:
  453. err = -EOPNOTSUPP;
  454. break;
  455. }
  456. return err;
  457. }
  458. static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
  459. {
  460. const struct npcm7xx_pwm_fan_data *data = _data;
  461. if (!data->pwm_present[channel])
  462. return 0;
  463. switch (attr) {
  464. case hwmon_pwm_input:
  465. return 0644;
  466. default:
  467. return 0;
  468. }
  469. }
  470. static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,
  471. long *val)
  472. {
  473. struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
  474. switch (attr) {
  475. case hwmon_fan_input:
  476. *val = 0;
  477. if (data->fan_dev[channel].fan_cnt <= 0)
  478. return data->fan_dev[channel].fan_cnt;
  479. /* Convert the raw reading to RPM */
  480. if (data->fan_dev[channel].fan_cnt > 0 &&
  481. data->fan_dev[channel].fan_pls_per_rev > 0)
  482. *val = ((data->input_clk_freq * 60) /
  483. (data->fan_dev[channel].fan_cnt *
  484. data->fan_dev[channel].fan_pls_per_rev));
  485. return 0;
  486. default:
  487. return -EOPNOTSUPP;
  488. }
  489. }
  490. static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)
  491. {
  492. const struct npcm7xx_pwm_fan_data *data = _data;
  493. if (!data->fan_present[channel])
  494. return 0;
  495. switch (attr) {
  496. case hwmon_fan_input:
  497. return 0444;
  498. default:
  499. return 0;
  500. }
  501. }
  502. static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
  503. u32 attr, int channel, long *val)
  504. {
  505. switch (type) {
  506. case hwmon_pwm:
  507. return npcm7xx_read_pwm(dev, attr, channel, val);
  508. case hwmon_fan:
  509. return npcm7xx_read_fan(dev, attr, channel, val);
  510. default:
  511. return -EOPNOTSUPP;
  512. }
  513. }
  514. static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
  515. u32 attr, int channel, long val)
  516. {
  517. switch (type) {
  518. case hwmon_pwm:
  519. return npcm7xx_write_pwm(dev, attr, channel, val);
  520. default:
  521. return -EOPNOTSUPP;
  522. }
  523. }
  524. static umode_t npcm7xx_is_visible(const void *data,
  525. enum hwmon_sensor_types type,
  526. u32 attr, int channel)
  527. {
  528. switch (type) {
  529. case hwmon_pwm:
  530. return npcm7xx_pwm_is_visible(data, attr, channel);
  531. case hwmon_fan:
  532. return npcm7xx_fan_is_visible(data, attr, channel);
  533. default:
  534. return 0;
  535. }
  536. }
  537. static const struct hwmon_channel_info *npcm7xx_info[] = {
  538. HWMON_CHANNEL_INFO(pwm,
  539. HWMON_PWM_INPUT,
  540. HWMON_PWM_INPUT,
  541. HWMON_PWM_INPUT,
  542. HWMON_PWM_INPUT,
  543. HWMON_PWM_INPUT,
  544. HWMON_PWM_INPUT,
  545. HWMON_PWM_INPUT,
  546. HWMON_PWM_INPUT),
  547. HWMON_CHANNEL_INFO(fan,
  548. HWMON_F_INPUT,
  549. HWMON_F_INPUT,
  550. HWMON_F_INPUT,
  551. HWMON_F_INPUT,
  552. HWMON_F_INPUT,
  553. HWMON_F_INPUT,
  554. HWMON_F_INPUT,
  555. HWMON_F_INPUT,
  556. HWMON_F_INPUT,
  557. HWMON_F_INPUT,
  558. HWMON_F_INPUT,
  559. HWMON_F_INPUT,
  560. HWMON_F_INPUT,
  561. HWMON_F_INPUT,
  562. HWMON_F_INPUT,
  563. HWMON_F_INPUT),
  564. NULL
  565. };
  566. static const struct hwmon_ops npcm7xx_hwmon_ops = {
  567. .is_visible = npcm7xx_is_visible,
  568. .read = npcm7xx_read,
  569. .write = npcm7xx_write,
  570. };
  571. static const struct hwmon_chip_info npcm7xx_chip_info = {
  572. .ops = &npcm7xx_hwmon_ops,
  573. .info = npcm7xx_info,
  574. };
  575. static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
  576. {
  577. int m, ch;
  578. u32 prescale_val, output_freq;
  579. data->pwm_clk_freq = clk_get_rate(data->pwm_clk);
  580. /* Adjust NPCM7xx PWMs output frequency to ~25Khz */
  581. output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT;
  582. prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
  583. /* If prescale_val = 0, then the prescale output clock is stopped */
  584. if (prescale_val < MIN_PRESCALE1)
  585. prescale_val = MIN_PRESCALE1;
  586. /*
  587. * prescale_val need to decrement in one because in the PWM Prescale
  588. * register the Prescale value increment by one
  589. */
  590. prescale_val--;
  591. /* Setting PWM Prescale Register value register to both modules */
  592. prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
  593. for (m = 0; m < NPCM7XX_PWM_MAX_MODULES ; m++) {
  594. iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
  595. iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,
  596. NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
  597. iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,
  598. NPCM7XX_PWM_REG_CR(data->pwm_base, m));
  599. for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {
  600. iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,
  601. NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
  602. }
  603. }
  604. return output_freq / ((prescale_val & 0xf) + 1);
  605. }
  606. static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
  607. {
  608. int md;
  609. int ch;
  610. int i;
  611. u32 apb_clk_freq;
  612. for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {
  613. /* stop FAN0~7 clock */
  614. iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,
  615. NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
  616. /* disable all interrupt */
  617. iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
  618. /* clear all interrupt */
  619. iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
  620. NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
  621. /* set FAN0~7 clock prescaler */
  622. iowrite8(NPCM7XX_FAN_CLK_PRESCALE,
  623. NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
  624. /* set FAN0~7 mode (high-to-low transition) */
  625. iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |
  626. NPCM7XX_FAN_TMCTRL_TAEN),
  627. NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
  628. /* set FAN0~7 Initial Count/Cap */
  629. iowrite16(NPCM7XX_FAN_TCNT,
  630. NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
  631. iowrite16(NPCM7XX_FAN_TCNT,
  632. NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
  633. /* set FAN0~7 compare (equal to count) */
  634. iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),
  635. NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
  636. /* set FAN0~7 compare value */
  637. iowrite16(NPCM7XX_FAN_TCPA,
  638. NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
  639. iowrite16(NPCM7XX_FAN_TCPB,
  640. NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
  641. /* set FAN0~7 fan input FANIN 0~15 */
  642. iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
  643. NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
  644. iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
  645. NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
  646. for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {
  647. ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;
  648. data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
  649. data->fan_dev[ch].fan_pls_per_rev =
  650. NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;
  651. data->fan_dev[ch].fan_cnt = 0;
  652. }
  653. }
  654. apb_clk_freq = clk_get_rate(data->fan_clk);
  655. /* Fan tach input clock = APB clock / prescalar, default is 255. */
  656. data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
  657. }
  658. static int
  659. npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
  660. unsigned long *state)
  661. {
  662. struct npcm7xx_cooling_device *cdev = tcdev->devdata;
  663. *state = cdev->max_state;
  664. return 0;
  665. }
  666. static int
  667. npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
  668. unsigned long *state)
  669. {
  670. struct npcm7xx_cooling_device *cdev = tcdev->devdata;
  671. *state = cdev->cur_state;
  672. return 0;
  673. }
  674. static int
  675. npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
  676. unsigned long state)
  677. {
  678. struct npcm7xx_cooling_device *cdev = tcdev->devdata;
  679. int ret;
  680. if (state > cdev->max_state)
  681. return -EINVAL;
  682. cdev->cur_state = state;
  683. ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
  684. cdev->cooling_levels[cdev->cur_state]);
  685. return ret;
  686. }
  687. static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {
  688. .get_max_state = npcm7xx_pwm_cz_get_max_state,
  689. .get_cur_state = npcm7xx_pwm_cz_get_cur_state,
  690. .set_cur_state = npcm7xx_pwm_cz_set_cur_state,
  691. };
  692. static int npcm7xx_create_pwm_cooling(struct device *dev,
  693. struct device_node *child,
  694. struct npcm7xx_pwm_fan_data *data,
  695. u32 pwm_port, u8 num_levels)
  696. {
  697. int ret;
  698. struct npcm7xx_cooling_device *cdev;
  699. cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
  700. if (!cdev)
  701. return -ENOMEM;
  702. cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
  703. if (!cdev->cooling_levels)
  704. return -ENOMEM;
  705. cdev->max_state = num_levels - 1;
  706. ret = of_property_read_u8_array(child, "cooling-levels",
  707. cdev->cooling_levels,
  708. num_levels);
  709. if (ret) {
  710. dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
  711. return ret;
  712. }
  713. snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,
  714. pwm_port);
  715. cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
  716. cdev->name, cdev, &npcm7xx_pwm_cool_ops);
  717. if (IS_ERR(cdev->tcdev))
  718. return PTR_ERR(cdev->tcdev);
  719. cdev->data = data;
  720. cdev->pwm_port = pwm_port;
  721. data->cdev[pwm_port] = cdev;
  722. return 0;
  723. }
  724. static int npcm7xx_en_pwm_fan(struct device *dev,
  725. struct device_node *child,
  726. struct npcm7xx_pwm_fan_data *data)
  727. {
  728. u8 *fan_ch;
  729. u32 pwm_port;
  730. int ret, fan_cnt;
  731. u8 index, ch;
  732. ret = of_property_read_u32(child, "reg", &pwm_port);
  733. if (ret)
  734. return ret;
  735. data->pwm_present[pwm_port] = true;
  736. ret = npcm7xx_pwm_config_set(data, pwm_port,
  737. NPCM7XX_PWM_CMR_DEFAULT_NUM);
  738. ret = of_property_count_u8_elems(child, "cooling-levels");
  739. if (ret > 0) {
  740. ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
  741. ret);
  742. if (ret)
  743. return ret;
  744. }
  745. fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");
  746. if (fan_cnt < 1)
  747. return -EINVAL;
  748. fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);
  749. if (!fan_ch)
  750. return -ENOMEM;
  751. ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);
  752. if (ret)
  753. return ret;
  754. for (ch = 0; ch < fan_cnt; ch++) {
  755. index = fan_ch[ch];
  756. data->fan_present[index] = true;
  757. data->fan_dev[index].fan_st_flg = FAN_INIT;
  758. }
  759. return 0;
  760. }
  761. static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)
  762. {
  763. struct device *dev = &pdev->dev;
  764. struct device_node *np, *child;
  765. struct npcm7xx_pwm_fan_data *data;
  766. struct resource *res;
  767. struct device *hwmon;
  768. char name[20];
  769. int ret, cnt;
  770. u32 output_freq;
  771. u32 i;
  772. np = dev->of_node;
  773. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  774. if (!data)
  775. return -ENOMEM;
  776. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
  777. if (!res) {
  778. dev_err(dev, "pwm resource not found\n");
  779. return -ENODEV;
  780. }
  781. data->pwm_base = devm_ioremap_resource(dev, res);
  782. dev_dbg(dev, "pwm base resource is %pR\n", res);
  783. if (IS_ERR(data->pwm_base))
  784. return PTR_ERR(data->pwm_base);
  785. data->pwm_clk = devm_clk_get(dev, "pwm");
  786. if (IS_ERR(data->pwm_clk)) {
  787. dev_err(dev, "couldn't get pwm clock\n");
  788. return PTR_ERR(data->pwm_clk);
  789. }
  790. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");
  791. if (!res) {
  792. dev_err(dev, "fan resource not found\n");
  793. return -ENODEV;
  794. }
  795. data->fan_base = devm_ioremap_resource(dev, res);
  796. dev_dbg(dev, "fan base resource is %pR\n", res);
  797. if (IS_ERR(data->fan_base))
  798. return PTR_ERR(data->fan_base);
  799. data->fan_clk = devm_clk_get(dev, "fan");
  800. if (IS_ERR(data->fan_clk)) {
  801. dev_err(dev, "couldn't get fan clock\n");
  802. return PTR_ERR(data->fan_clk);
  803. }
  804. output_freq = npcm7xx_pwm_init(data);
  805. npcm7xx_fan_init(data);
  806. for (cnt = 0; cnt < NPCM7XX_PWM_MAX_MODULES ; cnt++)
  807. mutex_init(&data->pwm_lock[cnt]);
  808. for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {
  809. spin_lock_init(&data->fan_lock[i]);
  810. data->fan_irq[i] = platform_get_irq(pdev, i);
  811. if (data->fan_irq[i] < 0)
  812. return data->fan_irq[i];
  813. sprintf(name, "NPCM7XX-FAN-MD%d", i);
  814. ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
  815. 0, name, (void *)data);
  816. if (ret) {
  817. dev_err(dev, "register IRQ fan%d failed\n", i);
  818. return ret;
  819. }
  820. }
  821. for_each_child_of_node(np, child) {
  822. ret = npcm7xx_en_pwm_fan(dev, child, data);
  823. if (ret) {
  824. dev_err(dev, "enable pwm and fan failed\n");
  825. of_node_put(child);
  826. return ret;
  827. }
  828. }
  829. hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",
  830. data, &npcm7xx_chip_info,
  831. NULL);
  832. if (IS_ERR(hwmon)) {
  833. dev_err(dev, "unable to register hwmon device\n");
  834. return PTR_ERR(hwmon);
  835. }
  836. for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {
  837. if (data->fan_present[i]) {
  838. /* fan timer initialization */
  839. data->fan_timer.expires = jiffies +
  840. msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
  841. timer_setup(&data->fan_timer,
  842. npcm7xx_fan_polling, 0);
  843. add_timer(&data->fan_timer);
  844. break;
  845. }
  846. }
  847. pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",
  848. output_freq, data->input_clk_freq);
  849. return 0;
  850. }
  851. static const struct of_device_id of_pwm_fan_match_table[] = {
  852. { .compatible = "nuvoton,npcm750-pwm-fan", },
  853. {},
  854. };
  855. MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);
  856. static struct platform_driver npcm7xx_pwm_fan_driver = {
  857. .probe = npcm7xx_pwm_fan_probe,
  858. .driver = {
  859. .name = "npcm7xx_pwm_fan",
  860. .of_match_table = of_pwm_fan_match_table,
  861. },
  862. };
  863. module_platform_driver(npcm7xx_pwm_fan_driver);
  864. MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");
  865. MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
  866. MODULE_LICENSE("GPL v2");