max6621.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Hardware monitoring driver for Maxim MAX6621
  4. *
  5. * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
  6. * Copyright (c) 2017 Vadim Pasternak <vadimp@mellanox.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/hwmon.h>
  10. #include <linux/hwmon-sysfs.h>
  11. #include <linux/i2c.h>
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/regmap.h>
  16. #define MAX6621_DRV_NAME "max6621"
  17. #define MAX6621_TEMP_INPUT_REG_NUM 9
  18. #define MAX6621_TEMP_INPUT_MIN -127000
  19. #define MAX6621_TEMP_INPUT_MAX 128000
  20. #define MAX6621_TEMP_ALERT_CHAN_SHIFT 1
  21. #define MAX6621_TEMP_S0D0_REG 0x00
  22. #define MAX6621_TEMP_S0D1_REG 0x01
  23. #define MAX6621_TEMP_S1D0_REG 0x02
  24. #define MAX6621_TEMP_S1D1_REG 0x03
  25. #define MAX6621_TEMP_S2D0_REG 0x04
  26. #define MAX6621_TEMP_S2D1_REG 0x05
  27. #define MAX6621_TEMP_S3D0_REG 0x06
  28. #define MAX6621_TEMP_S3D1_REG 0x07
  29. #define MAX6621_TEMP_MAX_REG 0x08
  30. #define MAX6621_TEMP_MAX_ADDR_REG 0x0a
  31. #define MAX6621_TEMP_ALERT_CAUSE_REG 0x0b
  32. #define MAX6621_CONFIG0_REG 0x0c
  33. #define MAX6621_CONFIG1_REG 0x0d
  34. #define MAX6621_CONFIG2_REG 0x0e
  35. #define MAX6621_CONFIG3_REG 0x0f
  36. #define MAX6621_TEMP_S0_ALERT_REG 0x10
  37. #define MAX6621_TEMP_S1_ALERT_REG 0x11
  38. #define MAX6621_TEMP_S2_ALERT_REG 0x12
  39. #define MAX6621_TEMP_S3_ALERT_REG 0x13
  40. #define MAX6621_CLEAR_ALERT_REG 0x15
  41. #define MAX6621_REG_MAX (MAX6621_CLEAR_ALERT_REG + 1)
  42. #define MAX6621_REG_TEMP_SHIFT 0x06
  43. #define MAX6621_ENABLE_TEMP_ALERTS_BIT 4
  44. #define MAX6621_ENABLE_I2C_CRC_BIT 5
  45. #define MAX6621_ENABLE_ALTERNATE_DATA 6
  46. #define MAX6621_ENABLE_LOCKUP_TO 7
  47. #define MAX6621_ENABLE_S0D0_BIT 8
  48. #define MAX6621_ENABLE_S3D1_BIT 15
  49. #define MAX6621_ENABLE_TEMP_ALL GENMASK(MAX6621_ENABLE_S3D1_BIT, \
  50. MAX6621_ENABLE_S0D0_BIT)
  51. #define MAX6621_POLL_DELAY_MASK 0x5
  52. #define MAX6621_CONFIG0_INIT (MAX6621_ENABLE_TEMP_ALL | \
  53. BIT(MAX6621_ENABLE_LOCKUP_TO) | \
  54. BIT(MAX6621_ENABLE_I2C_CRC_BIT) | \
  55. MAX6621_POLL_DELAY_MASK)
  56. #define MAX6621_PECI_BIT_TIME 0x2
  57. #define MAX6621_PECI_RETRY_NUM 0x3
  58. #define MAX6621_CONFIG1_INIT ((MAX6621_PECI_BIT_TIME << 8) | \
  59. MAX6621_PECI_RETRY_NUM)
  60. /* Error codes */
  61. #define MAX6621_TRAN_FAILED 0x8100 /*
  62. * PECI transaction failed for more
  63. * than the configured number of
  64. * consecutive retries.
  65. */
  66. #define MAX6621_POOL_DIS 0x8101 /*
  67. * Polling disabled for requested
  68. * socket/domain.
  69. */
  70. #define MAX6621_POOL_UNCOMPLETE 0x8102 /*
  71. * First poll not yet completed for
  72. * requested socket/domain (on
  73. * startup).
  74. */
  75. #define MAX6621_SD_DIS 0x8103 /*
  76. * Read maximum temperature requested,
  77. * but no sockets/domains enabled or
  78. * all enabled sockets/domains have
  79. * errors; or read maximum temperature
  80. * address requested, but read maximum
  81. * temperature was not called.
  82. */
  83. #define MAX6621_ALERT_DIS 0x8104 /*
  84. * Get alert socket/domain requested,
  85. * but no alert active.
  86. */
  87. #define MAX6621_PECI_ERR_MIN 0x8000 /* Intel spec PECI error min value. */
  88. #define MAX6621_PECI_ERR_MAX 0x80ff /* Intel spec PECI error max value. */
  89. static const u32 max6621_temp_regs[] = {
  90. MAX6621_TEMP_MAX_REG, MAX6621_TEMP_S0D0_REG, MAX6621_TEMP_S1D0_REG,
  91. MAX6621_TEMP_S2D0_REG, MAX6621_TEMP_S3D0_REG, MAX6621_TEMP_S0D1_REG,
  92. MAX6621_TEMP_S1D1_REG, MAX6621_TEMP_S2D1_REG, MAX6621_TEMP_S3D1_REG,
  93. };
  94. static const char *const max6621_temp_labels[] = {
  95. "maximum",
  96. "socket0_0",
  97. "socket1_0",
  98. "socket2_0",
  99. "socket3_0",
  100. "socket0_1",
  101. "socket1_1",
  102. "socket2_1",
  103. "socket3_1",
  104. };
  105. static const int max6621_temp_alert_chan2reg[] = {
  106. MAX6621_TEMP_S0_ALERT_REG,
  107. MAX6621_TEMP_S1_ALERT_REG,
  108. MAX6621_TEMP_S2_ALERT_REG,
  109. MAX6621_TEMP_S3_ALERT_REG,
  110. };
  111. /**
  112. * struct max6621_data - private data:
  113. *
  114. * @client: I2C client;
  115. * @regmap: register map handle;
  116. * @input_chan2reg: mapping from channel to register;
  117. */
  118. struct max6621_data {
  119. struct i2c_client *client;
  120. struct regmap *regmap;
  121. int input_chan2reg[MAX6621_TEMP_INPUT_REG_NUM + 1];
  122. };
  123. static long max6621_temp_mc2reg(long val)
  124. {
  125. return (val / 1000L) << MAX6621_REG_TEMP_SHIFT;
  126. }
  127. static umode_t
  128. max6621_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
  129. int channel)
  130. {
  131. /* Skip channels which are not physically conncted. */
  132. if (((struct max6621_data *)data)->input_chan2reg[channel] < 0)
  133. return 0;
  134. switch (type) {
  135. case hwmon_temp:
  136. switch (attr) {
  137. case hwmon_temp_input:
  138. case hwmon_temp_label:
  139. case hwmon_temp_crit_alarm:
  140. return 0444;
  141. case hwmon_temp_offset:
  142. case hwmon_temp_crit:
  143. return 0644;
  144. default:
  145. break;
  146. }
  147. default:
  148. break;
  149. }
  150. return 0;
  151. }
  152. static int max6621_verify_reg_data(struct device *dev, int regval)
  153. {
  154. if (regval >= MAX6621_PECI_ERR_MIN &&
  155. regval <= MAX6621_PECI_ERR_MAX) {
  156. dev_dbg(dev, "PECI error code - err 0x%04x.\n",
  157. regval);
  158. return -EIO;
  159. }
  160. switch (regval) {
  161. case MAX6621_TRAN_FAILED:
  162. dev_dbg(dev, "PECI transaction failed - err 0x%04x.\n",
  163. regval);
  164. return -EIO;
  165. case MAX6621_POOL_DIS:
  166. dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval);
  167. return -EOPNOTSUPP;
  168. case MAX6621_POOL_UNCOMPLETE:
  169. dev_dbg(dev, "First poll not completed on startup - err 0x%04x.\n",
  170. regval);
  171. return -EIO;
  172. case MAX6621_SD_DIS:
  173. dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval);
  174. return -EOPNOTSUPP;
  175. case MAX6621_ALERT_DIS:
  176. dev_dbg(dev, "No alert active - err 0x%04x.\n", regval);
  177. return -EOPNOTSUPP;
  178. default:
  179. return 0;
  180. }
  181. }
  182. static int
  183. max6621_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
  184. int channel, long *val)
  185. {
  186. struct max6621_data *data = dev_get_drvdata(dev);
  187. u32 regval;
  188. int reg;
  189. s8 temp;
  190. int ret;
  191. switch (type) {
  192. case hwmon_temp:
  193. switch (attr) {
  194. case hwmon_temp_input:
  195. reg = data->input_chan2reg[channel];
  196. ret = regmap_read(data->regmap, reg, &regval);
  197. if (ret)
  198. return ret;
  199. ret = max6621_verify_reg_data(dev, regval);
  200. if (ret)
  201. return ret;
  202. /*
  203. * Bit MAX6621_REG_TEMP_SHIFT represents 1 degree step.
  204. * The temperature is given in two's complement and 8
  205. * bits is used for the register conversion.
  206. */
  207. temp = (regval >> MAX6621_REG_TEMP_SHIFT);
  208. *val = temp * 1000L;
  209. break;
  210. case hwmon_temp_offset:
  211. ret = regmap_read(data->regmap, MAX6621_CONFIG2_REG,
  212. &regval);
  213. if (ret)
  214. return ret;
  215. ret = max6621_verify_reg_data(dev, regval);
  216. if (ret)
  217. return ret;
  218. *val = (regval >> MAX6621_REG_TEMP_SHIFT) *
  219. 1000L;
  220. break;
  221. case hwmon_temp_crit:
  222. channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
  223. reg = max6621_temp_alert_chan2reg[channel];
  224. ret = regmap_read(data->regmap, reg, &regval);
  225. if (ret)
  226. return ret;
  227. ret = max6621_verify_reg_data(dev, regval);
  228. if (ret)
  229. return ret;
  230. *val = regval * 1000L;
  231. break;
  232. case hwmon_temp_crit_alarm:
  233. /*
  234. * Set val to zero to recover the case, when reading
  235. * MAX6621_TEMP_ALERT_CAUSE_REG results in for example
  236. * MAX6621_ALERT_DIS. Reading will return with error,
  237. * but in such case alarm should be returned as 0.
  238. */
  239. *val = 0;
  240. ret = regmap_read(data->regmap,
  241. MAX6621_TEMP_ALERT_CAUSE_REG,
  242. &regval);
  243. if (ret)
  244. return ret;
  245. ret = max6621_verify_reg_data(dev, regval);
  246. if (ret) {
  247. /* Do not report error if alert is disabled. */
  248. if (regval == MAX6621_ALERT_DIS)
  249. return 0;
  250. else
  251. return ret;
  252. }
  253. /*
  254. * Clear the alert automatically, using send-byte
  255. * smbus protocol for clearing alert.
  256. */
  257. if (regval) {
  258. ret = i2c_smbus_write_byte(data->client,
  259. MAX6621_CLEAR_ALERT_REG);
  260. if (ret)
  261. return ret;
  262. }
  263. *val = !!regval;
  264. break;
  265. default:
  266. return -EOPNOTSUPP;
  267. }
  268. break;
  269. default:
  270. return -EOPNOTSUPP;
  271. }
  272. return 0;
  273. }
  274. static int
  275. max6621_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
  276. int channel, long val)
  277. {
  278. struct max6621_data *data = dev_get_drvdata(dev);
  279. u32 reg;
  280. switch (type) {
  281. case hwmon_temp:
  282. switch (attr) {
  283. case hwmon_temp_offset:
  284. /* Clamp to allowed range to prevent overflow. */
  285. val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
  286. MAX6621_TEMP_INPUT_MAX);
  287. val = max6621_temp_mc2reg(val);
  288. return regmap_write(data->regmap,
  289. MAX6621_CONFIG2_REG, val);
  290. case hwmon_temp_crit:
  291. channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
  292. reg = max6621_temp_alert_chan2reg[channel];
  293. /* Clamp to allowed range to prevent overflow. */
  294. val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
  295. MAX6621_TEMP_INPUT_MAX);
  296. val = val / 1000L;
  297. return regmap_write(data->regmap, reg, val);
  298. default:
  299. return -EOPNOTSUPP;
  300. }
  301. break;
  302. default:
  303. return -EOPNOTSUPP;
  304. }
  305. return -EOPNOTSUPP;
  306. }
  307. static int
  308. max6621_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr,
  309. int channel, const char **str)
  310. {
  311. switch (type) {
  312. case hwmon_temp:
  313. switch (attr) {
  314. case hwmon_temp_label:
  315. *str = max6621_temp_labels[channel];
  316. return 0;
  317. default:
  318. return -EOPNOTSUPP;
  319. }
  320. break;
  321. default:
  322. return -EOPNOTSUPP;
  323. }
  324. return -EOPNOTSUPP;
  325. }
  326. static bool max6621_writeable_reg(struct device *dev, unsigned int reg)
  327. {
  328. switch (reg) {
  329. case MAX6621_CONFIG0_REG:
  330. case MAX6621_CONFIG1_REG:
  331. case MAX6621_CONFIG2_REG:
  332. case MAX6621_CONFIG3_REG:
  333. case MAX6621_TEMP_S0_ALERT_REG:
  334. case MAX6621_TEMP_S1_ALERT_REG:
  335. case MAX6621_TEMP_S2_ALERT_REG:
  336. case MAX6621_TEMP_S3_ALERT_REG:
  337. case MAX6621_TEMP_ALERT_CAUSE_REG:
  338. return true;
  339. }
  340. return false;
  341. }
  342. static bool max6621_readable_reg(struct device *dev, unsigned int reg)
  343. {
  344. switch (reg) {
  345. case MAX6621_TEMP_S0D0_REG:
  346. case MAX6621_TEMP_S0D1_REG:
  347. case MAX6621_TEMP_S1D0_REG:
  348. case MAX6621_TEMP_S1D1_REG:
  349. case MAX6621_TEMP_S2D0_REG:
  350. case MAX6621_TEMP_S2D1_REG:
  351. case MAX6621_TEMP_S3D0_REG:
  352. case MAX6621_TEMP_S3D1_REG:
  353. case MAX6621_TEMP_MAX_REG:
  354. case MAX6621_TEMP_MAX_ADDR_REG:
  355. case MAX6621_CONFIG0_REG:
  356. case MAX6621_CONFIG1_REG:
  357. case MAX6621_CONFIG2_REG:
  358. case MAX6621_CONFIG3_REG:
  359. case MAX6621_TEMP_S0_ALERT_REG:
  360. case MAX6621_TEMP_S1_ALERT_REG:
  361. case MAX6621_TEMP_S2_ALERT_REG:
  362. case MAX6621_TEMP_S3_ALERT_REG:
  363. return true;
  364. }
  365. return false;
  366. }
  367. static bool max6621_volatile_reg(struct device *dev, unsigned int reg)
  368. {
  369. switch (reg) {
  370. case MAX6621_TEMP_S0D0_REG:
  371. case MAX6621_TEMP_S0D1_REG:
  372. case MAX6621_TEMP_S1D0_REG:
  373. case MAX6621_TEMP_S1D1_REG:
  374. case MAX6621_TEMP_S2D0_REG:
  375. case MAX6621_TEMP_S2D1_REG:
  376. case MAX6621_TEMP_S3D0_REG:
  377. case MAX6621_TEMP_S3D1_REG:
  378. case MAX6621_TEMP_MAX_REG:
  379. case MAX6621_TEMP_S0_ALERT_REG:
  380. case MAX6621_TEMP_S1_ALERT_REG:
  381. case MAX6621_TEMP_S2_ALERT_REG:
  382. case MAX6621_TEMP_S3_ALERT_REG:
  383. case MAX6621_TEMP_ALERT_CAUSE_REG:
  384. return true;
  385. }
  386. return false;
  387. }
  388. static const struct reg_default max6621_regmap_default[] = {
  389. { MAX6621_CONFIG0_REG, MAX6621_CONFIG0_INIT },
  390. { MAX6621_CONFIG1_REG, MAX6621_CONFIG1_INIT },
  391. };
  392. static const struct regmap_config max6621_regmap_config = {
  393. .reg_bits = 8,
  394. .val_bits = 16,
  395. .max_register = MAX6621_REG_MAX,
  396. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  397. .cache_type = REGCACHE_FLAT,
  398. .writeable_reg = max6621_writeable_reg,
  399. .readable_reg = max6621_readable_reg,
  400. .volatile_reg = max6621_volatile_reg,
  401. .reg_defaults = max6621_regmap_default,
  402. .num_reg_defaults = ARRAY_SIZE(max6621_regmap_default),
  403. };
  404. static const struct hwmon_channel_info *max6621_info[] = {
  405. HWMON_CHANNEL_INFO(chip,
  406. HWMON_C_REGISTER_TZ),
  407. HWMON_CHANNEL_INFO(temp,
  408. HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_OFFSET,
  409. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  410. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  411. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  412. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  413. HWMON_T_INPUT | HWMON_T_LABEL,
  414. HWMON_T_INPUT | HWMON_T_LABEL,
  415. HWMON_T_INPUT | HWMON_T_LABEL,
  416. HWMON_T_INPUT | HWMON_T_LABEL),
  417. NULL
  418. };
  419. static const struct hwmon_ops max6621_hwmon_ops = {
  420. .read = max6621_read,
  421. .write = max6621_write,
  422. .read_string = max6621_read_string,
  423. .is_visible = max6621_is_visible,
  424. };
  425. static const struct hwmon_chip_info max6621_chip_info = {
  426. .ops = &max6621_hwmon_ops,
  427. .info = max6621_info,
  428. };
  429. static int max6621_probe(struct i2c_client *client)
  430. {
  431. struct device *dev = &client->dev;
  432. struct max6621_data *data;
  433. struct device *hwmon_dev;
  434. int i;
  435. int ret;
  436. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  437. if (!data)
  438. return -ENOMEM;
  439. data->regmap = devm_regmap_init_i2c(client, &max6621_regmap_config);
  440. if (IS_ERR(data->regmap))
  441. return PTR_ERR(data->regmap);
  442. i2c_set_clientdata(client, data);
  443. data->client = client;
  444. /* Set CONFIG0 register masking temperature alerts and PEC. */
  445. ret = regmap_write(data->regmap, MAX6621_CONFIG0_REG,
  446. MAX6621_CONFIG0_INIT);
  447. if (ret)
  448. return ret;
  449. /* Set CONFIG1 register for PEC access retry number. */
  450. ret = regmap_write(data->regmap, MAX6621_CONFIG1_REG,
  451. MAX6621_CONFIG1_INIT);
  452. if (ret)
  453. return ret;
  454. /* Sync registers with hardware. */
  455. regcache_mark_dirty(data->regmap);
  456. ret = regcache_sync(data->regmap);
  457. if (ret)
  458. return ret;
  459. /* Verify which temperature input registers are enabled. */
  460. for (i = 0; i < MAX6621_TEMP_INPUT_REG_NUM; i++) {
  461. ret = i2c_smbus_read_word_data(client, max6621_temp_regs[i]);
  462. if (ret < 0)
  463. return ret;
  464. ret = max6621_verify_reg_data(dev, ret);
  465. if (ret) {
  466. data->input_chan2reg[i] = -1;
  467. continue;
  468. }
  469. data->input_chan2reg[i] = max6621_temp_regs[i];
  470. }
  471. hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
  472. data,
  473. &max6621_chip_info,
  474. NULL);
  475. return PTR_ERR_OR_ZERO(hwmon_dev);
  476. }
  477. static const struct i2c_device_id max6621_id[] = {
  478. { MAX6621_DRV_NAME, 0 },
  479. { }
  480. };
  481. MODULE_DEVICE_TABLE(i2c, max6621_id);
  482. static const struct of_device_id __maybe_unused max6621_of_match[] = {
  483. { .compatible = "maxim,max6621" },
  484. { }
  485. };
  486. MODULE_DEVICE_TABLE(of, max6621_of_match);
  487. static struct i2c_driver max6621_driver = {
  488. .class = I2C_CLASS_HWMON,
  489. .driver = {
  490. .name = MAX6621_DRV_NAME,
  491. .of_match_table = of_match_ptr(max6621_of_match),
  492. },
  493. .probe_new = max6621_probe,
  494. .id_table = max6621_id,
  495. };
  496. module_i2c_driver(max6621_driver);
  497. MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
  498. MODULE_DESCRIPTION("Driver for Maxim MAX6621");
  499. MODULE_LICENSE("GPL");