hwmon-vid.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * hwmon-vid.c - VID/VRM/VRD voltage conversions
  4. *
  5. * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
  6. *
  7. * Partly imported from i2c-vid.h of the lm_sensors project
  8. * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
  9. * With assistance from Trent Piepho <xyzzy@speakeasy.org>
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/hwmon-vid.h>
  15. /*
  16. * Common code for decoding VID pins.
  17. *
  18. * References:
  19. *
  20. * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
  21. * available at http://developer.intel.com/.
  22. *
  23. * For VRD 10.0 and up, "VRD x.y Design Guide",
  24. * available at http://developer.intel.com/.
  25. *
  26. * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
  27. * http://support.amd.com/us/Processor_TechDocs/26094.PDF
  28. * Table 74. VID Code Voltages
  29. * This corresponds to an arbitrary VRM code of 24 in the functions below.
  30. * These CPU models (K8 revision <= E) have 5 VID pins. See also:
  31. * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
  32. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
  33. *
  34. * AMD NPT Family 0Fh Processors, AMD Publication 32559,
  35. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  36. * Table 71. VID Code Voltages
  37. * This corresponds to an arbitrary VRM code of 25 in the functions below.
  38. * These CPU models (K8 revision >= F) have 6 VID pins. See also:
  39. * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
  40. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
  41. *
  42. * The 17 specification is in fact Intel Mobile Voltage Positioning -
  43. * (IMVP-II). You can find more information in the datasheet of Max1718
  44. * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
  45. *
  46. * The 13 specification corresponds to the Intel Pentium M series. There
  47. * doesn't seem to be any named specification for these. The conversion
  48. * tables are detailed directly in the various Pentium M datasheets:
  49. * https://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
  50. *
  51. * The 14 specification corresponds to Intel Core series. There
  52. * doesn't seem to be any named specification for these. The conversion
  53. * tables are detailed directly in the various Pentium Core datasheets:
  54. * https://www.intel.com/design/mobile/datashts/309221.htm
  55. *
  56. * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
  57. * https://www.intel.com/design/processor/applnots/313214.htm
  58. */
  59. /*
  60. * vrm is the VRM/VRD document version multiplied by 10.
  61. * val is the 4-bit or more VID code.
  62. * Returned value is in mV to avoid floating point in the kernel.
  63. * Some VID have some bits in uV scale, this is rounded to mV.
  64. */
  65. int vid_from_reg(int val, u8 vrm)
  66. {
  67. int vid;
  68. switch (vrm) {
  69. case 100: /* VRD 10.0 */
  70. /* compute in uV, round to mV */
  71. val &= 0x3f;
  72. if ((val & 0x1f) == 0x1f)
  73. return 0;
  74. if ((val & 0x1f) <= 0x09 || val == 0x0a)
  75. vid = 1087500 - (val & 0x1f) * 25000;
  76. else
  77. vid = 1862500 - (val & 0x1f) * 25000;
  78. if (val & 0x20)
  79. vid -= 12500;
  80. return (vid + 500) / 1000;
  81. case 110: /* Intel Conroe */
  82. /* compute in uV, round to mV */
  83. val &= 0xff;
  84. if (val < 0x02 || val > 0xb2)
  85. return 0;
  86. return (1600000 - (val - 2) * 6250 + 500) / 1000;
  87. case 24: /* Athlon64 & Opteron */
  88. val &= 0x1f;
  89. if (val == 0x1f)
  90. return 0;
  91. fallthrough;
  92. case 25: /* AMD NPT 0Fh */
  93. val &= 0x3f;
  94. return (val < 32) ? 1550 - 25 * val
  95. : 775 - (25 * (val - 31)) / 2;
  96. case 26: /* AMD family 10h to 15h, serial VID */
  97. val &= 0x7f;
  98. if (val >= 0x7c)
  99. return 0;
  100. return DIV_ROUND_CLOSEST(15500 - 125 * val, 10);
  101. case 91: /* VRM 9.1 */
  102. case 90: /* VRM 9.0 */
  103. val &= 0x1f;
  104. return val == 0x1f ? 0 :
  105. 1850 - val * 25;
  106. case 85: /* VRM 8.5 */
  107. val &= 0x1f;
  108. return (val & 0x10 ? 25 : 0) +
  109. ((val & 0x0f) > 0x04 ? 2050 : 1250) -
  110. ((val & 0x0f) * 50);
  111. case 84: /* VRM 8.4 */
  112. val &= 0x0f;
  113. fallthrough;
  114. case 82: /* VRM 8.2 */
  115. val &= 0x1f;
  116. return val == 0x1f ? 0 :
  117. val & 0x10 ? 5100 - (val) * 100 :
  118. 2050 - (val) * 50;
  119. case 17: /* Intel IMVP-II */
  120. val &= 0x1f;
  121. return val & 0x10 ? 975 - (val & 0xF) * 25 :
  122. 1750 - val * 50;
  123. case 13:
  124. case 131:
  125. val &= 0x3f;
  126. /* Exception for Eden ULV 500 MHz */
  127. if (vrm == 131 && val == 0x3f)
  128. val++;
  129. return 1708 - val * 16;
  130. case 14: /* Intel Core */
  131. /* compute in uV, round to mV */
  132. val &= 0x7f;
  133. return val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000;
  134. default: /* report 0 for unknown */
  135. if (vrm)
  136. pr_warn("Requested unsupported VRM version (%u)\n",
  137. (unsigned int)vrm);
  138. return 0;
  139. }
  140. }
  141. EXPORT_SYMBOL(vid_from_reg);
  142. /*
  143. * After this point is the code to automatically determine which
  144. * VRM/VRD specification should be used depending on the CPU.
  145. */
  146. struct vrm_model {
  147. u8 vendor;
  148. u8 family;
  149. u8 model_from;
  150. u8 model_to;
  151. u8 stepping_to;
  152. u8 vrm_type;
  153. };
  154. #define ANY 0xFF
  155. #ifdef CONFIG_X86
  156. /*
  157. * The stepping_to parameter is highest acceptable stepping for current line.
  158. * The model match must be exact for 4-bit values. For model values 0x10
  159. * and above (extended model), all models below the parameter will match.
  160. */
  161. static struct vrm_model vrm_models[] = {
  162. {X86_VENDOR_AMD, 0x6, 0x0, ANY, ANY, 90}, /* Athlon Duron etc */
  163. {X86_VENDOR_AMD, 0xF, 0x0, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
  164. /*
  165. * In theory, all NPT family 0Fh processors have 6 VID pins and should
  166. * thus use vrm 25, however in practice not all mainboards route the
  167. * 6th VID pin because it is never needed. So we use the 5 VID pin
  168. * variant (vrm 24) for the models which exist today.
  169. */
  170. {X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24}, /* NPT family 0Fh */
  171. {X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25}, /* future fam. 0Fh */
  172. {X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25}, /* NPT family 10h */
  173. {X86_VENDOR_AMD, 0x11, 0x0, ANY, ANY, 26}, /* family 11h */
  174. {X86_VENDOR_AMD, 0x12, 0x0, ANY, ANY, 26}, /* family 12h */
  175. {X86_VENDOR_AMD, 0x14, 0x0, ANY, ANY, 26}, /* family 14h */
  176. {X86_VENDOR_AMD, 0x15, 0x0, ANY, ANY, 26}, /* family 15h */
  177. {X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82}, /* Pentium Pro,
  178. * Pentium II, Xeon,
  179. * Mobile Pentium,
  180. * Celeron */
  181. {X86_VENDOR_INTEL, 0x6, 0x7, 0x7, ANY, 84}, /* Pentium III, Xeon */
  182. {X86_VENDOR_INTEL, 0x6, 0x8, 0x8, ANY, 82}, /* Pentium III, Xeon */
  183. {X86_VENDOR_INTEL, 0x6, 0x9, 0x9, ANY, 13}, /* Pentium M (130 nm) */
  184. {X86_VENDOR_INTEL, 0x6, 0xA, 0xA, ANY, 82}, /* Pentium III Xeon */
  185. {X86_VENDOR_INTEL, 0x6, 0xB, 0xB, ANY, 85}, /* Tualatin */
  186. {X86_VENDOR_INTEL, 0x6, 0xD, 0xD, ANY, 13}, /* Pentium M (90 nm) */
  187. {X86_VENDOR_INTEL, 0x6, 0xE, 0xE, ANY, 14}, /* Intel Core (65 nm) */
  188. {X86_VENDOR_INTEL, 0x6, 0xF, ANY, ANY, 110}, /* Intel Conroe and
  189. * later */
  190. {X86_VENDOR_INTEL, 0xF, 0x0, 0x0, ANY, 90}, /* P4 */
  191. {X86_VENDOR_INTEL, 0xF, 0x1, 0x1, ANY, 90}, /* P4 Willamette */
  192. {X86_VENDOR_INTEL, 0xF, 0x2, 0x2, ANY, 90}, /* P4 Northwood */
  193. {X86_VENDOR_INTEL, 0xF, 0x3, ANY, ANY, 100}, /* Prescott and above
  194. * assume VRD 10 */
  195. {X86_VENDOR_CENTAUR, 0x6, 0x7, 0x7, ANY, 85}, /* Eden ESP/Ezra */
  196. {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x8, 0x7, 85}, /* Ezra T */
  197. {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, 0x7, 85}, /* Nehemiah */
  198. {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, ANY, 17}, /* C3-M, Eden-N */
  199. {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, 0x7, 0}, /* No information */
  200. {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, ANY, 13}, /* C7-M, C7,
  201. * Eden (Esther) */
  202. {X86_VENDOR_CENTAUR, 0x6, 0xD, 0xD, ANY, 134}, /* C7-D, C7-M, C7,
  203. * Eden (Esther) */
  204. };
  205. /*
  206. * Special case for VIA model D: there are two different possible
  207. * VID tables, so we have to figure out first, which one must be
  208. * used. This resolves temporary drm value 134 to 14 (Intel Core
  209. * 7-bit VID), 13 (Pentium M 6-bit VID) or 131 (Pentium M 6-bit VID
  210. * + quirk for Eden ULV 500 MHz).
  211. * Note: something similar might be needed for model A, I'm not sure.
  212. */
  213. static u8 get_via_model_d_vrm(void)
  214. {
  215. unsigned int vid, brand, __maybe_unused dummy;
  216. static const char *brands[4] = {
  217. "C7-M", "C7", "Eden", "C7-D"
  218. };
  219. rdmsr(0x198, dummy, vid);
  220. vid &= 0xff;
  221. rdmsr(0x1154, brand, dummy);
  222. brand = ((brand >> 4) ^ (brand >> 2)) & 0x03;
  223. if (vid > 0x3f) {
  224. pr_info("Using %d-bit VID table for VIA %s CPU\n",
  225. 7, brands[brand]);
  226. return 14;
  227. } else {
  228. pr_info("Using %d-bit VID table for VIA %s CPU\n",
  229. 6, brands[brand]);
  230. /* Enable quirk for Eden */
  231. return brand == 2 ? 131 : 13;
  232. }
  233. }
  234. static u8 find_vrm(u8 family, u8 model, u8 stepping, u8 vendor)
  235. {
  236. int i;
  237. for (i = 0; i < ARRAY_SIZE(vrm_models); i++) {
  238. if (vendor == vrm_models[i].vendor &&
  239. family == vrm_models[i].family &&
  240. model >= vrm_models[i].model_from &&
  241. model <= vrm_models[i].model_to &&
  242. stepping <= vrm_models[i].stepping_to)
  243. return vrm_models[i].vrm_type;
  244. }
  245. return 0;
  246. }
  247. u8 vid_which_vrm(void)
  248. {
  249. struct cpuinfo_x86 *c = &cpu_data(0);
  250. u8 vrm_ret;
  251. if (c->x86 < 6) /* Any CPU with family lower than 6 */
  252. return 0; /* doesn't have VID */
  253. vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
  254. if (vrm_ret == 134)
  255. vrm_ret = get_via_model_d_vrm();
  256. if (vrm_ret == 0)
  257. pr_info("Unknown VRM version of your x86 CPU\n");
  258. return vrm_ret;
  259. }
  260. /* and now for something completely different for the non-x86 world */
  261. #else
  262. u8 vid_which_vrm(void)
  263. {
  264. pr_info("Unknown VRM version of your CPU\n");
  265. return 0;
  266. }
  267. #endif
  268. EXPORT_SYMBOL(vid_which_vrm);
  269. MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
  270. MODULE_DESCRIPTION("hwmon-vid driver");
  271. MODULE_LICENSE("GPL");