aspeed-pwm-tacho.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/errno.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/hwmon.h>
  10. #include <linux/hwmon-sysfs.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #include <linux/reset.h>
  19. #include <linux/sysfs.h>
  20. #include <linux/thermal.h>
  21. /* ASPEED PWM & FAN Tach Register Definition */
  22. #define ASPEED_PTCR_CTRL 0x00
  23. #define ASPEED_PTCR_CLK_CTRL 0x04
  24. #define ASPEED_PTCR_DUTY0_CTRL 0x08
  25. #define ASPEED_PTCR_DUTY1_CTRL 0x0c
  26. #define ASPEED_PTCR_TYPEM_CTRL 0x10
  27. #define ASPEED_PTCR_TYPEM_CTRL1 0x14
  28. #define ASPEED_PTCR_TYPEN_CTRL 0x18
  29. #define ASPEED_PTCR_TYPEN_CTRL1 0x1c
  30. #define ASPEED_PTCR_TACH_SOURCE 0x20
  31. #define ASPEED_PTCR_TRIGGER 0x28
  32. #define ASPEED_PTCR_RESULT 0x2c
  33. #define ASPEED_PTCR_INTR_CTRL 0x30
  34. #define ASPEED_PTCR_INTR_STS 0x34
  35. #define ASPEED_PTCR_TYPEM_LIMIT 0x38
  36. #define ASPEED_PTCR_TYPEN_LIMIT 0x3C
  37. #define ASPEED_PTCR_CTRL_EXT 0x40
  38. #define ASPEED_PTCR_CLK_CTRL_EXT 0x44
  39. #define ASPEED_PTCR_DUTY2_CTRL 0x48
  40. #define ASPEED_PTCR_DUTY3_CTRL 0x4c
  41. #define ASPEED_PTCR_TYPEO_CTRL 0x50
  42. #define ASPEED_PTCR_TYPEO_CTRL1 0x54
  43. #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60
  44. #define ASPEED_PTCR_TYPEO_LIMIT 0x78
  45. /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
  46. #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15
  47. #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6
  48. #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15))
  49. #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14
  50. #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5
  51. #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14))
  52. #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13
  53. #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4
  54. #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13))
  55. #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12
  56. #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3
  57. #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12))
  58. #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x))
  59. #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11)
  60. #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10)
  61. #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9)
  62. #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8)
  63. #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1)
  64. #define ASPEED_PTCR_CTRL_CLK_EN BIT(0)
  65. /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
  66. /* TYPE N */
  67. #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16)
  68. #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24
  69. #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20
  70. #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16
  71. /* TYPE M */
  72. #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0)
  73. #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8
  74. #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4
  75. #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0
  76. /*
  77. * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
  78. * 0/1/2/3 register
  79. */
  80. #define DUTY_CTRL_PWM2_FALL_POINT 24
  81. #define DUTY_CTRL_PWM2_RISE_POINT 16
  82. #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16)
  83. #define DUTY_CTRL_PWM1_FALL_POINT 8
  84. #define DUTY_CTRL_PWM1_RISE_POINT 0
  85. #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0)
  86. /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
  87. #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16))
  88. #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0)
  89. #define TYPE_CTRL_FAN_PERIOD 16
  90. #define TYPE_CTRL_FAN_MODE 4
  91. #define TYPE_CTRL_FAN_DIVISION 1
  92. #define TYPE_CTRL_FAN_TYPE_EN 1
  93. /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
  94. /* bit [0,1] at 0x20, bit [2] at 0x60 */
  95. #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2)
  96. #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2)
  97. #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2))
  98. #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2)
  99. /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
  100. #define RESULT_STATUS_MASK BIT(31)
  101. #define RESULT_VALUE_MASK 0xfffff
  102. /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
  103. #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15
  104. #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6
  105. #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15))
  106. #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14
  107. #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5
  108. #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14))
  109. #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13
  110. #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4
  111. #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13))
  112. #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12
  113. #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3
  114. #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12))
  115. #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11)
  116. #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10)
  117. #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9)
  118. #define ASPEED_PTCR_CTRL_PWME_EN BIT(8)
  119. /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
  120. /* TYPE O */
  121. #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0)
  122. #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8
  123. #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4
  124. #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0
  125. #define PWM_MAX 255
  126. #define BOTH_EDGES 0x02 /* 10b */
  127. #define M_PWM_DIV_H 0x00
  128. #define M_PWM_DIV_L 0x05
  129. #define M_PWM_PERIOD 0x5F
  130. #define M_TACH_CLK_DIV 0x00
  131. /*
  132. * 5:4 Type N fan tach mode selection bit:
  133. * 00: falling
  134. * 01: rising
  135. * 10: both
  136. * 11: reserved.
  137. */
  138. #define M_TACH_MODE 0x02 /* 10b */
  139. #define M_TACH_UNIT 0x0210
  140. #define INIT_FAN_CTRL 0xFF
  141. /* How long we sleep in us while waiting for an RPM result. */
  142. #define ASPEED_RPM_STATUS_SLEEP_USEC 500
  143. #define MAX_CDEV_NAME_LEN 16
  144. struct aspeed_cooling_device {
  145. char name[16];
  146. struct aspeed_pwm_tacho_data *priv;
  147. struct thermal_cooling_device *tcdev;
  148. int pwm_port;
  149. u8 *cooling_levels;
  150. u8 max_state;
  151. u8 cur_state;
  152. };
  153. struct aspeed_pwm_tacho_data {
  154. struct regmap *regmap;
  155. struct reset_control *rst;
  156. unsigned long clk_freq;
  157. bool pwm_present[8];
  158. bool fan_tach_present[16];
  159. u8 type_pwm_clock_unit[3];
  160. u8 type_pwm_clock_division_h[3];
  161. u8 type_pwm_clock_division_l[3];
  162. u8 type_fan_tach_clock_division[3];
  163. u8 type_fan_tach_mode[3];
  164. u16 type_fan_tach_unit[3];
  165. u8 pwm_port_type[8];
  166. u8 pwm_port_fan_ctrl[8];
  167. u8 fan_tach_ch_source[16];
  168. struct aspeed_cooling_device *cdev[8];
  169. const struct attribute_group *groups[3];
  170. };
  171. enum type { TYPEM, TYPEN, TYPEO };
  172. struct type_params {
  173. u32 l_value;
  174. u32 h_value;
  175. u32 unit_value;
  176. u32 clk_ctrl_mask;
  177. u32 clk_ctrl_reg;
  178. u32 ctrl_reg;
  179. u32 ctrl_reg1;
  180. };
  181. static const struct type_params type_params[] = {
  182. [TYPEM] = {
  183. .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
  184. .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
  185. .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
  186. .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
  187. .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
  188. .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
  189. .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
  190. },
  191. [TYPEN] = {
  192. .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
  193. .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
  194. .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
  195. .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
  196. .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
  197. .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
  198. .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
  199. },
  200. [TYPEO] = {
  201. .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
  202. .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
  203. .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
  204. .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
  205. .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
  206. .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
  207. .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
  208. }
  209. };
  210. enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
  211. struct pwm_port_params {
  212. u32 pwm_en;
  213. u32 ctrl_reg;
  214. u32 type_part1;
  215. u32 type_part2;
  216. u32 type_mask;
  217. u32 duty_ctrl_rise_point;
  218. u32 duty_ctrl_fall_point;
  219. u32 duty_ctrl_reg;
  220. u32 duty_ctrl_rise_fall_mask;
  221. };
  222. static const struct pwm_port_params pwm_port_params[] = {
  223. [PWMA] = {
  224. .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
  225. .ctrl_reg = ASPEED_PTCR_CTRL,
  226. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
  227. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
  228. .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
  229. .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
  230. .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
  231. .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
  232. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
  233. },
  234. [PWMB] = {
  235. .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
  236. .ctrl_reg = ASPEED_PTCR_CTRL,
  237. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
  238. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
  239. .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
  240. .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
  241. .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
  242. .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
  243. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
  244. },
  245. [PWMC] = {
  246. .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
  247. .ctrl_reg = ASPEED_PTCR_CTRL,
  248. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
  249. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
  250. .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
  251. .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
  252. .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
  253. .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
  254. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
  255. },
  256. [PWMD] = {
  257. .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
  258. .ctrl_reg = ASPEED_PTCR_CTRL,
  259. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
  260. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
  261. .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
  262. .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
  263. .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
  264. .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
  265. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
  266. },
  267. [PWME] = {
  268. .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
  269. .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
  270. .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
  271. .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
  272. .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
  273. .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
  274. .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
  275. .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
  276. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
  277. },
  278. [PWMF] = {
  279. .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
  280. .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
  281. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
  282. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
  283. .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
  284. .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
  285. .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
  286. .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
  287. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
  288. },
  289. [PWMG] = {
  290. .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
  291. .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
  292. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
  293. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
  294. .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
  295. .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
  296. .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
  297. .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
  298. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
  299. },
  300. [PWMH] = {
  301. .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
  302. .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
  303. .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
  304. .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
  305. .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
  306. .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
  307. .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
  308. .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
  309. .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
  310. }
  311. };
  312. static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
  313. unsigned int val)
  314. {
  315. void __iomem *regs = (void __iomem *)context;
  316. writel(val, regs + reg);
  317. return 0;
  318. }
  319. static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
  320. unsigned int *val)
  321. {
  322. void __iomem *regs = (void __iomem *)context;
  323. *val = readl(regs + reg);
  324. return 0;
  325. }
  326. static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
  327. .reg_bits = 32,
  328. .val_bits = 32,
  329. .reg_stride = 4,
  330. .max_register = ASPEED_PTCR_TYPEO_LIMIT,
  331. .reg_write = regmap_aspeed_pwm_tacho_reg_write,
  332. .reg_read = regmap_aspeed_pwm_tacho_reg_read,
  333. .fast_io = true,
  334. };
  335. static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
  336. {
  337. regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
  338. ASPEED_PTCR_CTRL_CLK_EN,
  339. val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
  340. }
  341. static void aspeed_set_clock_source(struct regmap *regmap, int val)
  342. {
  343. regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
  344. ASPEED_PTCR_CTRL_CLK_SRC,
  345. val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
  346. }
  347. static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
  348. u8 div_high, u8 div_low, u8 unit)
  349. {
  350. u32 reg_value = ((div_high << type_params[type].h_value) |
  351. (div_low << type_params[type].l_value) |
  352. (unit << type_params[type].unit_value));
  353. regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
  354. type_params[type].clk_ctrl_mask, reg_value);
  355. }
  356. static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
  357. bool enable)
  358. {
  359. regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
  360. pwm_port_params[pwm_port].pwm_en,
  361. enable ? pwm_port_params[pwm_port].pwm_en : 0);
  362. }
  363. static void aspeed_set_pwm_port_type(struct regmap *regmap,
  364. u8 pwm_port, u8 type)
  365. {
  366. u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
  367. reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
  368. regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
  369. pwm_port_params[pwm_port].type_mask, reg_value);
  370. }
  371. static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
  372. u8 pwm_port, u8 rising,
  373. u8 falling)
  374. {
  375. u32 reg_value = (rising <<
  376. pwm_port_params[pwm_port].duty_ctrl_rise_point);
  377. reg_value |= (falling <<
  378. pwm_port_params[pwm_port].duty_ctrl_fall_point);
  379. regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
  380. pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
  381. reg_value);
  382. }
  383. static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
  384. bool enable)
  385. {
  386. regmap_update_bits(regmap, type_params[type].ctrl_reg,
  387. TYPE_CTRL_FAN_TYPE_EN,
  388. enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
  389. }
  390. static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
  391. u8 mode, u16 unit, u8 division)
  392. {
  393. u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
  394. (unit << TYPE_CTRL_FAN_PERIOD) |
  395. (division << TYPE_CTRL_FAN_DIVISION));
  396. regmap_update_bits(regmap, type_params[type].ctrl_reg,
  397. TYPE_CTRL_FAN_MASK, reg_value);
  398. regmap_update_bits(regmap, type_params[type].ctrl_reg1,
  399. TYPE_CTRL_FAN1_MASK, unit << 16);
  400. }
  401. static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
  402. bool enable)
  403. {
  404. regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
  405. ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
  406. enable ?
  407. ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
  408. }
  409. static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
  410. u8 fan_tach_ch_source)
  411. {
  412. u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
  413. TACH_PWM_SOURCE_BIT01(fan_tach_ch));
  414. u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
  415. TACH_PWM_SOURCE_BIT2(fan_tach_ch));
  416. regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
  417. TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
  418. reg_value1);
  419. regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
  420. TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
  421. reg_value2);
  422. }
  423. static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
  424. u8 index, u8 fan_ctrl)
  425. {
  426. u16 period, dc_time_on;
  427. period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
  428. period += 1;
  429. dc_time_on = (fan_ctrl * period) / PWM_MAX;
  430. if (dc_time_on == 0) {
  431. aspeed_set_pwm_port_enable(priv->regmap, index, false);
  432. } else {
  433. if (dc_time_on == period)
  434. dc_time_on = 0;
  435. aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
  436. dc_time_on);
  437. aspeed_set_pwm_port_enable(priv->regmap, index, true);
  438. }
  439. }
  440. static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
  441. *priv, u8 type)
  442. {
  443. u32 clk;
  444. u16 tacho_unit;
  445. u8 clk_unit, div_h, div_l, tacho_div;
  446. clk = priv->clk_freq;
  447. clk_unit = priv->type_pwm_clock_unit[type];
  448. div_h = priv->type_pwm_clock_division_h[type];
  449. div_h = 0x1 << div_h;
  450. div_l = priv->type_pwm_clock_division_l[type];
  451. if (div_l == 0)
  452. div_l = 1;
  453. else
  454. div_l = div_l * 2;
  455. tacho_unit = priv->type_fan_tach_unit[type];
  456. tacho_div = priv->type_fan_tach_clock_division[type];
  457. tacho_div = 0x4 << (tacho_div * 2);
  458. return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
  459. }
  460. static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
  461. u8 fan_tach_ch)
  462. {
  463. u32 raw_data, tach_div, clk_source, msec, usec, val;
  464. u8 fan_tach_ch_source, type, mode, both;
  465. int ret;
  466. regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
  467. regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
  468. fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
  469. type = priv->pwm_port_type[fan_tach_ch_source];
  470. msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
  471. usec = msec * 1000;
  472. ret = regmap_read_poll_timeout(
  473. priv->regmap,
  474. ASPEED_PTCR_RESULT,
  475. val,
  476. (val & RESULT_STATUS_MASK),
  477. ASPEED_RPM_STATUS_SLEEP_USEC,
  478. usec);
  479. /* return -ETIMEDOUT if we didn't get an answer. */
  480. if (ret)
  481. return ret;
  482. raw_data = val & RESULT_VALUE_MASK;
  483. tach_div = priv->type_fan_tach_clock_division[type];
  484. /*
  485. * We need the mode to determine if the raw_data is double (from
  486. * counting both edges).
  487. */
  488. mode = priv->type_fan_tach_mode[type];
  489. both = (mode & BOTH_EDGES) ? 1 : 0;
  490. tach_div = (0x4 << both) << (tach_div * 2);
  491. clk_source = priv->clk_freq;
  492. if (raw_data == 0)
  493. return 0;
  494. return (clk_source * 60) / (2 * raw_data * tach_div);
  495. }
  496. static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
  497. const char *buf, size_t count)
  498. {
  499. struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
  500. int index = sensor_attr->index;
  501. int ret;
  502. struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
  503. long fan_ctrl;
  504. ret = kstrtol(buf, 10, &fan_ctrl);
  505. if (ret != 0)
  506. return ret;
  507. if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
  508. return -EINVAL;
  509. if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
  510. return count;
  511. priv->pwm_port_fan_ctrl[index] = fan_ctrl;
  512. aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
  513. return count;
  514. }
  515. static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
  516. char *buf)
  517. {
  518. struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
  519. int index = sensor_attr->index;
  520. struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
  521. return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
  522. }
  523. static ssize_t rpm_show(struct device *dev, struct device_attribute *attr,
  524. char *buf)
  525. {
  526. struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
  527. int index = sensor_attr->index;
  528. int rpm;
  529. struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
  530. rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
  531. if (rpm < 0)
  532. return rpm;
  533. return sprintf(buf, "%d\n", rpm);
  534. }
  535. static umode_t pwm_is_visible(struct kobject *kobj,
  536. struct attribute *a, int index)
  537. {
  538. struct device *dev = container_of(kobj, struct device, kobj);
  539. struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
  540. if (!priv->pwm_present[index])
  541. return 0;
  542. return a->mode;
  543. }
  544. static umode_t fan_dev_is_visible(struct kobject *kobj,
  545. struct attribute *a, int index)
  546. {
  547. struct device *dev = container_of(kobj, struct device, kobj);
  548. struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
  549. if (!priv->fan_tach_present[index])
  550. return 0;
  551. return a->mode;
  552. }
  553. static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
  554. static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
  555. static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
  556. static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
  557. static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4);
  558. static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5);
  559. static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6);
  560. static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7);
  561. static struct attribute *pwm_dev_attrs[] = {
  562. &sensor_dev_attr_pwm1.dev_attr.attr,
  563. &sensor_dev_attr_pwm2.dev_attr.attr,
  564. &sensor_dev_attr_pwm3.dev_attr.attr,
  565. &sensor_dev_attr_pwm4.dev_attr.attr,
  566. &sensor_dev_attr_pwm5.dev_attr.attr,
  567. &sensor_dev_attr_pwm6.dev_attr.attr,
  568. &sensor_dev_attr_pwm7.dev_attr.attr,
  569. &sensor_dev_attr_pwm8.dev_attr.attr,
  570. NULL,
  571. };
  572. static const struct attribute_group pwm_dev_group = {
  573. .attrs = pwm_dev_attrs,
  574. .is_visible = pwm_is_visible,
  575. };
  576. static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
  577. static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1);
  578. static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2);
  579. static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3);
  580. static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4);
  581. static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5);
  582. static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6);
  583. static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7);
  584. static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8);
  585. static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9);
  586. static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10);
  587. static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11);
  588. static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12);
  589. static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13);
  590. static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14);
  591. static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15);
  592. static struct attribute *fan_dev_attrs[] = {
  593. &sensor_dev_attr_fan1_input.dev_attr.attr,
  594. &sensor_dev_attr_fan2_input.dev_attr.attr,
  595. &sensor_dev_attr_fan3_input.dev_attr.attr,
  596. &sensor_dev_attr_fan4_input.dev_attr.attr,
  597. &sensor_dev_attr_fan5_input.dev_attr.attr,
  598. &sensor_dev_attr_fan6_input.dev_attr.attr,
  599. &sensor_dev_attr_fan7_input.dev_attr.attr,
  600. &sensor_dev_attr_fan8_input.dev_attr.attr,
  601. &sensor_dev_attr_fan9_input.dev_attr.attr,
  602. &sensor_dev_attr_fan10_input.dev_attr.attr,
  603. &sensor_dev_attr_fan11_input.dev_attr.attr,
  604. &sensor_dev_attr_fan12_input.dev_attr.attr,
  605. &sensor_dev_attr_fan13_input.dev_attr.attr,
  606. &sensor_dev_attr_fan14_input.dev_attr.attr,
  607. &sensor_dev_attr_fan15_input.dev_attr.attr,
  608. &sensor_dev_attr_fan16_input.dev_attr.attr,
  609. NULL
  610. };
  611. static const struct attribute_group fan_dev_group = {
  612. .attrs = fan_dev_attrs,
  613. .is_visible = fan_dev_is_visible,
  614. };
  615. /*
  616. * The clock type is type M :
  617. * The PWM frequency = 24MHz / (type M clock division L bit *
  618. * type M clock division H bit * (type M PWM period bit + 1))
  619. */
  620. static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
  621. {
  622. priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
  623. priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
  624. priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
  625. aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
  626. M_PWM_DIV_L, M_PWM_PERIOD);
  627. aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
  628. priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
  629. priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
  630. priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
  631. aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
  632. M_TACH_UNIT, M_TACH_CLK_DIV);
  633. }
  634. static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
  635. u8 pwm_port)
  636. {
  637. aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
  638. priv->pwm_present[pwm_port] = true;
  639. priv->pwm_port_type[pwm_port] = TYPEM;
  640. aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
  641. priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
  642. aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
  643. }
  644. static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
  645. u8 *fan_tach_ch,
  646. int count,
  647. u8 pwm_source)
  648. {
  649. u8 val, index;
  650. for (val = 0; val < count; val++) {
  651. index = fan_tach_ch[val];
  652. aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
  653. priv->fan_tach_present[index] = true;
  654. priv->fan_tach_ch_source[index] = pwm_source;
  655. aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
  656. }
  657. }
  658. static int
  659. aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
  660. unsigned long *state)
  661. {
  662. struct aspeed_cooling_device *cdev = tcdev->devdata;
  663. *state = cdev->max_state;
  664. return 0;
  665. }
  666. static int
  667. aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
  668. unsigned long *state)
  669. {
  670. struct aspeed_cooling_device *cdev = tcdev->devdata;
  671. *state = cdev->cur_state;
  672. return 0;
  673. }
  674. static int
  675. aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
  676. unsigned long state)
  677. {
  678. struct aspeed_cooling_device *cdev = tcdev->devdata;
  679. if (state > cdev->max_state)
  680. return -EINVAL;
  681. cdev->cur_state = state;
  682. cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
  683. cdev->cooling_levels[cdev->cur_state];
  684. aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
  685. cdev->cooling_levels[cdev->cur_state]);
  686. return 0;
  687. }
  688. static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
  689. .get_max_state = aspeed_pwm_cz_get_max_state,
  690. .get_cur_state = aspeed_pwm_cz_get_cur_state,
  691. .set_cur_state = aspeed_pwm_cz_set_cur_state,
  692. };
  693. static int aspeed_create_pwm_cooling(struct device *dev,
  694. struct device_node *child,
  695. struct aspeed_pwm_tacho_data *priv,
  696. u32 pwm_port, u8 num_levels)
  697. {
  698. int ret;
  699. struct aspeed_cooling_device *cdev;
  700. cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
  701. if (!cdev)
  702. return -ENOMEM;
  703. cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
  704. if (!cdev->cooling_levels)
  705. return -ENOMEM;
  706. cdev->max_state = num_levels - 1;
  707. ret = of_property_read_u8_array(child, "cooling-levels",
  708. cdev->cooling_levels,
  709. num_levels);
  710. if (ret) {
  711. dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
  712. return ret;
  713. }
  714. snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
  715. cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
  716. cdev->name, cdev, &aspeed_pwm_cool_ops);
  717. if (IS_ERR(cdev->tcdev))
  718. return PTR_ERR(cdev->tcdev);
  719. cdev->priv = priv;
  720. cdev->pwm_port = pwm_port;
  721. priv->cdev[pwm_port] = cdev;
  722. return 0;
  723. }
  724. static int aspeed_create_fan(struct device *dev,
  725. struct device_node *child,
  726. struct aspeed_pwm_tacho_data *priv)
  727. {
  728. u8 *fan_tach_ch;
  729. u32 pwm_port;
  730. int ret, count;
  731. ret = of_property_read_u32(child, "reg", &pwm_port);
  732. if (ret)
  733. return ret;
  734. if (pwm_port >= ARRAY_SIZE(pwm_port_params))
  735. return -EINVAL;
  736. aspeed_create_pwm_port(priv, (u8)pwm_port);
  737. ret = of_property_count_u8_elems(child, "cooling-levels");
  738. if (ret > 0) {
  739. ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
  740. ret);
  741. if (ret)
  742. return ret;
  743. }
  744. count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
  745. if (count < 1)
  746. return -EINVAL;
  747. fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch),
  748. GFP_KERNEL);
  749. if (!fan_tach_ch)
  750. return -ENOMEM;
  751. ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
  752. fan_tach_ch, count);
  753. if (ret)
  754. return ret;
  755. aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
  756. return 0;
  757. }
  758. static void aspeed_pwm_tacho_remove(void *data)
  759. {
  760. struct aspeed_pwm_tacho_data *priv = data;
  761. reset_control_assert(priv->rst);
  762. }
  763. static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
  764. {
  765. struct device *dev = &pdev->dev;
  766. struct device_node *np, *child;
  767. struct aspeed_pwm_tacho_data *priv;
  768. void __iomem *regs;
  769. struct device *hwmon;
  770. struct clk *clk;
  771. int ret;
  772. np = dev->of_node;
  773. regs = devm_platform_ioremap_resource(pdev, 0);
  774. if (IS_ERR(regs))
  775. return PTR_ERR(regs);
  776. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  777. if (!priv)
  778. return -ENOMEM;
  779. priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
  780. &aspeed_pwm_tacho_regmap_config);
  781. if (IS_ERR(priv->regmap))
  782. return PTR_ERR(priv->regmap);
  783. priv->rst = devm_reset_control_get_exclusive(dev, NULL);
  784. if (IS_ERR(priv->rst)) {
  785. dev_err(dev,
  786. "missing or invalid reset controller device tree entry");
  787. return PTR_ERR(priv->rst);
  788. }
  789. reset_control_deassert(priv->rst);
  790. ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv);
  791. if (ret)
  792. return ret;
  793. regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
  794. regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
  795. clk = devm_clk_get(dev, NULL);
  796. if (IS_ERR(clk))
  797. return -ENODEV;
  798. priv->clk_freq = clk_get_rate(clk);
  799. aspeed_set_clock_enable(priv->regmap, true);
  800. aspeed_set_clock_source(priv->regmap, 0);
  801. aspeed_create_type(priv);
  802. for_each_child_of_node(np, child) {
  803. ret = aspeed_create_fan(dev, child, priv);
  804. if (ret) {
  805. of_node_put(child);
  806. return ret;
  807. }
  808. }
  809. priv->groups[0] = &pwm_dev_group;
  810. priv->groups[1] = &fan_dev_group;
  811. priv->groups[2] = NULL;
  812. hwmon = devm_hwmon_device_register_with_groups(dev,
  813. "aspeed_pwm_tacho",
  814. priv, priv->groups);
  815. return PTR_ERR_OR_ZERO(hwmon);
  816. }
  817. static const struct of_device_id of_pwm_tacho_match_table[] = {
  818. { .compatible = "aspeed,ast2400-pwm-tacho", },
  819. { .compatible = "aspeed,ast2500-pwm-tacho", },
  820. {},
  821. };
  822. MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
  823. static struct platform_driver aspeed_pwm_tacho_driver = {
  824. .probe = aspeed_pwm_tacho_probe,
  825. .driver = {
  826. .name = "aspeed_pwm_tacho",
  827. .of_match_table = of_pwm_tacho_match_table,
  828. },
  829. };
  830. module_platform_driver(aspeed_pwm_tacho_driver);
  831. MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
  832. MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
  833. MODULE_LICENSE("GPL");