abituguru3.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * abituguru3.c
  4. *
  5. * Copyright (c) 2006-2008 Hans de Goede <hdegoede@redhat.com>
  6. * Copyright (c) 2008 Alistair John Strachan <alistair@devzero.co.uk>
  7. */
  8. /*
  9. * This driver supports the sensor part of revision 3 of the custom Abit uGuru
  10. * chip found on newer Abit uGuru motherboards. Note: because of lack of specs
  11. * only reading the sensors and their settings is supported.
  12. */
  13. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/slab.h>
  17. #include <linux/jiffies.h>
  18. #include <linux/mutex.h>
  19. #include <linux/err.h>
  20. #include <linux/delay.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/hwmon.h>
  23. #include <linux/hwmon-sysfs.h>
  24. #include <linux/dmi.h>
  25. #include <linux/io.h>
  26. /* uGuru3 bank addresses */
  27. #define ABIT_UGURU3_SETTINGS_BANK 0x01
  28. #define ABIT_UGURU3_SENSORS_BANK 0x08
  29. #define ABIT_UGURU3_MISC_BANK 0x09
  30. #define ABIT_UGURU3_ALARMS_START 0x1E
  31. #define ABIT_UGURU3_SETTINGS_START 0x24
  32. #define ABIT_UGURU3_VALUES_START 0x80
  33. #define ABIT_UGURU3_BOARD_ID 0x0A
  34. /* uGuru3 sensor bank flags */ /* Alarm if: */
  35. #define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */
  36. #define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */
  37. #define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */
  38. #define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */
  39. #define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */
  40. #define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */
  41. #define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */
  42. #define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */
  43. #define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */
  44. /* sensor types */
  45. #define ABIT_UGURU3_IN_SENSOR 0
  46. #define ABIT_UGURU3_TEMP_SENSOR 1
  47. #define ABIT_UGURU3_FAN_SENSOR 2
  48. /*
  49. * Timeouts / Retries, if these turn out to need a lot of fiddling we could
  50. * convert them to params. Determined by trial and error. I assume this is
  51. * cpu-speed independent, since the ISA-bus and not the CPU should be the
  52. * bottleneck.
  53. */
  54. #define ABIT_UGURU3_WAIT_TIMEOUT 250
  55. /*
  56. * Normally the 0xAC at the end of synchronize() is reported after the
  57. * first read, but sometimes not and we need to poll
  58. */
  59. #define ABIT_UGURU3_SYNCHRONIZE_TIMEOUT 5
  60. /* utility macros */
  61. #define ABIT_UGURU3_NAME "abituguru3"
  62. #define ABIT_UGURU3_DEBUG(format, arg...) \
  63. do { \
  64. if (verbose) \
  65. pr_debug(format , ## arg); \
  66. } while (0)
  67. /* Macros to help calculate the sysfs_names array length */
  68. #define ABIT_UGURU3_MAX_NO_SENSORS 26
  69. /*
  70. * sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0,
  71. * in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0
  72. */
  73. #define ABIT_UGURU3_IN_NAMES_LENGTH \
  74. (11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11)
  75. /*
  76. * sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0,
  77. * temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0,
  78. * temp??_label\0
  79. */
  80. #define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13)
  81. /*
  82. * sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0,
  83. * fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0
  84. */
  85. #define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12)
  86. /*
  87. * Worst case scenario 16 in sensors (longest names_length) and the rest
  88. * temp sensors (second longest names_length).
  89. */
  90. #define ABIT_UGURU3_SYSFS_NAMES_LENGTH (16 * ABIT_UGURU3_IN_NAMES_LENGTH + \
  91. (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
  92. /*
  93. * All the macros below are named identical to the openguru2 program
  94. * reverse engineered by Louis Kruger, hence the names might not be 100%
  95. * logical. I could come up with better names, but I prefer keeping the names
  96. * identical so that this driver can be compared with his work more easily.
  97. */
  98. /* Two i/o-ports are used by uGuru */
  99. #define ABIT_UGURU3_BASE 0x00E0
  100. #define ABIT_UGURU3_CMD 0x00
  101. #define ABIT_UGURU3_DATA 0x04
  102. #define ABIT_UGURU3_REGION_LENGTH 5
  103. /*
  104. * The wait_xxx functions return this on success and the last contents
  105. * of the DATA register (0-255) on failure.
  106. */
  107. #define ABIT_UGURU3_SUCCESS -1
  108. /* uGuru status flags */
  109. #define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01
  110. #define ABIT_UGURU3_STATUS_BUSY 0x02
  111. /* Structures */
  112. struct abituguru3_sensor_info {
  113. const char *name;
  114. int port;
  115. int type;
  116. int multiplier;
  117. int divisor;
  118. int offset;
  119. };
  120. /* Avoid use of flexible array members */
  121. #define ABIT_UGURU3_MAX_DMI_NAMES 2
  122. struct abituguru3_motherboard_info {
  123. u16 id;
  124. const char *dmi_name[ABIT_UGURU3_MAX_DMI_NAMES + 1];
  125. /* + 1 -> end of sensors indicated by a sensor with name == NULL */
  126. struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1];
  127. };
  128. /*
  129. * For the Abit uGuru, we need to keep some data in memory.
  130. * The structure is dynamically allocated, at the same time when a new
  131. * abituguru3 device is allocated.
  132. */
  133. struct abituguru3_data {
  134. struct device *hwmon_dev; /* hwmon registered device */
  135. struct mutex update_lock; /* protect access to data and uGuru */
  136. unsigned short addr; /* uguru base address */
  137. char valid; /* !=0 if following fields are valid */
  138. unsigned long last_updated; /* In jiffies */
  139. /*
  140. * For convenience the sysfs attr and their names are generated
  141. * automatically. We have max 10 entries per sensor (for in sensors)
  142. */
  143. struct sensor_device_attribute_2 sysfs_attr[ABIT_UGURU3_MAX_NO_SENSORS
  144. * 10];
  145. /* Buffer to store the dynamically generated sysfs names */
  146. char sysfs_names[ABIT_UGURU3_SYSFS_NAMES_LENGTH];
  147. /* Pointer to the sensors info for the detected motherboard */
  148. const struct abituguru3_sensor_info *sensors;
  149. /*
  150. * The abituguru3 supports up to 48 sensors, and thus has registers
  151. * sets for 48 sensors, for convenience reasons / simplicity of the
  152. * code we always read and store all registers for all 48 sensors
  153. */
  154. /* Alarms for all 48 sensors (1 bit per sensor) */
  155. u8 alarms[48/8];
  156. /* Value of all 48 sensors */
  157. u8 value[48];
  158. /*
  159. * Settings of all 48 sensors, note in and temp sensors (the first 32
  160. * sensors) have 3 bytes of settings, while fans only have 2 bytes,
  161. * for convenience we use 3 bytes for all sensors
  162. */
  163. u8 settings[48][3];
  164. };
  165. /* Constants */
  166. static const struct abituguru3_motherboard_info abituguru3_motherboards[] = {
  167. { 0x000C, { NULL } /* Unknown, need DMI string */, {
  168. { "CPU Core", 0, 0, 10, 1, 0 },
  169. { "DDR", 1, 0, 10, 1, 0 },
  170. { "DDR VTT", 2, 0, 10, 1, 0 },
  171. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  172. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  173. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  174. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  175. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  176. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  177. { "ATX +5V", 9, 0, 30, 1, 0 },
  178. { "+3.3V", 10, 0, 20, 1, 0 },
  179. { "5VSB", 11, 0, 30, 1, 0 },
  180. { "CPU", 24, 1, 1, 1, 0 },
  181. { "System", 25, 1, 1, 1, 0 },
  182. { "PWM", 26, 1, 1, 1, 0 },
  183. { "CPU Fan", 32, 2, 60, 1, 0 },
  184. { "NB Fan", 33, 2, 60, 1, 0 },
  185. { "SYS FAN", 34, 2, 60, 1, 0 },
  186. { "AUX1 Fan", 35, 2, 60, 1, 0 },
  187. { NULL, 0, 0, 0, 0, 0 } }
  188. },
  189. { 0x000D, { NULL } /* Abit AW8, need DMI string */, {
  190. { "CPU Core", 0, 0, 10, 1, 0 },
  191. { "DDR", 1, 0, 10, 1, 0 },
  192. { "DDR VTT", 2, 0, 10, 1, 0 },
  193. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  194. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  195. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  196. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  197. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  198. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  199. { "ATX +5V", 9, 0, 30, 1, 0 },
  200. { "+3.3V", 10, 0, 20, 1, 0 },
  201. { "5VSB", 11, 0, 30, 1, 0 },
  202. { "CPU", 24, 1, 1, 1, 0 },
  203. { "System", 25, 1, 1, 1, 0 },
  204. { "PWM1", 26, 1, 1, 1, 0 },
  205. { "PWM2", 27, 1, 1, 1, 0 },
  206. { "PWM3", 28, 1, 1, 1, 0 },
  207. { "PWM4", 29, 1, 1, 1, 0 },
  208. { "CPU Fan", 32, 2, 60, 1, 0 },
  209. { "NB Fan", 33, 2, 60, 1, 0 },
  210. { "SYS Fan", 34, 2, 60, 1, 0 },
  211. { "AUX1 Fan", 35, 2, 60, 1, 0 },
  212. { "AUX2 Fan", 36, 2, 60, 1, 0 },
  213. { "AUX3 Fan", 37, 2, 60, 1, 0 },
  214. { "AUX4 Fan", 38, 2, 60, 1, 0 },
  215. { "AUX5 Fan", 39, 2, 60, 1, 0 },
  216. { NULL, 0, 0, 0, 0, 0 } }
  217. },
  218. { 0x000E, { NULL } /* AL-8, need DMI string */, {
  219. { "CPU Core", 0, 0, 10, 1, 0 },
  220. { "DDR", 1, 0, 10, 1, 0 },
  221. { "DDR VTT", 2, 0, 10, 1, 0 },
  222. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  223. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  224. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  225. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  226. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  227. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  228. { "ATX +5V", 9, 0, 30, 1, 0 },
  229. { "+3.3V", 10, 0, 20, 1, 0 },
  230. { "5VSB", 11, 0, 30, 1, 0 },
  231. { "CPU", 24, 1, 1, 1, 0 },
  232. { "System", 25, 1, 1, 1, 0 },
  233. { "PWM", 26, 1, 1, 1, 0 },
  234. { "CPU Fan", 32, 2, 60, 1, 0 },
  235. { "NB Fan", 33, 2, 60, 1, 0 },
  236. { "SYS Fan", 34, 2, 60, 1, 0 },
  237. { NULL, 0, 0, 0, 0, 0 } }
  238. },
  239. { 0x000F, { NULL } /* Unknown, need DMI string */, {
  240. { "CPU Core", 0, 0, 10, 1, 0 },
  241. { "DDR", 1, 0, 10, 1, 0 },
  242. { "DDR VTT", 2, 0, 10, 1, 0 },
  243. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  244. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  245. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  246. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  247. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  248. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  249. { "ATX +5V", 9, 0, 30, 1, 0 },
  250. { "+3.3V", 10, 0, 20, 1, 0 },
  251. { "5VSB", 11, 0, 30, 1, 0 },
  252. { "CPU", 24, 1, 1, 1, 0 },
  253. { "System", 25, 1, 1, 1, 0 },
  254. { "PWM", 26, 1, 1, 1, 0 },
  255. { "CPU Fan", 32, 2, 60, 1, 0 },
  256. { "NB Fan", 33, 2, 60, 1, 0 },
  257. { "SYS Fan", 34, 2, 60, 1, 0 },
  258. { NULL, 0, 0, 0, 0, 0 } }
  259. },
  260. { 0x0010, { NULL } /* Abit NI8 SLI GR, need DMI string */, {
  261. { "CPU Core", 0, 0, 10, 1, 0 },
  262. { "DDR", 1, 0, 10, 1, 0 },
  263. { "DDR VTT", 2, 0, 10, 1, 0 },
  264. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  265. { "NB 1.4V", 4, 0, 10, 1, 0 },
  266. { "SB 1.5V", 6, 0, 10, 1, 0 },
  267. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  268. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  269. { "ATX +5V", 9, 0, 30, 1, 0 },
  270. { "+3.3V", 10, 0, 20, 1, 0 },
  271. { "5VSB", 11, 0, 30, 1, 0 },
  272. { "CPU", 24, 1, 1, 1, 0 },
  273. { "SYS", 25, 1, 1, 1, 0 },
  274. { "PWM", 26, 1, 1, 1, 0 },
  275. { "CPU Fan", 32, 2, 60, 1, 0 },
  276. { "NB Fan", 33, 2, 60, 1, 0 },
  277. { "SYS Fan", 34, 2, 60, 1, 0 },
  278. { "AUX1 Fan", 35, 2, 60, 1, 0 },
  279. { "OTES1 Fan", 36, 2, 60, 1, 0 },
  280. { NULL, 0, 0, 0, 0, 0 } }
  281. },
  282. { 0x0011, { "AT8 32X", NULL }, {
  283. { "CPU Core", 0, 0, 10, 1, 0 },
  284. { "DDR", 1, 0, 20, 1, 0 },
  285. { "DDR VTT", 2, 0, 10, 1, 0 },
  286. { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
  287. { "NB 1.8V", 4, 0, 10, 1, 0 },
  288. { "NB 1.8V Dual", 5, 0, 10, 1, 0 },
  289. { "HTV 1.2", 3, 0, 10, 1, 0 },
  290. { "PCIE 1.2V", 12, 0, 10, 1, 0 },
  291. { "NB 1.2V", 13, 0, 10, 1, 0 },
  292. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  293. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  294. { "ATX +5V", 9, 0, 30, 1, 0 },
  295. { "+3.3V", 10, 0, 20, 1, 0 },
  296. { "5VSB", 11, 0, 30, 1, 0 },
  297. { "CPU", 24, 1, 1, 1, 0 },
  298. { "NB", 25, 1, 1, 1, 0 },
  299. { "System", 26, 1, 1, 1, 0 },
  300. { "PWM", 27, 1, 1, 1, 0 },
  301. { "CPU Fan", 32, 2, 60, 1, 0 },
  302. { "NB Fan", 33, 2, 60, 1, 0 },
  303. { "SYS Fan", 34, 2, 60, 1, 0 },
  304. { "AUX1 Fan", 35, 2, 60, 1, 0 },
  305. { "AUX2 Fan", 36, 2, 60, 1, 0 },
  306. { "AUX3 Fan", 37, 2, 60, 1, 0 },
  307. { NULL, 0, 0, 0, 0, 0 } }
  308. },
  309. { 0x0012, { NULL } /* Abit AN8 32X, need DMI string */, {
  310. { "CPU Core", 0, 0, 10, 1, 0 },
  311. { "DDR", 1, 0, 20, 1, 0 },
  312. { "DDR VTT", 2, 0, 10, 1, 0 },
  313. { "HyperTransport", 3, 0, 10, 1, 0 },
  314. { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
  315. { "NB", 4, 0, 10, 1, 0 },
  316. { "SB", 6, 0, 10, 1, 0 },
  317. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  318. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  319. { "ATX +5V", 9, 0, 30, 1, 0 },
  320. { "+3.3V", 10, 0, 20, 1, 0 },
  321. { "5VSB", 11, 0, 30, 1, 0 },
  322. { "CPU", 24, 1, 1, 1, 0 },
  323. { "SYS", 25, 1, 1, 1, 0 },
  324. { "PWM", 26, 1, 1, 1, 0 },
  325. { "CPU Fan", 32, 2, 60, 1, 0 },
  326. { "NB Fan", 33, 2, 60, 1, 0 },
  327. { "SYS Fan", 34, 2, 60, 1, 0 },
  328. { "AUX1 Fan", 36, 2, 60, 1, 0 },
  329. { NULL, 0, 0, 0, 0, 0 } }
  330. },
  331. { 0x0013, { NULL } /* Abit AW8D, need DMI string */, {
  332. { "CPU Core", 0, 0, 10, 1, 0 },
  333. { "DDR", 1, 0, 10, 1, 0 },
  334. { "DDR VTT", 2, 0, 10, 1, 0 },
  335. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  336. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  337. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  338. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  339. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  340. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  341. { "ATX +5V", 9, 0, 30, 1, 0 },
  342. { "+3.3V", 10, 0, 20, 1, 0 },
  343. { "5VSB", 11, 0, 30, 1, 0 },
  344. { "CPU", 24, 1, 1, 1, 0 },
  345. { "System", 25, 1, 1, 1, 0 },
  346. { "PWM1", 26, 1, 1, 1, 0 },
  347. { "PWM2", 27, 1, 1, 1, 0 },
  348. { "PWM3", 28, 1, 1, 1, 0 },
  349. { "PWM4", 29, 1, 1, 1, 0 },
  350. { "CPU Fan", 32, 2, 60, 1, 0 },
  351. { "NB Fan", 33, 2, 60, 1, 0 },
  352. { "SYS Fan", 34, 2, 60, 1, 0 },
  353. { "AUX1 Fan", 35, 2, 60, 1, 0 },
  354. { "AUX2 Fan", 36, 2, 60, 1, 0 },
  355. { "AUX3 Fan", 37, 2, 60, 1, 0 },
  356. { "AUX4 Fan", 38, 2, 60, 1, 0 },
  357. { "AUX5 Fan", 39, 2, 60, 1, 0 },
  358. { NULL, 0, 0, 0, 0, 0 } }
  359. },
  360. { 0x0014, { "AB9", "AB9 Pro", NULL }, {
  361. { "CPU Core", 0, 0, 10, 1, 0 },
  362. { "DDR", 1, 0, 10, 1, 0 },
  363. { "DDR VTT", 2, 0, 10, 1, 0 },
  364. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  365. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  366. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  367. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  368. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  369. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  370. { "ATX +5V", 9, 0, 30, 1, 0 },
  371. { "+3.3V", 10, 0, 20, 1, 0 },
  372. { "5VSB", 11, 0, 30, 1, 0 },
  373. { "CPU", 24, 1, 1, 1, 0 },
  374. { "System", 25, 1, 1, 1, 0 },
  375. { "PWM", 26, 1, 1, 1, 0 },
  376. { "CPU Fan", 32, 2, 60, 1, 0 },
  377. { "NB Fan", 33, 2, 60, 1, 0 },
  378. { "SYS Fan", 34, 2, 60, 1, 0 },
  379. { NULL, 0, 0, 0, 0, 0 } }
  380. },
  381. { 0x0015, { NULL } /* Unknown, need DMI string */, {
  382. { "CPU Core", 0, 0, 10, 1, 0 },
  383. { "DDR", 1, 0, 20, 1, 0 },
  384. { "DDR VTT", 2, 0, 10, 1, 0 },
  385. { "HyperTransport", 3, 0, 10, 1, 0 },
  386. { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
  387. { "NB", 4, 0, 10, 1, 0 },
  388. { "SB", 6, 0, 10, 1, 0 },
  389. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  390. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  391. { "ATX +5V", 9, 0, 30, 1, 0 },
  392. { "+3.3V", 10, 0, 20, 1, 0 },
  393. { "5VSB", 11, 0, 30, 1, 0 },
  394. { "CPU", 24, 1, 1, 1, 0 },
  395. { "SYS", 25, 1, 1, 1, 0 },
  396. { "PWM", 26, 1, 1, 1, 0 },
  397. { "CPU Fan", 32, 2, 60, 1, 0 },
  398. { "NB Fan", 33, 2, 60, 1, 0 },
  399. { "SYS Fan", 34, 2, 60, 1, 0 },
  400. { "AUX1 Fan", 33, 2, 60, 1, 0 },
  401. { "AUX2 Fan", 35, 2, 60, 1, 0 },
  402. { "AUX3 Fan", 36, 2, 60, 1, 0 },
  403. { NULL, 0, 0, 0, 0, 0 } }
  404. },
  405. { 0x0016, { "AW9D-MAX", NULL }, {
  406. { "CPU Core", 0, 0, 10, 1, 0 },
  407. { "DDR2", 1, 0, 20, 1, 0 },
  408. { "DDR2 VTT", 2, 0, 10, 1, 0 },
  409. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  410. { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
  411. { "MCH 2.5V", 5, 0, 20, 1, 0 },
  412. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  413. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  414. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  415. { "ATX +5V", 9, 0, 30, 1, 0 },
  416. { "+3.3V", 10, 0, 20, 1, 0 },
  417. { "5VSB", 11, 0, 30, 1, 0 },
  418. { "CPU", 24, 1, 1, 1, 0 },
  419. { "System", 25, 1, 1, 1, 0 },
  420. { "PWM1", 26, 1, 1, 1, 0 },
  421. { "PWM2", 27, 1, 1, 1, 0 },
  422. { "PWM3", 28, 1, 1, 1, 0 },
  423. { "PWM4", 29, 1, 1, 1, 0 },
  424. { "CPU Fan", 32, 2, 60, 1, 0 },
  425. { "NB Fan", 33, 2, 60, 1, 0 },
  426. { "SYS Fan", 34, 2, 60, 1, 0 },
  427. { "AUX1 Fan", 35, 2, 60, 1, 0 },
  428. { "AUX2 Fan", 36, 2, 60, 1, 0 },
  429. { "AUX3 Fan", 37, 2, 60, 1, 0 },
  430. { "OTES1 Fan", 38, 2, 60, 1, 0 },
  431. { NULL, 0, 0, 0, 0, 0 } }
  432. },
  433. { 0x0017, { NULL } /* Unknown, need DMI string */, {
  434. { "CPU Core", 0, 0, 10, 1, 0 },
  435. { "DDR2", 1, 0, 20, 1, 0 },
  436. { "DDR2 VTT", 2, 0, 10, 1, 0 },
  437. { "HyperTransport", 3, 0, 10, 1, 0 },
  438. { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
  439. { "NB 1.8V", 4, 0, 10, 1, 0 },
  440. { "NB 1.2V ", 13, 0, 10, 1, 0 },
  441. { "SB 1.2V", 5, 0, 10, 1, 0 },
  442. { "PCIE 1.2V", 12, 0, 10, 1, 0 },
  443. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  444. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  445. { "ATX +5V", 9, 0, 30, 1, 0 },
  446. { "ATX +3.3V", 10, 0, 20, 1, 0 },
  447. { "ATX 5VSB", 11, 0, 30, 1, 0 },
  448. { "CPU", 24, 1, 1, 1, 0 },
  449. { "System", 26, 1, 1, 1, 0 },
  450. { "PWM", 27, 1, 1, 1, 0 },
  451. { "CPU FAN", 32, 2, 60, 1, 0 },
  452. { "SYS FAN", 34, 2, 60, 1, 0 },
  453. { "AUX1 FAN", 35, 2, 60, 1, 0 },
  454. { "AUX2 FAN", 36, 2, 60, 1, 0 },
  455. { "AUX3 FAN", 37, 2, 60, 1, 0 },
  456. { NULL, 0, 0, 0, 0, 0 } }
  457. },
  458. { 0x0018, { "AB9 QuadGT", NULL }, {
  459. { "CPU Core", 0, 0, 10, 1, 0 },
  460. { "DDR2", 1, 0, 20, 1, 0 },
  461. { "DDR2 VTT", 2, 0, 10, 1, 0 },
  462. { "CPU VTT", 3, 0, 10, 1, 0 },
  463. { "MCH 1.25V", 4, 0, 10, 1, 0 },
  464. { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
  465. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  466. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  467. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  468. { "ATX +5V", 9, 0, 30, 1, 0 },
  469. { "+3.3V", 10, 0, 20, 1, 0 },
  470. { "5VSB", 11, 0, 30, 1, 0 },
  471. { "CPU", 24, 1, 1, 1, 0 },
  472. { "System", 25, 1, 1, 1, 0 },
  473. { "PWM Phase1", 26, 1, 1, 1, 0 },
  474. { "PWM Phase2", 27, 1, 1, 1, 0 },
  475. { "PWM Phase3", 28, 1, 1, 1, 0 },
  476. { "PWM Phase4", 29, 1, 1, 1, 0 },
  477. { "PWM Phase5", 30, 1, 1, 1, 0 },
  478. { "CPU Fan", 32, 2, 60, 1, 0 },
  479. { "SYS Fan", 34, 2, 60, 1, 0 },
  480. { "AUX1 Fan", 33, 2, 60, 1, 0 },
  481. { "AUX2 Fan", 35, 2, 60, 1, 0 },
  482. { "AUX3 Fan", 36, 2, 60, 1, 0 },
  483. { NULL, 0, 0, 0, 0, 0 } }
  484. },
  485. { 0x0019, { "IN9 32X MAX", NULL }, {
  486. { "CPU Core", 7, 0, 10, 1, 0 },
  487. { "DDR2", 13, 0, 20, 1, 0 },
  488. { "DDR2 VTT", 14, 0, 10, 1, 0 },
  489. { "CPU VTT", 3, 0, 20, 1, 0 },
  490. { "NB 1.2V", 4, 0, 10, 1, 0 },
  491. { "SB 1.5V", 6, 0, 10, 1, 0 },
  492. { "HyperTransport", 5, 0, 10, 1, 0 },
  493. { "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 },
  494. { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
  495. { "ATX +5V", 9, 0, 30, 1, 0 },
  496. { "ATX +3.3V", 10, 0, 20, 1, 0 },
  497. { "ATX 5VSB", 11, 0, 30, 1, 0 },
  498. { "CPU", 24, 1, 1, 1, 0 },
  499. { "System", 25, 1, 1, 1, 0 },
  500. { "PWM Phase1", 26, 1, 1, 1, 0 },
  501. { "PWM Phase2", 27, 1, 1, 1, 0 },
  502. { "PWM Phase3", 28, 1, 1, 1, 0 },
  503. { "PWM Phase4", 29, 1, 1, 1, 0 },
  504. { "PWM Phase5", 30, 1, 1, 1, 0 },
  505. { "CPU FAN", 32, 2, 60, 1, 0 },
  506. { "SYS FAN", 34, 2, 60, 1, 0 },
  507. { "AUX1 FAN", 33, 2, 60, 1, 0 },
  508. { "AUX2 FAN", 35, 2, 60, 1, 0 },
  509. { "AUX3 FAN", 36, 2, 60, 1, 0 },
  510. { NULL, 0, 0, 0, 0, 0 } }
  511. },
  512. { 0x001A, { "IP35 Pro", "IP35 Pro XE", NULL }, {
  513. { "CPU Core", 0, 0, 10, 1, 0 },
  514. { "DDR2", 1, 0, 20, 1, 0 },
  515. { "DDR2 VTT", 2, 0, 10, 1, 0 },
  516. { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
  517. { "MCH 1.25V", 4, 0, 10, 1, 0 },
  518. { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
  519. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  520. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  521. { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
  522. { "ATX +5V", 9, 0, 30, 1, 0 },
  523. { "+3.3V", 10, 0, 20, 1, 0 },
  524. { "5VSB", 11, 0, 30, 1, 0 },
  525. { "CPU", 24, 1, 1, 1, 0 },
  526. { "System", 25, 1, 1, 1, 0 },
  527. { "PWM", 26, 1, 1, 1, 0 },
  528. { "PWM Phase2", 27, 1, 1, 1, 0 },
  529. { "PWM Phase3", 28, 1, 1, 1, 0 },
  530. { "PWM Phase4", 29, 1, 1, 1, 0 },
  531. { "PWM Phase5", 30, 1, 1, 1, 0 },
  532. { "CPU Fan", 32, 2, 60, 1, 0 },
  533. { "SYS Fan", 34, 2, 60, 1, 0 },
  534. { "AUX1 Fan", 33, 2, 60, 1, 0 },
  535. { "AUX2 Fan", 35, 2, 60, 1, 0 },
  536. { "AUX3 Fan", 36, 2, 60, 1, 0 },
  537. { "AUX4 Fan", 37, 2, 60, 1, 0 },
  538. { NULL, 0, 0, 0, 0, 0 } }
  539. },
  540. { 0x001B, { NULL } /* Unknown, need DMI string */, {
  541. { "CPU Core", 0, 0, 10, 1, 0 },
  542. { "DDR3", 1, 0, 20, 1, 0 },
  543. { "DDR3 VTT", 2, 0, 10, 1, 0 },
  544. { "CPU VTT", 3, 0, 10, 1, 0 },
  545. { "MCH 1.25V", 4, 0, 10, 1, 0 },
  546. { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
  547. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  548. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  549. { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
  550. { "ATX +5V", 9, 0, 30, 1, 0 },
  551. { "+3.3V", 10, 0, 20, 1, 0 },
  552. { "5VSB", 11, 0, 30, 1, 0 },
  553. { "CPU", 24, 1, 1, 1, 0 },
  554. { "System", 25, 1, 1, 1, 0 },
  555. { "PWM Phase1", 26, 1, 1, 1, 0 },
  556. { "PWM Phase2", 27, 1, 1, 1, 0 },
  557. { "PWM Phase3", 28, 1, 1, 1, 0 },
  558. { "PWM Phase4", 29, 1, 1, 1, 0 },
  559. { "PWM Phase5", 30, 1, 1, 1, 0 },
  560. { "CPU Fan", 32, 2, 60, 1, 0 },
  561. { "SYS Fan", 34, 2, 60, 1, 0 },
  562. { "AUX1 Fan", 33, 2, 60, 1, 0 },
  563. { "AUX2 Fan", 35, 2, 60, 1, 0 },
  564. { "AUX3 Fan", 36, 2, 60, 1, 0 },
  565. { NULL, 0, 0, 0, 0, 0 } }
  566. },
  567. { 0x001C, { "IX38 QuadGT", NULL }, {
  568. { "CPU Core", 0, 0, 10, 1, 0 },
  569. { "DDR2", 1, 0, 20, 1, 0 },
  570. { "DDR2 VTT", 2, 0, 10, 1, 0 },
  571. { "CPU VTT", 3, 0, 10, 1, 0 },
  572. { "MCH 1.25V", 4, 0, 10, 1, 0 },
  573. { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
  574. { "ICH 1.05V", 6, 0, 10, 1, 0 },
  575. { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
  576. { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
  577. { "ATX +5V", 9, 0, 30, 1, 0 },
  578. { "+3.3V", 10, 0, 20, 1, 0 },
  579. { "5VSB", 11, 0, 30, 1, 0 },
  580. { "CPU", 24, 1, 1, 1, 0 },
  581. { "System", 25, 1, 1, 1, 0 },
  582. { "PWM Phase1", 26, 1, 1, 1, 0 },
  583. { "PWM Phase2", 27, 1, 1, 1, 0 },
  584. { "PWM Phase3", 28, 1, 1, 1, 0 },
  585. { "PWM Phase4", 29, 1, 1, 1, 0 },
  586. { "PWM Phase5", 30, 1, 1, 1, 0 },
  587. { "CPU Fan", 32, 2, 60, 1, 0 },
  588. { "SYS Fan", 34, 2, 60, 1, 0 },
  589. { "AUX1 Fan", 33, 2, 60, 1, 0 },
  590. { "AUX2 Fan", 35, 2, 60, 1, 0 },
  591. { "AUX3 Fan", 36, 2, 60, 1, 0 },
  592. { NULL, 0, 0, 0, 0, 0 } }
  593. },
  594. { 0x0000, { NULL }, { { NULL, 0, 0, 0, 0, 0 } } }
  595. };
  596. /* Insmod parameters */
  597. static bool force;
  598. module_param(force, bool, 0);
  599. MODULE_PARM_DESC(force, "Set to one to force detection.");
  600. /* Default verbose is 1, since this driver is still in the testing phase */
  601. static bool verbose = 1;
  602. module_param(verbose, bool, 0644);
  603. MODULE_PARM_DESC(verbose, "Enable/disable verbose error reporting");
  604. static const char *never_happen = "This should never happen.";
  605. static const char *report_this =
  606. "Please report this to the abituguru3 maintainer (see MAINTAINERS)";
  607. /* wait while the uguru is busy (usually after a write) */
  608. static int abituguru3_wait_while_busy(struct abituguru3_data *data)
  609. {
  610. u8 x;
  611. int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
  612. while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
  613. ABIT_UGURU3_STATUS_BUSY) {
  614. timeout--;
  615. if (timeout == 0)
  616. return x;
  617. /*
  618. * sleep a bit before our last try, to give the uGuru3 one
  619. * last chance to respond.
  620. */
  621. if (timeout == 1)
  622. msleep(1);
  623. }
  624. return ABIT_UGURU3_SUCCESS;
  625. }
  626. /* wait till uguru is ready to be read */
  627. static int abituguru3_wait_for_read(struct abituguru3_data *data)
  628. {
  629. u8 x;
  630. int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
  631. while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
  632. ABIT_UGURU3_STATUS_READY_FOR_READ)) {
  633. timeout--;
  634. if (timeout == 0)
  635. return x;
  636. /*
  637. * sleep a bit before our last try, to give the uGuru3 one
  638. * last chance to respond.
  639. */
  640. if (timeout == 1)
  641. msleep(1);
  642. }
  643. return ABIT_UGURU3_SUCCESS;
  644. }
  645. /*
  646. * This synchronizes us with the uGuru3's protocol state machine, this
  647. * must be done before each command.
  648. */
  649. static int abituguru3_synchronize(struct abituguru3_data *data)
  650. {
  651. int x, timeout = ABIT_UGURU3_SYNCHRONIZE_TIMEOUT;
  652. x = abituguru3_wait_while_busy(data);
  653. if (x != ABIT_UGURU3_SUCCESS) {
  654. ABIT_UGURU3_DEBUG("synchronize timeout during initial busy "
  655. "wait, status: 0x%02x\n", x);
  656. return -EIO;
  657. }
  658. outb(0x20, data->addr + ABIT_UGURU3_DATA);
  659. x = abituguru3_wait_while_busy(data);
  660. if (x != ABIT_UGURU3_SUCCESS) {
  661. ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, "
  662. "status: 0x%02x\n", x);
  663. return -EIO;
  664. }
  665. outb(0x10, data->addr + ABIT_UGURU3_CMD);
  666. x = abituguru3_wait_while_busy(data);
  667. if (x != ABIT_UGURU3_SUCCESS) {
  668. ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, "
  669. "status: 0x%02x\n", x);
  670. return -EIO;
  671. }
  672. outb(0x00, data->addr + ABIT_UGURU3_CMD);
  673. x = abituguru3_wait_while_busy(data);
  674. if (x != ABIT_UGURU3_SUCCESS) {
  675. ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, "
  676. "status: 0x%02x\n", x);
  677. return -EIO;
  678. }
  679. x = abituguru3_wait_for_read(data);
  680. if (x != ABIT_UGURU3_SUCCESS) {
  681. ABIT_UGURU3_DEBUG("synchronize timeout waiting for read, "
  682. "status: 0x%02x\n", x);
  683. return -EIO;
  684. }
  685. while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) {
  686. timeout--;
  687. if (timeout == 0) {
  688. ABIT_UGURU3_DEBUG("synchronize timeout cmd does not "
  689. "hold 0xAC after synchronize, cmd: 0x%02x\n",
  690. x);
  691. return -EIO;
  692. }
  693. msleep(1);
  694. }
  695. return 0;
  696. }
  697. /*
  698. * Read count bytes from sensor sensor_addr in bank bank_addr and store the
  699. * result in buf
  700. */
  701. static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset,
  702. u8 count, u8 *buf)
  703. {
  704. int i, x;
  705. x = abituguru3_synchronize(data);
  706. if (x)
  707. return x;
  708. outb(0x1A, data->addr + ABIT_UGURU3_DATA);
  709. x = abituguru3_wait_while_busy(data);
  710. if (x != ABIT_UGURU3_SUCCESS) {
  711. ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
  712. "sending 0x1A, status: 0x%02x\n", (unsigned int)bank,
  713. (unsigned int)offset, x);
  714. return -EIO;
  715. }
  716. outb(bank, data->addr + ABIT_UGURU3_CMD);
  717. x = abituguru3_wait_while_busy(data);
  718. if (x != ABIT_UGURU3_SUCCESS) {
  719. ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
  720. "sending the bank, status: 0x%02x\n",
  721. (unsigned int)bank, (unsigned int)offset, x);
  722. return -EIO;
  723. }
  724. outb(offset, data->addr + ABIT_UGURU3_CMD);
  725. x = abituguru3_wait_while_busy(data);
  726. if (x != ABIT_UGURU3_SUCCESS) {
  727. ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
  728. "sending the offset, status: 0x%02x\n",
  729. (unsigned int)bank, (unsigned int)offset, x);
  730. return -EIO;
  731. }
  732. outb(count, data->addr + ABIT_UGURU3_CMD);
  733. x = abituguru3_wait_while_busy(data);
  734. if (x != ABIT_UGURU3_SUCCESS) {
  735. ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
  736. "sending the count, status: 0x%02x\n",
  737. (unsigned int)bank, (unsigned int)offset, x);
  738. return -EIO;
  739. }
  740. for (i = 0; i < count; i++) {
  741. x = abituguru3_wait_for_read(data);
  742. if (x != ABIT_UGURU3_SUCCESS) {
  743. ABIT_UGURU3_DEBUG("timeout reading byte %d from "
  744. "0x%02x:0x%02x, status: 0x%02x\n", i,
  745. (unsigned int)bank, (unsigned int)offset, x);
  746. break;
  747. }
  748. buf[i] = inb(data->addr + ABIT_UGURU3_CMD);
  749. }
  750. return i;
  751. }
  752. /*
  753. * Sensor settings are stored 1 byte per offset with the bytes
  754. * placed add consecutive offsets.
  755. */
  756. static int abituguru3_read_increment_offset(struct abituguru3_data *data,
  757. u8 bank, u8 offset, u8 count,
  758. u8 *buf, int offset_count)
  759. {
  760. int i, x;
  761. for (i = 0; i < offset_count; i++) {
  762. x = abituguru3_read(data, bank, offset + i, count,
  763. buf + i * count);
  764. if (x != count) {
  765. if (x < 0)
  766. return x;
  767. return i * count + x;
  768. }
  769. }
  770. return i * count;
  771. }
  772. /*
  773. * Following are the sysfs callback functions. These functions expect:
  774. * sensor_device_attribute_2->index: index into the data->sensors array
  775. * sensor_device_attribute_2->nr: register offset, bitmask or NA.
  776. */
  777. static struct abituguru3_data *abituguru3_update_device(struct device *dev);
  778. static ssize_t show_value(struct device *dev,
  779. struct device_attribute *devattr, char *buf)
  780. {
  781. int value;
  782. struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
  783. struct abituguru3_data *data = abituguru3_update_device(dev);
  784. const struct abituguru3_sensor_info *sensor;
  785. if (!data)
  786. return -EIO;
  787. sensor = &data->sensors[attr->index];
  788. /* are we reading a setting, or is this a normal read? */
  789. if (attr->nr)
  790. value = data->settings[sensor->port][attr->nr];
  791. else
  792. value = data->value[sensor->port];
  793. /* convert the value */
  794. value = (value * sensor->multiplier) / sensor->divisor +
  795. sensor->offset;
  796. /*
  797. * alternatively we could update the sensors settings struct for this,
  798. * but then its contents would differ from the windows sw ini files
  799. */
  800. if (sensor->type == ABIT_UGURU3_TEMP_SENSOR)
  801. value *= 1000;
  802. return sprintf(buf, "%d\n", value);
  803. }
  804. static ssize_t show_alarm(struct device *dev,
  805. struct device_attribute *devattr, char *buf)
  806. {
  807. int port;
  808. struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
  809. struct abituguru3_data *data = abituguru3_update_device(dev);
  810. if (!data)
  811. return -EIO;
  812. port = data->sensors[attr->index].port;
  813. /*
  814. * See if the alarm bit for this sensor is set and if a bitmask is
  815. * given in attr->nr also check if the alarm matches the type of alarm
  816. * we're looking for (for volt it can be either low or high). The type
  817. * is stored in a few readonly bits in the settings of the sensor.
  818. */
  819. if ((data->alarms[port / 8] & (0x01 << (port % 8))) &&
  820. (!attr->nr || (data->settings[port][0] & attr->nr)))
  821. return sprintf(buf, "1\n");
  822. else
  823. return sprintf(buf, "0\n");
  824. }
  825. static ssize_t show_mask(struct device *dev,
  826. struct device_attribute *devattr, char *buf)
  827. {
  828. struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
  829. struct abituguru3_data *data = dev_get_drvdata(dev);
  830. if (data->settings[data->sensors[attr->index].port][0] & attr->nr)
  831. return sprintf(buf, "1\n");
  832. else
  833. return sprintf(buf, "0\n");
  834. }
  835. static ssize_t show_label(struct device *dev,
  836. struct device_attribute *devattr, char *buf)
  837. {
  838. struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
  839. struct abituguru3_data *data = dev_get_drvdata(dev);
  840. return sprintf(buf, "%s\n", data->sensors[attr->index].name);
  841. }
  842. static ssize_t show_name(struct device *dev,
  843. struct device_attribute *devattr, char *buf)
  844. {
  845. return sprintf(buf, "%s\n", ABIT_UGURU3_NAME);
  846. }
  847. /* Sysfs attr templates, the real entries are generated automatically. */
  848. static const
  849. struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { {
  850. SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0),
  851. SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0),
  852. SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0),
  853. SENSOR_ATTR_2(in%d_min_alarm, 0444, show_alarm, NULL,
  854. ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0),
  855. SENSOR_ATTR_2(in%d_max_alarm, 0444, show_alarm, NULL,
  856. ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0),
  857. SENSOR_ATTR_2(in%d_beep, 0444, show_mask, NULL,
  858. ABIT_UGURU3_BEEP_ENABLE, 0),
  859. SENSOR_ATTR_2(in%d_shutdown, 0444, show_mask, NULL,
  860. ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
  861. SENSOR_ATTR_2(in%d_min_alarm_enable, 0444, show_mask, NULL,
  862. ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0),
  863. SENSOR_ATTR_2(in%d_max_alarm_enable, 0444, show_mask, NULL,
  864. ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0),
  865. SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0)
  866. }, {
  867. SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0),
  868. SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0),
  869. SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0),
  870. SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0),
  871. SENSOR_ATTR_2(temp%d_beep, 0444, show_mask, NULL,
  872. ABIT_UGURU3_BEEP_ENABLE, 0),
  873. SENSOR_ATTR_2(temp%d_shutdown, 0444, show_mask, NULL,
  874. ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
  875. SENSOR_ATTR_2(temp%d_alarm_enable, 0444, show_mask, NULL,
  876. ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0),
  877. SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0)
  878. }, {
  879. SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0),
  880. SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0),
  881. SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0),
  882. SENSOR_ATTR_2(fan%d_beep, 0444, show_mask, NULL,
  883. ABIT_UGURU3_BEEP_ENABLE, 0),
  884. SENSOR_ATTR_2(fan%d_shutdown, 0444, show_mask, NULL,
  885. ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
  886. SENSOR_ATTR_2(fan%d_alarm_enable, 0444, show_mask, NULL,
  887. ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0),
  888. SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0)
  889. } };
  890. static struct sensor_device_attribute_2 abituguru3_sysfs_attr[] = {
  891. SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0),
  892. };
  893. static int abituguru3_probe(struct platform_device *pdev)
  894. {
  895. const int no_sysfs_attr[3] = { 10, 8, 7 };
  896. int sensor_index[3] = { 0, 1, 1 };
  897. struct abituguru3_data *data;
  898. int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV;
  899. char *sysfs_filename;
  900. u8 buf[2];
  901. u16 id;
  902. data = devm_kzalloc(&pdev->dev, sizeof(struct abituguru3_data),
  903. GFP_KERNEL);
  904. if (!data)
  905. return -ENOMEM;
  906. data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
  907. mutex_init(&data->update_lock);
  908. platform_set_drvdata(pdev, data);
  909. /* Read the motherboard ID */
  910. i = abituguru3_read(data, ABIT_UGURU3_MISC_BANK, ABIT_UGURU3_BOARD_ID,
  911. 2, buf);
  912. if (i != 2)
  913. goto abituguru3_probe_error;
  914. /* Completely read the uGuru to see if one really is there */
  915. if (!abituguru3_update_device(&pdev->dev))
  916. goto abituguru3_probe_error;
  917. /* lookup the ID in our motherboard table */
  918. id = ((u16)buf[0] << 8) | (u16)buf[1];
  919. for (i = 0; abituguru3_motherboards[i].id; i++)
  920. if (abituguru3_motherboards[i].id == id)
  921. break;
  922. if (!abituguru3_motherboards[i].id) {
  923. pr_err("error unknown motherboard ID: %04X. %s\n",
  924. (unsigned int)id, report_this);
  925. goto abituguru3_probe_error;
  926. }
  927. data->sensors = abituguru3_motherboards[i].sensors;
  928. pr_info("found Abit uGuru3, motherboard ID: %04X\n", (unsigned int)id);
  929. /* Fill the sysfs attr array */
  930. sysfs_attr_i = 0;
  931. sysfs_filename = data->sysfs_names;
  932. sysfs_names_free = ABIT_UGURU3_SYSFS_NAMES_LENGTH;
  933. for (i = 0; data->sensors[i].name; i++) {
  934. /* Fail safe check, this should never happen! */
  935. if (i >= ABIT_UGURU3_MAX_NO_SENSORS) {
  936. pr_err("Fatal error motherboard has more sensors then ABIT_UGURU3_MAX_NO_SENSORS. %s %s\n",
  937. never_happen, report_this);
  938. res = -ENAMETOOLONG;
  939. goto abituguru3_probe_error;
  940. }
  941. type = data->sensors[i].type;
  942. for (j = 0; j < no_sysfs_attr[type]; j++) {
  943. used = snprintf(sysfs_filename, sysfs_names_free,
  944. abituguru3_sysfs_templ[type][j].dev_attr.attr.
  945. name, sensor_index[type]) + 1;
  946. data->sysfs_attr[sysfs_attr_i] =
  947. abituguru3_sysfs_templ[type][j];
  948. data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name =
  949. sysfs_filename;
  950. data->sysfs_attr[sysfs_attr_i].index = i;
  951. sysfs_filename += used;
  952. sysfs_names_free -= used;
  953. sysfs_attr_i++;
  954. }
  955. sensor_index[type]++;
  956. }
  957. /* Fail safe check, this should never happen! */
  958. if (sysfs_names_free < 0) {
  959. pr_err("Fatal error ran out of space for sysfs attr names. %s %s\n",
  960. never_happen, report_this);
  961. res = -ENAMETOOLONG;
  962. goto abituguru3_probe_error;
  963. }
  964. /* Register sysfs hooks */
  965. for (i = 0; i < sysfs_attr_i; i++)
  966. if (device_create_file(&pdev->dev,
  967. &data->sysfs_attr[i].dev_attr))
  968. goto abituguru3_probe_error;
  969. for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
  970. if (device_create_file(&pdev->dev,
  971. &abituguru3_sysfs_attr[i].dev_attr))
  972. goto abituguru3_probe_error;
  973. data->hwmon_dev = hwmon_device_register(&pdev->dev);
  974. if (IS_ERR(data->hwmon_dev)) {
  975. res = PTR_ERR(data->hwmon_dev);
  976. goto abituguru3_probe_error;
  977. }
  978. return 0; /* success */
  979. abituguru3_probe_error:
  980. for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
  981. device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
  982. for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
  983. device_remove_file(&pdev->dev,
  984. &abituguru3_sysfs_attr[i].dev_attr);
  985. return res;
  986. }
  987. static int abituguru3_remove(struct platform_device *pdev)
  988. {
  989. int i;
  990. struct abituguru3_data *data = platform_get_drvdata(pdev);
  991. hwmon_device_unregister(data->hwmon_dev);
  992. for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
  993. device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
  994. for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
  995. device_remove_file(&pdev->dev,
  996. &abituguru3_sysfs_attr[i].dev_attr);
  997. return 0;
  998. }
  999. static struct abituguru3_data *abituguru3_update_device(struct device *dev)
  1000. {
  1001. int i;
  1002. struct abituguru3_data *data = dev_get_drvdata(dev);
  1003. mutex_lock(&data->update_lock);
  1004. if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
  1005. /* Clear data->valid while updating */
  1006. data->valid = 0;
  1007. /* Read alarms */
  1008. if (abituguru3_read_increment_offset(data,
  1009. ABIT_UGURU3_SETTINGS_BANK,
  1010. ABIT_UGURU3_ALARMS_START,
  1011. 1, data->alarms, 48/8) != (48/8))
  1012. goto LEAVE_UPDATE;
  1013. /* Read in and temp sensors (3 byte settings / sensor) */
  1014. for (i = 0; i < 32; i++) {
  1015. if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK,
  1016. ABIT_UGURU3_VALUES_START + i,
  1017. 1, &data->value[i]) != 1)
  1018. goto LEAVE_UPDATE;
  1019. if (abituguru3_read_increment_offset(data,
  1020. ABIT_UGURU3_SETTINGS_BANK,
  1021. ABIT_UGURU3_SETTINGS_START + i * 3,
  1022. 1,
  1023. data->settings[i], 3) != 3)
  1024. goto LEAVE_UPDATE;
  1025. }
  1026. /* Read temp sensors (2 byte settings / sensor) */
  1027. for (i = 0; i < 16; i++) {
  1028. if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK,
  1029. ABIT_UGURU3_VALUES_START + 32 + i,
  1030. 1, &data->value[32 + i]) != 1)
  1031. goto LEAVE_UPDATE;
  1032. if (abituguru3_read_increment_offset(data,
  1033. ABIT_UGURU3_SETTINGS_BANK,
  1034. ABIT_UGURU3_SETTINGS_START + 32 * 3 +
  1035. i * 2, 1,
  1036. data->settings[32 + i], 2) != 2)
  1037. goto LEAVE_UPDATE;
  1038. }
  1039. data->last_updated = jiffies;
  1040. data->valid = 1;
  1041. }
  1042. LEAVE_UPDATE:
  1043. mutex_unlock(&data->update_lock);
  1044. if (data->valid)
  1045. return data;
  1046. else
  1047. return NULL;
  1048. }
  1049. #ifdef CONFIG_PM_SLEEP
  1050. static int abituguru3_suspend(struct device *dev)
  1051. {
  1052. struct abituguru3_data *data = dev_get_drvdata(dev);
  1053. /*
  1054. * make sure all communications with the uguru3 are done and no new
  1055. * ones are started
  1056. */
  1057. mutex_lock(&data->update_lock);
  1058. return 0;
  1059. }
  1060. static int abituguru3_resume(struct device *dev)
  1061. {
  1062. struct abituguru3_data *data = dev_get_drvdata(dev);
  1063. mutex_unlock(&data->update_lock);
  1064. return 0;
  1065. }
  1066. static SIMPLE_DEV_PM_OPS(abituguru3_pm, abituguru3_suspend, abituguru3_resume);
  1067. #define ABIT_UGURU3_PM (&abituguru3_pm)
  1068. #else
  1069. #define ABIT_UGURU3_PM NULL
  1070. #endif /* CONFIG_PM */
  1071. static struct platform_driver abituguru3_driver = {
  1072. .driver = {
  1073. .name = ABIT_UGURU3_NAME,
  1074. .pm = ABIT_UGURU3_PM
  1075. },
  1076. .probe = abituguru3_probe,
  1077. .remove = abituguru3_remove,
  1078. };
  1079. static int __init abituguru3_dmi_detect(void)
  1080. {
  1081. const char *board_vendor, *board_name;
  1082. int i, err = (force) ? 1 : -ENODEV;
  1083. const char *const *dmi_name;
  1084. size_t sublen;
  1085. board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
  1086. if (!board_vendor || strcmp(board_vendor, "http://www.abit.com.tw/"))
  1087. return err;
  1088. board_name = dmi_get_system_info(DMI_BOARD_NAME);
  1089. if (!board_name)
  1090. return err;
  1091. /*
  1092. * At the moment, we don't care about the part of the vendor
  1093. * DMI string contained in brackets. Truncate the string at
  1094. * the first occurrence of a bracket. Trim any trailing space
  1095. * from the substring.
  1096. */
  1097. sublen = strcspn(board_name, "(");
  1098. while (sublen > 0 && board_name[sublen - 1] == ' ')
  1099. sublen--;
  1100. for (i = 0; abituguru3_motherboards[i].id; i++) {
  1101. dmi_name = abituguru3_motherboards[i].dmi_name;
  1102. for ( ; *dmi_name; dmi_name++) {
  1103. if (strlen(*dmi_name) != sublen)
  1104. continue;
  1105. if (!strncasecmp(board_name, *dmi_name, sublen))
  1106. return 0;
  1107. }
  1108. }
  1109. /* No match found */
  1110. return 1;
  1111. }
  1112. /*
  1113. * FIXME: Manual detection should die eventually; we need to collect stable
  1114. * DMI model names first before we can rely entirely on CONFIG_DMI.
  1115. */
  1116. static int __init abituguru3_detect(void)
  1117. {
  1118. /*
  1119. * See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or
  1120. * 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05
  1121. * or 0x55 at CMD instead, why is unknown.
  1122. */
  1123. u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA);
  1124. u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD);
  1125. if (((data_val == 0x00) || (data_val == 0x08)) &&
  1126. ((cmd_val == 0xAC) || (cmd_val == 0x05) ||
  1127. (cmd_val == 0x55)))
  1128. return 0;
  1129. ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = "
  1130. "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val);
  1131. if (force) {
  1132. pr_info("Assuming Abit uGuru3 is present because of \"force\" parameter\n");
  1133. return 0;
  1134. }
  1135. /* No uGuru3 found */
  1136. return -ENODEV;
  1137. }
  1138. static struct platform_device *abituguru3_pdev;
  1139. static int __init abituguru3_init(void)
  1140. {
  1141. struct resource res = { .flags = IORESOURCE_IO };
  1142. int err;
  1143. /* Attempt DMI detection first */
  1144. err = abituguru3_dmi_detect();
  1145. if (err < 0)
  1146. return err;
  1147. /*
  1148. * Fall back to manual detection if there was no exact
  1149. * board name match, or force was specified.
  1150. */
  1151. if (err > 0) {
  1152. err = abituguru3_detect();
  1153. if (err)
  1154. return err;
  1155. pr_warn("this motherboard was not detected using DMI. "
  1156. "Please send the output of \"dmidecode\" to the abituguru3 maintainer (see MAINTAINERS)\n");
  1157. }
  1158. err = platform_driver_register(&abituguru3_driver);
  1159. if (err)
  1160. goto exit;
  1161. abituguru3_pdev = platform_device_alloc(ABIT_UGURU3_NAME,
  1162. ABIT_UGURU3_BASE);
  1163. if (!abituguru3_pdev) {
  1164. pr_err("Device allocation failed\n");
  1165. err = -ENOMEM;
  1166. goto exit_driver_unregister;
  1167. }
  1168. res.start = ABIT_UGURU3_BASE;
  1169. res.end = ABIT_UGURU3_BASE + ABIT_UGURU3_REGION_LENGTH - 1;
  1170. res.name = ABIT_UGURU3_NAME;
  1171. err = platform_device_add_resources(abituguru3_pdev, &res, 1);
  1172. if (err) {
  1173. pr_err("Device resource addition failed (%d)\n", err);
  1174. goto exit_device_put;
  1175. }
  1176. err = platform_device_add(abituguru3_pdev);
  1177. if (err) {
  1178. pr_err("Device addition failed (%d)\n", err);
  1179. goto exit_device_put;
  1180. }
  1181. return 0;
  1182. exit_device_put:
  1183. platform_device_put(abituguru3_pdev);
  1184. exit_driver_unregister:
  1185. platform_driver_unregister(&abituguru3_driver);
  1186. exit:
  1187. return err;
  1188. }
  1189. static void __exit abituguru3_exit(void)
  1190. {
  1191. platform_device_unregister(abituguru3_pdev);
  1192. platform_driver_unregister(&abituguru3_driver);
  1193. }
  1194. MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
  1195. MODULE_DESCRIPTION("Abit uGuru3 Sensor device");
  1196. MODULE_LICENSE("GPL");
  1197. module_init(abituguru3_init);
  1198. module_exit(abituguru3_exit);