ipu-prv.h 8.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
  4. * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
  5. */
  6. #ifndef __IPU_PRV_H__
  7. #define __IPU_PRV_H__
  8. struct ipu_soc;
  9. #include <linux/types.h>
  10. #include <linux/device.h>
  11. #include <linux/clk.h>
  12. #include <linux/platform_device.h>
  13. #include <video/imx-ipu-v3.h>
  14. #define IPU_MCU_T_DEFAULT 8
  15. #define IPU_CM_IDMAC_REG_OFS 0x00008000
  16. #define IPU_CM_IC_REG_OFS 0x00020000
  17. #define IPU_CM_IRT_REG_OFS 0x00028000
  18. #define IPU_CM_CSI0_REG_OFS 0x00030000
  19. #define IPU_CM_CSI1_REG_OFS 0x00038000
  20. #define IPU_CM_SMFC_REG_OFS 0x00050000
  21. #define IPU_CM_DC_REG_OFS 0x00058000
  22. #define IPU_CM_DMFC_REG_OFS 0x00060000
  23. /* Register addresses */
  24. /* IPU Common registers */
  25. #define IPU_CM_REG(offset) (offset)
  26. #define IPU_CONF IPU_CM_REG(0)
  27. #define IPU_SRM_PRI1 IPU_CM_REG(0x00a0)
  28. #define IPU_SRM_PRI2 IPU_CM_REG(0x00a4)
  29. #define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00a8)
  30. #define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00ac)
  31. #define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00b0)
  32. #define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00b4)
  33. #define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00b8)
  34. #define IPU_SKIP IPU_CM_REG(0x00bc)
  35. #define IPU_DISP_ALT_CONF IPU_CM_REG(0x00c0)
  36. #define IPU_DISP_GEN IPU_CM_REG(0x00c4)
  37. #define IPU_DISP_ALT1 IPU_CM_REG(0x00c8)
  38. #define IPU_DISP_ALT2 IPU_CM_REG(0x00cc)
  39. #define IPU_DISP_ALT3 IPU_CM_REG(0x00d0)
  40. #define IPU_DISP_ALT4 IPU_CM_REG(0x00d4)
  41. #define IPU_SNOOP IPU_CM_REG(0x00d8)
  42. #define IPU_MEM_RST IPU_CM_REG(0x00dc)
  43. #define IPU_PM IPU_CM_REG(0x00e0)
  44. #define IPU_GPR IPU_CM_REG(0x00e4)
  45. #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
  46. #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
  47. #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32))
  48. #define IPU_ALT_CUR_BUF0 IPU_CM_REG(0x0244)
  49. #define IPU_ALT_CUR_BUF1 IPU_CM_REG(0x0248)
  50. #define IPU_SRM_STAT IPU_CM_REG(0x024C)
  51. #define IPU_PROC_TASK_STAT IPU_CM_REG(0x0250)
  52. #define IPU_DISP_TASK_STAT IPU_CM_REG(0x0254)
  53. #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
  54. #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
  55. #define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
  56. #define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
  57. #define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
  58. #define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
  59. #define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
  60. /* SRM_PRI2 */
  61. #define DP_S_SRM_MODE_MASK (0x3 << 3)
  62. #define DP_S_SRM_MODE_NOW (0x3 << 3)
  63. #define DP_S_SRM_MODE_NEXT_FRAME (0x1 << 3)
  64. /* FS_PROC_FLOW1 */
  65. #define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0)
  66. #define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0)
  67. #define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8)
  68. #define FS_PRPVF_ROT_SRC_SEL_VF (0x8 << 8)
  69. #define FS_PP_SRC_SEL_MASK (0xf << 12)
  70. #define FS_PP_ROT_SRC_SEL_MASK (0xf << 16)
  71. #define FS_PP_ROT_SRC_SEL_PP (0x5 << 16)
  72. #define FS_VDI1_SRC_SEL_MASK (0x3 << 20)
  73. #define FS_VDI3_SRC_SEL_MASK (0x3 << 20)
  74. #define FS_PRP_SRC_SEL_MASK (0xf << 24)
  75. #define FS_VDI_SRC_SEL_MASK (0x3 << 28)
  76. #define FS_VDI_SRC_SEL_CSI_DIRECT (0x1 << 28)
  77. #define FS_VDI_SRC_SEL_VDOA (0x2 << 28)
  78. /* FS_PROC_FLOW2 */
  79. #define FS_PRP_ENC_DEST_SEL_MASK (0xf << 0)
  80. #define FS_PRP_ENC_DEST_SEL_IRT_ENC (0x1 << 0)
  81. #define FS_PRPVF_DEST_SEL_MASK (0xf << 4)
  82. #define FS_PRPVF_DEST_SEL_IRT_VF (0x1 << 4)
  83. #define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8)
  84. #define FS_PP_DEST_SEL_MASK (0xf << 12)
  85. #define FS_PP_DEST_SEL_IRT_PP (0x3 << 12)
  86. #define FS_PP_ROT_DEST_SEL_MASK (0xf << 16)
  87. #define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20)
  88. #define FS_PRP_DEST_SEL_MASK (0xf << 24)
  89. #define IPU_DI0_COUNTER_RELEASE (1 << 24)
  90. #define IPU_DI1_COUNTER_RELEASE (1 << 25)
  91. #define IPU_IDMAC_REG(offset) (offset)
  92. #define IDMAC_CONF IPU_IDMAC_REG(0x0000)
  93. #define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
  94. #define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000c)
  95. #define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010)
  96. #define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
  97. #define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
  98. #define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG(0x0024)
  99. #define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG(0x0028)
  100. #define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG(0x002c)
  101. #define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG(0x0030)
  102. #define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG(0x0034)
  103. #define IDMAC_BAND_EN(ch) IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
  104. #define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
  105. #define IPU_NUM_IRQS (32 * 15)
  106. enum ipu_modules {
  107. IPU_CONF_CSI0_EN = (1 << 0),
  108. IPU_CONF_CSI1_EN = (1 << 1),
  109. IPU_CONF_IC_EN = (1 << 2),
  110. IPU_CONF_ROT_EN = (1 << 3),
  111. IPU_CONF_ISP_EN = (1 << 4),
  112. IPU_CONF_DP_EN = (1 << 5),
  113. IPU_CONF_DI0_EN = (1 << 6),
  114. IPU_CONF_DI1_EN = (1 << 7),
  115. IPU_CONF_SMFC_EN = (1 << 8),
  116. IPU_CONF_DC_EN = (1 << 9),
  117. IPU_CONF_DMFC_EN = (1 << 10),
  118. IPU_CONF_VDI_EN = (1 << 12),
  119. IPU_CONF_IDMAC_DIS = (1 << 22),
  120. IPU_CONF_IC_DMFC_SEL = (1 << 25),
  121. IPU_CONF_IC_DMFC_SYNC = (1 << 26),
  122. IPU_CONF_VDI_DMFC_SYNC = (1 << 27),
  123. IPU_CONF_CSI0_DATA_SOURCE = (1 << 28),
  124. IPU_CONF_CSI1_DATA_SOURCE = (1 << 29),
  125. IPU_CONF_IC_INPUT = (1 << 30),
  126. IPU_CONF_CSI_SEL = (1 << 31),
  127. };
  128. struct ipuv3_channel {
  129. unsigned int num;
  130. struct ipu_soc *ipu;
  131. struct list_head list;
  132. };
  133. struct ipu_cpmem;
  134. struct ipu_csi;
  135. struct ipu_dc_priv;
  136. struct ipu_dmfc_priv;
  137. struct ipu_di;
  138. struct ipu_ic_priv;
  139. struct ipu_vdi;
  140. struct ipu_image_convert_priv;
  141. struct ipu_smfc_priv;
  142. struct ipu_pre;
  143. struct ipu_prg;
  144. struct ipu_devtype;
  145. struct ipu_soc {
  146. struct device *dev;
  147. const struct ipu_devtype *devtype;
  148. enum ipuv3_type ipu_type;
  149. spinlock_t lock;
  150. struct mutex channel_lock;
  151. struct list_head channels;
  152. void __iomem *cm_reg;
  153. void __iomem *idmac_reg;
  154. int id;
  155. int usecount;
  156. struct clk *clk;
  157. int irq_sync;
  158. int irq_err;
  159. struct irq_domain *domain;
  160. struct ipu_cpmem *cpmem_priv;
  161. struct ipu_dc_priv *dc_priv;
  162. struct ipu_dp_priv *dp_priv;
  163. struct ipu_dmfc_priv *dmfc_priv;
  164. struct ipu_di *di_priv[2];
  165. struct ipu_csi *csi_priv[2];
  166. struct ipu_ic_priv *ic_priv;
  167. struct ipu_vdi *vdi_priv;
  168. struct ipu_image_convert_priv *image_convert_priv;
  169. struct ipu_smfc_priv *smfc_priv;
  170. struct ipu_prg *prg_priv;
  171. };
  172. static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
  173. {
  174. return readl(ipu->idmac_reg + offset);
  175. }
  176. static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
  177. unsigned offset)
  178. {
  179. writel(value, ipu->idmac_reg + offset);
  180. }
  181. void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
  182. int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
  183. int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
  184. bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
  185. int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
  186. unsigned long base, u32 module, struct clk *clk_ipu);
  187. void ipu_csi_exit(struct ipu_soc *ipu, int id);
  188. int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
  189. unsigned long base, unsigned long tpmem_base);
  190. void ipu_ic_exit(struct ipu_soc *ipu);
  191. int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
  192. unsigned long base, u32 module);
  193. void ipu_vdi_exit(struct ipu_soc *ipu);
  194. int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
  195. void ipu_image_convert_exit(struct ipu_soc *ipu);
  196. int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
  197. unsigned long base, u32 module, struct clk *ipu_clk);
  198. void ipu_di_exit(struct ipu_soc *ipu, int id);
  199. int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
  200. struct clk *ipu_clk);
  201. void ipu_dmfc_exit(struct ipu_soc *ipu);
  202. int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
  203. void ipu_dp_exit(struct ipu_soc *ipu);
  204. int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
  205. unsigned long template_base);
  206. void ipu_dc_exit(struct ipu_soc *ipu);
  207. int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
  208. void ipu_cpmem_exit(struct ipu_soc *ipu);
  209. int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
  210. void ipu_smfc_exit(struct ipu_soc *ipu);
  211. struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name,
  212. int index);
  213. int ipu_pre_get_available_count(void);
  214. int ipu_pre_get(struct ipu_pre *pre);
  215. void ipu_pre_put(struct ipu_pre *pre);
  216. u32 ipu_pre_get_baddr(struct ipu_pre *pre);
  217. void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
  218. unsigned int height, unsigned int stride, u32 format,
  219. uint64_t modifier, unsigned int bufaddr);
  220. void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr);
  221. bool ipu_pre_update_pending(struct ipu_pre *pre);
  222. struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name,
  223. int ipu_id);
  224. extern struct platform_driver ipu_pre_drv;
  225. extern struct platform_driver ipu_prg_drv;
  226. #endif /* __IPU_PRV_H__ */