ipu-prg.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2017 Lucas Stach, Pengutronix
  4. */
  5. #include <drm/drm_fourcc.h>
  6. #include <linux/clk.h>
  7. #include <linux/err.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/regmap.h>
  16. #include <video/imx-ipu-v3.h>
  17. #include "ipu-prv.h"
  18. #define IPU_PRG_CTL 0x00
  19. #define IPU_PRG_CTL_BYPASS(i) (1 << (0 + i))
  20. #define IPU_PRG_CTL_SOFT_ARID_MASK 0x3
  21. #define IPU_PRG_CTL_SOFT_ARID_SHIFT(i) (8 + i * 2)
  22. #define IPU_PRG_CTL_SOFT_ARID(i, v) ((v & 0x3) << (8 + 2 * i))
  23. #define IPU_PRG_CTL_SO(i) (1 << (16 + i))
  24. #define IPU_PRG_CTL_VFLIP(i) (1 << (19 + i))
  25. #define IPU_PRG_CTL_BLOCK_MODE(i) (1 << (22 + i))
  26. #define IPU_PRG_CTL_CNT_LOAD_EN(i) (1 << (25 + i))
  27. #define IPU_PRG_CTL_SOFTRST (1 << 30)
  28. #define IPU_PRG_CTL_SHADOW_EN (1 << 31)
  29. #define IPU_PRG_STATUS 0x04
  30. #define IPU_PRG_STATUS_BUFFER0_READY(i) (1 << (0 + i * 2))
  31. #define IPU_PRG_STATUS_BUFFER1_READY(i) (1 << (1 + i * 2))
  32. #define IPU_PRG_QOS 0x08
  33. #define IPU_PRG_QOS_ARID_MASK 0xf
  34. #define IPU_PRG_QOS_ARID_SHIFT(i) (0 + i * 4)
  35. #define IPU_PRG_REG_UPDATE 0x0c
  36. #define IPU_PRG_REG_UPDATE_REG_UPDATE (1 << 0)
  37. #define IPU_PRG_STRIDE(i) (0x10 + i * 0x4)
  38. #define IPU_PRG_STRIDE_STRIDE_MASK 0x3fff
  39. #define IPU_PRG_CROP_LINE 0x1c
  40. #define IPU_PRG_THD 0x20
  41. #define IPU_PRG_BADDR(i) (0x24 + i * 0x4)
  42. #define IPU_PRG_OFFSET(i) (0x30 + i * 0x4)
  43. #define IPU_PRG_ILO(i) (0x3c + i * 0x4)
  44. #define IPU_PRG_HEIGHT(i) (0x48 + i * 0x4)
  45. #define IPU_PRG_HEIGHT_PRE_HEIGHT_MASK 0xfff
  46. #define IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT 0
  47. #define IPU_PRG_HEIGHT_IPU_HEIGHT_MASK 0xfff
  48. #define IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT 16
  49. struct ipu_prg_channel {
  50. bool enabled;
  51. int used_pre;
  52. };
  53. struct ipu_prg {
  54. struct list_head list;
  55. struct device *dev;
  56. int id;
  57. void __iomem *regs;
  58. struct clk *clk_ipg, *clk_axi;
  59. struct regmap *iomuxc_gpr;
  60. struct ipu_pre *pres[3];
  61. struct ipu_prg_channel chan[3];
  62. };
  63. static DEFINE_MUTEX(ipu_prg_list_mutex);
  64. static LIST_HEAD(ipu_prg_list);
  65. struct ipu_prg *
  66. ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
  67. {
  68. struct device_node *prg_node = of_parse_phandle(dev->of_node,
  69. name, 0);
  70. struct ipu_prg *prg;
  71. mutex_lock(&ipu_prg_list_mutex);
  72. list_for_each_entry(prg, &ipu_prg_list, list) {
  73. if (prg_node == prg->dev->of_node) {
  74. mutex_unlock(&ipu_prg_list_mutex);
  75. device_link_add(dev, prg->dev,
  76. DL_FLAG_AUTOREMOVE_CONSUMER);
  77. prg->id = ipu_id;
  78. of_node_put(prg_node);
  79. return prg;
  80. }
  81. }
  82. mutex_unlock(&ipu_prg_list_mutex);
  83. of_node_put(prg_node);
  84. return NULL;
  85. }
  86. int ipu_prg_max_active_channels(void)
  87. {
  88. return ipu_pre_get_available_count();
  89. }
  90. EXPORT_SYMBOL_GPL(ipu_prg_max_active_channels);
  91. bool ipu_prg_present(struct ipu_soc *ipu)
  92. {
  93. if (ipu->prg_priv)
  94. return true;
  95. return false;
  96. }
  97. EXPORT_SYMBOL_GPL(ipu_prg_present);
  98. bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
  99. uint64_t modifier)
  100. {
  101. const struct drm_format_info *info = drm_format_info(format);
  102. if (info->num_planes != 1)
  103. return false;
  104. switch (modifier) {
  105. case DRM_FORMAT_MOD_LINEAR:
  106. case DRM_FORMAT_MOD_VIVANTE_TILED:
  107. case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
  108. return true;
  109. default:
  110. return false;
  111. }
  112. }
  113. EXPORT_SYMBOL_GPL(ipu_prg_format_supported);
  114. int ipu_prg_enable(struct ipu_soc *ipu)
  115. {
  116. struct ipu_prg *prg = ipu->prg_priv;
  117. if (!prg)
  118. return 0;
  119. return pm_runtime_get_sync(prg->dev);
  120. }
  121. EXPORT_SYMBOL_GPL(ipu_prg_enable);
  122. void ipu_prg_disable(struct ipu_soc *ipu)
  123. {
  124. struct ipu_prg *prg = ipu->prg_priv;
  125. if (!prg)
  126. return;
  127. pm_runtime_put(prg->dev);
  128. }
  129. EXPORT_SYMBOL_GPL(ipu_prg_disable);
  130. /*
  131. * The channel configuartion functions below are not thread safe, as they
  132. * must be only called from the atomic commit path in the DRM driver, which
  133. * is properly serialized.
  134. */
  135. static int ipu_prg_ipu_to_prg_chan(int ipu_chan)
  136. {
  137. /*
  138. * This isn't clearly documented in the RM, but IPU to PRG channel
  139. * assignment is fixed, as only with this mapping the control signals
  140. * match up.
  141. */
  142. switch (ipu_chan) {
  143. case IPUV3_CHANNEL_MEM_BG_SYNC:
  144. return 0;
  145. case IPUV3_CHANNEL_MEM_FG_SYNC:
  146. return 1;
  147. case IPUV3_CHANNEL_MEM_DC_SYNC:
  148. return 2;
  149. default:
  150. return -EINVAL;
  151. }
  152. }
  153. static int ipu_prg_get_pre(struct ipu_prg *prg, int prg_chan)
  154. {
  155. int i, ret;
  156. /* channel 0 is special as it is hardwired to one of the PREs */
  157. if (prg_chan == 0) {
  158. ret = ipu_pre_get(prg->pres[0]);
  159. if (ret)
  160. goto fail;
  161. prg->chan[prg_chan].used_pre = 0;
  162. return 0;
  163. }
  164. for (i = 1; i < 3; i++) {
  165. ret = ipu_pre_get(prg->pres[i]);
  166. if (!ret) {
  167. u32 val, mux;
  168. int shift;
  169. prg->chan[prg_chan].used_pre = i;
  170. /* configure the PRE to PRG channel mux */
  171. shift = (i == 1) ? 12 : 14;
  172. mux = (prg->id << 1) | (prg_chan - 1);
  173. regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
  174. 0x3 << shift, mux << shift);
  175. /* check other mux, must not point to same channel */
  176. shift = (i == 1) ? 14 : 12;
  177. regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val);
  178. if (((val >> shift) & 0x3) == mux) {
  179. regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
  180. 0x3 << shift,
  181. (mux ^ 0x1) << shift);
  182. }
  183. return 0;
  184. }
  185. }
  186. fail:
  187. dev_err(prg->dev, "could not get PRE for PRG chan %d", prg_chan);
  188. return ret;
  189. }
  190. static void ipu_prg_put_pre(struct ipu_prg *prg, int prg_chan)
  191. {
  192. struct ipu_prg_channel *chan = &prg->chan[prg_chan];
  193. ipu_pre_put(prg->pres[chan->used_pre]);
  194. chan->used_pre = -1;
  195. }
  196. void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
  197. {
  198. int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
  199. struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
  200. struct ipu_prg_channel *chan;
  201. u32 val;
  202. if (prg_chan < 0)
  203. return;
  204. chan = &prg->chan[prg_chan];
  205. if (!chan->enabled)
  206. return;
  207. pm_runtime_get_sync(prg->dev);
  208. val = readl(prg->regs + IPU_PRG_CTL);
  209. val |= IPU_PRG_CTL_BYPASS(prg_chan);
  210. writel(val, prg->regs + IPU_PRG_CTL);
  211. val = IPU_PRG_REG_UPDATE_REG_UPDATE;
  212. writel(val, prg->regs + IPU_PRG_REG_UPDATE);
  213. pm_runtime_put(prg->dev);
  214. ipu_prg_put_pre(prg, prg_chan);
  215. chan->enabled = false;
  216. }
  217. EXPORT_SYMBOL_GPL(ipu_prg_channel_disable);
  218. int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
  219. unsigned int axi_id, unsigned int width,
  220. unsigned int height, unsigned int stride,
  221. u32 format, uint64_t modifier, unsigned long *eba)
  222. {
  223. int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
  224. struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
  225. struct ipu_prg_channel *chan;
  226. u32 val;
  227. int ret;
  228. if (prg_chan < 0)
  229. return prg_chan;
  230. chan = &prg->chan[prg_chan];
  231. if (chan->enabled) {
  232. ipu_pre_update(prg->pres[chan->used_pre], *eba);
  233. return 0;
  234. }
  235. ret = ipu_prg_get_pre(prg, prg_chan);
  236. if (ret)
  237. return ret;
  238. ipu_pre_configure(prg->pres[chan->used_pre],
  239. width, height, stride, format, modifier, *eba);
  240. pm_runtime_get_sync(prg->dev);
  241. val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK;
  242. writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
  243. val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) <<
  244. IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT) |
  245. ((height & IPU_PRG_HEIGHT_IPU_HEIGHT_MASK) <<
  246. IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT);
  247. writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
  248. val = ipu_pre_get_baddr(prg->pres[chan->used_pre]);
  249. *eba = val;
  250. writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
  251. val = readl(prg->regs + IPU_PRG_CTL);
  252. /* config AXI ID */
  253. val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
  254. IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
  255. val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id);
  256. /* enable channel */
  257. val &= ~IPU_PRG_CTL_BYPASS(prg_chan);
  258. writel(val, prg->regs + IPU_PRG_CTL);
  259. val = IPU_PRG_REG_UPDATE_REG_UPDATE;
  260. writel(val, prg->regs + IPU_PRG_REG_UPDATE);
  261. /* wait for both double buffers to be filled */
  262. readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
  263. (val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
  264. (val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
  265. 5, 1000);
  266. pm_runtime_put(prg->dev);
  267. chan->enabled = true;
  268. return 0;
  269. }
  270. EXPORT_SYMBOL_GPL(ipu_prg_channel_configure);
  271. bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan)
  272. {
  273. int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
  274. struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
  275. struct ipu_prg_channel *chan;
  276. if (prg_chan < 0)
  277. return false;
  278. chan = &prg->chan[prg_chan];
  279. WARN_ON(!chan->enabled);
  280. return ipu_pre_update_pending(prg->pres[chan->used_pre]);
  281. }
  282. EXPORT_SYMBOL_GPL(ipu_prg_channel_configure_pending);
  283. static int ipu_prg_probe(struct platform_device *pdev)
  284. {
  285. struct device *dev = &pdev->dev;
  286. struct resource *res;
  287. struct ipu_prg *prg;
  288. u32 val;
  289. int i, ret;
  290. prg = devm_kzalloc(dev, sizeof(*prg), GFP_KERNEL);
  291. if (!prg)
  292. return -ENOMEM;
  293. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  294. prg->regs = devm_ioremap_resource(&pdev->dev, res);
  295. if (IS_ERR(prg->regs))
  296. return PTR_ERR(prg->regs);
  297. prg->clk_ipg = devm_clk_get(dev, "ipg");
  298. if (IS_ERR(prg->clk_ipg))
  299. return PTR_ERR(prg->clk_ipg);
  300. prg->clk_axi = devm_clk_get(dev, "axi");
  301. if (IS_ERR(prg->clk_axi))
  302. return PTR_ERR(prg->clk_axi);
  303. prg->iomuxc_gpr =
  304. syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
  305. if (IS_ERR(prg->iomuxc_gpr))
  306. return PTR_ERR(prg->iomuxc_gpr);
  307. for (i = 0; i < 3; i++) {
  308. prg->pres[i] = ipu_pre_lookup_by_phandle(dev, "fsl,pres", i);
  309. if (!prg->pres[i])
  310. return -EPROBE_DEFER;
  311. }
  312. ret = clk_prepare_enable(prg->clk_ipg);
  313. if (ret)
  314. return ret;
  315. ret = clk_prepare_enable(prg->clk_axi);
  316. if (ret) {
  317. clk_disable_unprepare(prg->clk_ipg);
  318. return ret;
  319. }
  320. /* init to free running mode */
  321. val = readl(prg->regs + IPU_PRG_CTL);
  322. val |= IPU_PRG_CTL_SHADOW_EN;
  323. writel(val, prg->regs + IPU_PRG_CTL);
  324. /* disable address threshold */
  325. writel(0xffffffff, prg->regs + IPU_PRG_THD);
  326. pm_runtime_set_active(dev);
  327. pm_runtime_enable(dev);
  328. prg->dev = dev;
  329. platform_set_drvdata(pdev, prg);
  330. mutex_lock(&ipu_prg_list_mutex);
  331. list_add(&prg->list, &ipu_prg_list);
  332. mutex_unlock(&ipu_prg_list_mutex);
  333. return 0;
  334. }
  335. static int ipu_prg_remove(struct platform_device *pdev)
  336. {
  337. struct ipu_prg *prg = platform_get_drvdata(pdev);
  338. mutex_lock(&ipu_prg_list_mutex);
  339. list_del(&prg->list);
  340. mutex_unlock(&ipu_prg_list_mutex);
  341. return 0;
  342. }
  343. #ifdef CONFIG_PM
  344. static int prg_suspend(struct device *dev)
  345. {
  346. struct ipu_prg *prg = dev_get_drvdata(dev);
  347. clk_disable_unprepare(prg->clk_axi);
  348. clk_disable_unprepare(prg->clk_ipg);
  349. return 0;
  350. }
  351. static int prg_resume(struct device *dev)
  352. {
  353. struct ipu_prg *prg = dev_get_drvdata(dev);
  354. int ret;
  355. ret = clk_prepare_enable(prg->clk_ipg);
  356. if (ret)
  357. return ret;
  358. ret = clk_prepare_enable(prg->clk_axi);
  359. if (ret) {
  360. clk_disable_unprepare(prg->clk_ipg);
  361. return ret;
  362. }
  363. return 0;
  364. }
  365. #endif
  366. static const struct dev_pm_ops prg_pm_ops = {
  367. SET_RUNTIME_PM_OPS(prg_suspend, prg_resume, NULL)
  368. };
  369. static const struct of_device_id ipu_prg_dt_ids[] = {
  370. { .compatible = "fsl,imx6qp-prg", },
  371. { /* sentinel */ },
  372. };
  373. struct platform_driver ipu_prg_drv = {
  374. .probe = ipu_prg_probe,
  375. .remove = ipu_prg_remove,
  376. .driver = {
  377. .name = "imx-ipu-prg",
  378. .pm = &prg_pm_ops,
  379. .of_match_table = ipu_prg_dt_ids,
  380. },
  381. };