ipu-pre.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 Lucas Stach, Pengutronix
  4. */
  5. #include <drm/drm_fourcc.h>
  6. #include <linux/clk.h>
  7. #include <linux/err.h>
  8. #include <linux/genalloc.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <video/imx-ipu-v3.h>
  13. #include "ipu-prv.h"
  14. #define IPU_PRE_MAX_WIDTH 2048
  15. #define IPU_PRE_NUM_SCANLINES 8
  16. #define IPU_PRE_CTRL 0x000
  17. #define IPU_PRE_CTRL_SET 0x004
  18. #define IPU_PRE_CTRL_ENABLE (1 << 0)
  19. #define IPU_PRE_CTRL_BLOCK_EN (1 << 1)
  20. #define IPU_PRE_CTRL_BLOCK_16 (1 << 2)
  21. #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4)
  22. #define IPU_PRE_CTRL_VFLIP (1 << 5)
  23. #define IPU_PRE_CTRL_SO (1 << 6)
  24. #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7)
  25. #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8)
  26. #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9)
  27. #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11)
  28. #define IPU_PRE_CTRL_EN_REPEAT (1 << 28)
  29. #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29)
  30. #define IPU_PRE_CTRL_CLKGATE (1 << 30)
  31. #define IPU_PRE_CTRL_SFTRST (1 << 31)
  32. #define IPU_PRE_CUR_BUF 0x030
  33. #define IPU_PRE_NEXT_BUF 0x040
  34. #define IPU_PRE_TPR_CTRL 0x070
  35. #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0)
  36. #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff
  37. #define IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT (1 << 0)
  38. #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF (1 << 4)
  39. #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF (1 << 5)
  40. #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED (1 << 6)
  41. #define IPU_PRE_PREFETCH_ENG_CTRL 0x080
  42. #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0)
  43. #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1)
  44. #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
  45. #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8)
  46. #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11)
  47. #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12)
  48. #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14)
  49. #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15)
  50. #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0
  51. #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0)
  52. #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16)
  53. #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0
  54. #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0)
  55. #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16)
  56. #define IPU_PRE_STORE_ENG_CTRL 0x110
  57. #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0)
  58. #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
  59. #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
  60. #define IPU_PRE_STORE_ENG_STATUS 0x120
  61. #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff
  62. #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0
  63. #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff
  64. #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16
  65. #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30)
  66. #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31)
  67. #define IPU_PRE_STORE_ENG_SIZE 0x130
  68. #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
  69. #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
  70. #define IPU_PRE_STORE_ENG_PITCH 0x140
  71. #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0)
  72. #define IPU_PRE_STORE_ENG_ADDR 0x150
  73. struct ipu_pre {
  74. struct list_head list;
  75. struct device *dev;
  76. void __iomem *regs;
  77. struct clk *clk_axi;
  78. struct gen_pool *iram;
  79. dma_addr_t buffer_paddr;
  80. void *buffer_virt;
  81. bool in_use;
  82. unsigned int safe_window_end;
  83. unsigned int last_bufaddr;
  84. };
  85. static DEFINE_MUTEX(ipu_pre_list_mutex);
  86. static LIST_HEAD(ipu_pre_list);
  87. static int available_pres;
  88. int ipu_pre_get_available_count(void)
  89. {
  90. return available_pres;
  91. }
  92. struct ipu_pre *
  93. ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
  94. {
  95. struct device_node *pre_node = of_parse_phandle(dev->of_node,
  96. name, index);
  97. struct ipu_pre *pre;
  98. mutex_lock(&ipu_pre_list_mutex);
  99. list_for_each_entry(pre, &ipu_pre_list, list) {
  100. if (pre_node == pre->dev->of_node) {
  101. mutex_unlock(&ipu_pre_list_mutex);
  102. device_link_add(dev, pre->dev,
  103. DL_FLAG_AUTOREMOVE_CONSUMER);
  104. of_node_put(pre_node);
  105. return pre;
  106. }
  107. }
  108. mutex_unlock(&ipu_pre_list_mutex);
  109. of_node_put(pre_node);
  110. return NULL;
  111. }
  112. int ipu_pre_get(struct ipu_pre *pre)
  113. {
  114. u32 val;
  115. if (pre->in_use)
  116. return -EBUSY;
  117. /* first get the engine out of reset and remove clock gating */
  118. writel(0, pre->regs + IPU_PRE_CTRL);
  119. /* init defaults that should be applied to all streams */
  120. val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
  121. IPU_PRE_CTRL_HANDSHAKE_EN |
  122. IPU_PRE_CTRL_TPR_REST_SEL |
  123. IPU_PRE_CTRL_SDW_UPDATE;
  124. writel(val, pre->regs + IPU_PRE_CTRL);
  125. pre->in_use = true;
  126. return 0;
  127. }
  128. void ipu_pre_put(struct ipu_pre *pre)
  129. {
  130. writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
  131. pre->in_use = false;
  132. }
  133. void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
  134. unsigned int height, unsigned int stride, u32 format,
  135. uint64_t modifier, unsigned int bufaddr)
  136. {
  137. const struct drm_format_info *info = drm_format_info(format);
  138. u32 active_bpp = info->cpp[0] >> 1;
  139. u32 val;
  140. /* calculate safe window for ctrl register updates */
  141. if (modifier == DRM_FORMAT_MOD_LINEAR)
  142. pre->safe_window_end = height - 2;
  143. else
  144. pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
  145. writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
  146. writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
  147. pre->last_bufaddr = bufaddr;
  148. val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
  149. IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
  150. IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
  151. IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
  152. IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
  153. writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
  154. val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
  155. IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
  156. writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
  157. val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
  158. writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
  159. val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
  160. IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
  161. IPU_PRE_STORE_ENG_CTRL_STORE_EN;
  162. writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
  163. val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
  164. IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
  165. writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
  166. val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
  167. writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
  168. writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
  169. val = readl(pre->regs + IPU_PRE_TPR_CTRL);
  170. val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK;
  171. if (modifier != DRM_FORMAT_MOD_LINEAR) {
  172. /* only support single buffer formats for now */
  173. val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF;
  174. if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
  175. val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED;
  176. if (info->cpp[0] == 2)
  177. val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT;
  178. }
  179. writel(val, pre->regs + IPU_PRE_TPR_CTRL);
  180. val = readl(pre->regs + IPU_PRE_CTRL);
  181. val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
  182. IPU_PRE_CTRL_SDW_UPDATE;
  183. if (modifier == DRM_FORMAT_MOD_LINEAR)
  184. val &= ~IPU_PRE_CTRL_BLOCK_EN;
  185. else
  186. val |= IPU_PRE_CTRL_BLOCK_EN;
  187. writel(val, pre->regs + IPU_PRE_CTRL);
  188. }
  189. void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
  190. {
  191. unsigned long timeout = jiffies + msecs_to_jiffies(5);
  192. unsigned short current_yblock;
  193. u32 val;
  194. if (bufaddr == pre->last_bufaddr)
  195. return;
  196. writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
  197. pre->last_bufaddr = bufaddr;
  198. do {
  199. if (time_after(jiffies, timeout)) {
  200. dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
  201. return;
  202. }
  203. val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
  204. current_yblock =
  205. (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
  206. IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
  207. } while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
  208. writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
  209. }
  210. bool ipu_pre_update_pending(struct ipu_pre *pre)
  211. {
  212. return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) &
  213. IPU_PRE_CTRL_SDW_UPDATE);
  214. }
  215. u32 ipu_pre_get_baddr(struct ipu_pre *pre)
  216. {
  217. return (u32)pre->buffer_paddr;
  218. }
  219. static int ipu_pre_probe(struct platform_device *pdev)
  220. {
  221. struct device *dev = &pdev->dev;
  222. struct resource *res;
  223. struct ipu_pre *pre;
  224. pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
  225. if (!pre)
  226. return -ENOMEM;
  227. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  228. pre->regs = devm_ioremap_resource(&pdev->dev, res);
  229. if (IS_ERR(pre->regs))
  230. return PTR_ERR(pre->regs);
  231. pre->clk_axi = devm_clk_get(dev, "axi");
  232. if (IS_ERR(pre->clk_axi))
  233. return PTR_ERR(pre->clk_axi);
  234. pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
  235. if (!pre->iram)
  236. return -EPROBE_DEFER;
  237. /*
  238. * Allocate IRAM buffer with maximum size. This could be made dynamic,
  239. * but as there is no other user of this IRAM region and we can fit all
  240. * max sized buffers into it, there is no need yet.
  241. */
  242. pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
  243. IPU_PRE_NUM_SCANLINES * 4,
  244. &pre->buffer_paddr);
  245. if (!pre->buffer_virt)
  246. return -ENOMEM;
  247. clk_prepare_enable(pre->clk_axi);
  248. pre->dev = dev;
  249. platform_set_drvdata(pdev, pre);
  250. mutex_lock(&ipu_pre_list_mutex);
  251. list_add(&pre->list, &ipu_pre_list);
  252. available_pres++;
  253. mutex_unlock(&ipu_pre_list_mutex);
  254. return 0;
  255. }
  256. static int ipu_pre_remove(struct platform_device *pdev)
  257. {
  258. struct ipu_pre *pre = platform_get_drvdata(pdev);
  259. mutex_lock(&ipu_pre_list_mutex);
  260. list_del(&pre->list);
  261. available_pres--;
  262. mutex_unlock(&ipu_pre_list_mutex);
  263. clk_disable_unprepare(pre->clk_axi);
  264. if (pre->buffer_virt)
  265. gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
  266. IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
  267. return 0;
  268. }
  269. static const struct of_device_id ipu_pre_dt_ids[] = {
  270. { .compatible = "fsl,imx6qp-pre", },
  271. { /* sentinel */ },
  272. };
  273. struct platform_driver ipu_pre_drv = {
  274. .probe = ipu_pre_probe,
  275. .remove = ipu_pre_remove,
  276. .driver = {
  277. .name = "imx-ipu-pre",
  278. .of_match_table = ipu_pre_dt_ids,
  279. },
  280. };