ipu-ic.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2012-2014 Mentor Graphics Inc.
  4. * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  5. */
  6. #include <linux/types.h>
  7. #include <linux/init.h>
  8. #include <linux/errno.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/bitrev.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <linux/sizes.h>
  14. #include "ipu-prv.h"
  15. /* IC Register Offsets */
  16. #define IC_CONF 0x0000
  17. #define IC_PRP_ENC_RSC 0x0004
  18. #define IC_PRP_VF_RSC 0x0008
  19. #define IC_PP_RSC 0x000C
  20. #define IC_CMBP_1 0x0010
  21. #define IC_CMBP_2 0x0014
  22. #define IC_IDMAC_1 0x0018
  23. #define IC_IDMAC_2 0x001C
  24. #define IC_IDMAC_3 0x0020
  25. #define IC_IDMAC_4 0x0024
  26. /* IC Register Fields */
  27. #define IC_CONF_PRPENC_EN (1 << 0)
  28. #define IC_CONF_PRPENC_CSC1 (1 << 1)
  29. #define IC_CONF_PRPENC_ROT_EN (1 << 2)
  30. #define IC_CONF_PRPVF_EN (1 << 8)
  31. #define IC_CONF_PRPVF_CSC1 (1 << 9)
  32. #define IC_CONF_PRPVF_CSC2 (1 << 10)
  33. #define IC_CONF_PRPVF_CMB (1 << 11)
  34. #define IC_CONF_PRPVF_ROT_EN (1 << 12)
  35. #define IC_CONF_PP_EN (1 << 16)
  36. #define IC_CONF_PP_CSC1 (1 << 17)
  37. #define IC_CONF_PP_CSC2 (1 << 18)
  38. #define IC_CONF_PP_CMB (1 << 19)
  39. #define IC_CONF_PP_ROT_EN (1 << 20)
  40. #define IC_CONF_IC_GLB_LOC_A (1 << 28)
  41. #define IC_CONF_KEY_COLOR_EN (1 << 29)
  42. #define IC_CONF_RWS_EN (1 << 30)
  43. #define IC_CONF_CSI_MEM_WR_EN (1 << 31)
  44. #define IC_IDMAC_1_CB0_BURST_16 (1 << 0)
  45. #define IC_IDMAC_1_CB1_BURST_16 (1 << 1)
  46. #define IC_IDMAC_1_CB2_BURST_16 (1 << 2)
  47. #define IC_IDMAC_1_CB3_BURST_16 (1 << 3)
  48. #define IC_IDMAC_1_CB4_BURST_16 (1 << 4)
  49. #define IC_IDMAC_1_CB5_BURST_16 (1 << 5)
  50. #define IC_IDMAC_1_CB6_BURST_16 (1 << 6)
  51. #define IC_IDMAC_1_CB7_BURST_16 (1 << 7)
  52. #define IC_IDMAC_1_PRPENC_ROT_MASK (0x7 << 11)
  53. #define IC_IDMAC_1_PRPENC_ROT_OFFSET 11
  54. #define IC_IDMAC_1_PRPVF_ROT_MASK (0x7 << 14)
  55. #define IC_IDMAC_1_PRPVF_ROT_OFFSET 14
  56. #define IC_IDMAC_1_PP_ROT_MASK (0x7 << 17)
  57. #define IC_IDMAC_1_PP_ROT_OFFSET 17
  58. #define IC_IDMAC_1_PP_FLIP_RS (1 << 22)
  59. #define IC_IDMAC_1_PRPVF_FLIP_RS (1 << 21)
  60. #define IC_IDMAC_1_PRPENC_FLIP_RS (1 << 20)
  61. #define IC_IDMAC_2_PRPENC_HEIGHT_MASK (0x3ff << 0)
  62. #define IC_IDMAC_2_PRPENC_HEIGHT_OFFSET 0
  63. #define IC_IDMAC_2_PRPVF_HEIGHT_MASK (0x3ff << 10)
  64. #define IC_IDMAC_2_PRPVF_HEIGHT_OFFSET 10
  65. #define IC_IDMAC_2_PP_HEIGHT_MASK (0x3ff << 20)
  66. #define IC_IDMAC_2_PP_HEIGHT_OFFSET 20
  67. #define IC_IDMAC_3_PRPENC_WIDTH_MASK (0x3ff << 0)
  68. #define IC_IDMAC_3_PRPENC_WIDTH_OFFSET 0
  69. #define IC_IDMAC_3_PRPVF_WIDTH_MASK (0x3ff << 10)
  70. #define IC_IDMAC_3_PRPVF_WIDTH_OFFSET 10
  71. #define IC_IDMAC_3_PP_WIDTH_MASK (0x3ff << 20)
  72. #define IC_IDMAC_3_PP_WIDTH_OFFSET 20
  73. struct ic_task_regoffs {
  74. u32 rsc;
  75. u32 tpmem_csc[2];
  76. };
  77. struct ic_task_bitfields {
  78. u32 ic_conf_en;
  79. u32 ic_conf_rot_en;
  80. u32 ic_conf_cmb_en;
  81. u32 ic_conf_csc1_en;
  82. u32 ic_conf_csc2_en;
  83. u32 ic_cmb_galpha_bit;
  84. };
  85. static const struct ic_task_regoffs ic_task_reg[IC_NUM_TASKS] = {
  86. [IC_TASK_ENCODER] = {
  87. .rsc = IC_PRP_ENC_RSC,
  88. .tpmem_csc = {0x2008, 0},
  89. },
  90. [IC_TASK_VIEWFINDER] = {
  91. .rsc = IC_PRP_VF_RSC,
  92. .tpmem_csc = {0x4028, 0x4040},
  93. },
  94. [IC_TASK_POST_PROCESSOR] = {
  95. .rsc = IC_PP_RSC,
  96. .tpmem_csc = {0x6060, 0x6078},
  97. },
  98. };
  99. static const struct ic_task_bitfields ic_task_bit[IC_NUM_TASKS] = {
  100. [IC_TASK_ENCODER] = {
  101. .ic_conf_en = IC_CONF_PRPENC_EN,
  102. .ic_conf_rot_en = IC_CONF_PRPENC_ROT_EN,
  103. .ic_conf_cmb_en = 0, /* NA */
  104. .ic_conf_csc1_en = IC_CONF_PRPENC_CSC1,
  105. .ic_conf_csc2_en = 0, /* NA */
  106. .ic_cmb_galpha_bit = 0, /* NA */
  107. },
  108. [IC_TASK_VIEWFINDER] = {
  109. .ic_conf_en = IC_CONF_PRPVF_EN,
  110. .ic_conf_rot_en = IC_CONF_PRPVF_ROT_EN,
  111. .ic_conf_cmb_en = IC_CONF_PRPVF_CMB,
  112. .ic_conf_csc1_en = IC_CONF_PRPVF_CSC1,
  113. .ic_conf_csc2_en = IC_CONF_PRPVF_CSC2,
  114. .ic_cmb_galpha_bit = 0,
  115. },
  116. [IC_TASK_POST_PROCESSOR] = {
  117. .ic_conf_en = IC_CONF_PP_EN,
  118. .ic_conf_rot_en = IC_CONF_PP_ROT_EN,
  119. .ic_conf_cmb_en = IC_CONF_PP_CMB,
  120. .ic_conf_csc1_en = IC_CONF_PP_CSC1,
  121. .ic_conf_csc2_en = IC_CONF_PP_CSC2,
  122. .ic_cmb_galpha_bit = 8,
  123. },
  124. };
  125. struct ipu_ic_priv;
  126. struct ipu_ic {
  127. enum ipu_ic_task task;
  128. const struct ic_task_regoffs *reg;
  129. const struct ic_task_bitfields *bit;
  130. struct ipu_ic_colorspace in_cs;
  131. struct ipu_ic_colorspace g_in_cs;
  132. struct ipu_ic_colorspace out_cs;
  133. bool graphics;
  134. bool rotation;
  135. bool in_use;
  136. struct ipu_ic_priv *priv;
  137. };
  138. struct ipu_ic_priv {
  139. void __iomem *base;
  140. void __iomem *tpmem_base;
  141. spinlock_t lock;
  142. struct ipu_soc *ipu;
  143. int use_count;
  144. int irt_use_count;
  145. struct ipu_ic task[IC_NUM_TASKS];
  146. };
  147. static inline u32 ipu_ic_read(struct ipu_ic *ic, unsigned offset)
  148. {
  149. return readl(ic->priv->base + offset);
  150. }
  151. static inline void ipu_ic_write(struct ipu_ic *ic, u32 value, unsigned offset)
  152. {
  153. writel(value, ic->priv->base + offset);
  154. }
  155. static int init_csc(struct ipu_ic *ic,
  156. const struct ipu_ic_csc *csc,
  157. int csc_index)
  158. {
  159. struct ipu_ic_priv *priv = ic->priv;
  160. u32 __iomem *base;
  161. const u16 (*c)[3];
  162. const u16 *a;
  163. u32 param;
  164. base = (u32 __iomem *)
  165. (priv->tpmem_base + ic->reg->tpmem_csc[csc_index]);
  166. /* Cast to unsigned */
  167. c = (const u16 (*)[3])csc->params.coeff;
  168. a = (const u16 *)csc->params.offset;
  169. param = ((a[0] & 0x1f) << 27) | ((c[0][0] & 0x1ff) << 18) |
  170. ((c[1][1] & 0x1ff) << 9) | (c[2][2] & 0x1ff);
  171. writel(param, base++);
  172. param = ((a[0] & 0x1fe0) >> 5) | (csc->params.scale << 8) |
  173. (csc->params.sat << 10);
  174. writel(param, base++);
  175. param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) |
  176. ((c[1][0] & 0x1ff) << 9) | (c[2][0] & 0x1ff);
  177. writel(param, base++);
  178. param = ((a[1] & 0x1fe0) >> 5);
  179. writel(param, base++);
  180. param = ((a[2] & 0x1f) << 27) | ((c[0][2] & 0x1ff) << 18) |
  181. ((c[1][2] & 0x1ff) << 9) | (c[2][1] & 0x1ff);
  182. writel(param, base++);
  183. param = ((a[2] & 0x1fe0) >> 5);
  184. writel(param, base++);
  185. return 0;
  186. }
  187. static int calc_resize_coeffs(struct ipu_ic *ic,
  188. u32 in_size, u32 out_size,
  189. u32 *resize_coeff,
  190. u32 *downsize_coeff)
  191. {
  192. struct ipu_ic_priv *priv = ic->priv;
  193. struct ipu_soc *ipu = priv->ipu;
  194. u32 temp_size, temp_downsize;
  195. /*
  196. * Input size cannot be more than 4096, and output size cannot
  197. * be more than 1024
  198. */
  199. if (in_size > 4096) {
  200. dev_err(ipu->dev, "Unsupported resize (in_size > 4096)\n");
  201. return -EINVAL;
  202. }
  203. if (out_size > 1024) {
  204. dev_err(ipu->dev, "Unsupported resize (out_size > 1024)\n");
  205. return -EINVAL;
  206. }
  207. /* Cannot downsize more than 4:1 */
  208. if ((out_size << 2) < in_size) {
  209. dev_err(ipu->dev, "Unsupported downsize\n");
  210. return -EINVAL;
  211. }
  212. /* Compute downsizing coefficient */
  213. temp_downsize = 0;
  214. temp_size = in_size;
  215. while (((temp_size > 1024) || (temp_size >= out_size * 2)) &&
  216. (temp_downsize < 2)) {
  217. temp_size >>= 1;
  218. temp_downsize++;
  219. }
  220. *downsize_coeff = temp_downsize;
  221. /*
  222. * compute resizing coefficient using the following equation:
  223. * resize_coeff = M * (SI - 1) / (SO - 1)
  224. * where M = 2^13, SI = input size, SO = output size
  225. */
  226. *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
  227. if (*resize_coeff >= 16384L) {
  228. dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n");
  229. *resize_coeff = 0x3FFF;
  230. }
  231. return 0;
  232. }
  233. void ipu_ic_task_enable(struct ipu_ic *ic)
  234. {
  235. struct ipu_ic_priv *priv = ic->priv;
  236. unsigned long flags;
  237. u32 ic_conf;
  238. spin_lock_irqsave(&priv->lock, flags);
  239. ic_conf = ipu_ic_read(ic, IC_CONF);
  240. ic_conf |= ic->bit->ic_conf_en;
  241. if (ic->rotation)
  242. ic_conf |= ic->bit->ic_conf_rot_en;
  243. if (ic->in_cs.cs != ic->out_cs.cs)
  244. ic_conf |= ic->bit->ic_conf_csc1_en;
  245. if (ic->graphics) {
  246. ic_conf |= ic->bit->ic_conf_cmb_en;
  247. ic_conf |= ic->bit->ic_conf_csc1_en;
  248. if (ic->g_in_cs.cs != ic->out_cs.cs)
  249. ic_conf |= ic->bit->ic_conf_csc2_en;
  250. }
  251. ipu_ic_write(ic, ic_conf, IC_CONF);
  252. spin_unlock_irqrestore(&priv->lock, flags);
  253. }
  254. EXPORT_SYMBOL_GPL(ipu_ic_task_enable);
  255. void ipu_ic_task_disable(struct ipu_ic *ic)
  256. {
  257. struct ipu_ic_priv *priv = ic->priv;
  258. unsigned long flags;
  259. u32 ic_conf;
  260. spin_lock_irqsave(&priv->lock, flags);
  261. ic_conf = ipu_ic_read(ic, IC_CONF);
  262. ic_conf &= ~(ic->bit->ic_conf_en |
  263. ic->bit->ic_conf_csc1_en |
  264. ic->bit->ic_conf_rot_en);
  265. if (ic->bit->ic_conf_csc2_en)
  266. ic_conf &= ~ic->bit->ic_conf_csc2_en;
  267. if (ic->bit->ic_conf_cmb_en)
  268. ic_conf &= ~ic->bit->ic_conf_cmb_en;
  269. ipu_ic_write(ic, ic_conf, IC_CONF);
  270. spin_unlock_irqrestore(&priv->lock, flags);
  271. }
  272. EXPORT_SYMBOL_GPL(ipu_ic_task_disable);
  273. int ipu_ic_task_graphics_init(struct ipu_ic *ic,
  274. const struct ipu_ic_colorspace *g_in_cs,
  275. bool galpha_en, u32 galpha,
  276. bool colorkey_en, u32 colorkey)
  277. {
  278. struct ipu_ic_priv *priv = ic->priv;
  279. struct ipu_ic_csc csc2;
  280. unsigned long flags;
  281. u32 reg, ic_conf;
  282. int ret = 0;
  283. if (ic->task == IC_TASK_ENCODER)
  284. return -EINVAL;
  285. spin_lock_irqsave(&priv->lock, flags);
  286. ic_conf = ipu_ic_read(ic, IC_CONF);
  287. if (!(ic_conf & ic->bit->ic_conf_csc1_en)) {
  288. struct ipu_ic_csc csc1;
  289. ret = ipu_ic_calc_csc(&csc1,
  290. V4L2_YCBCR_ENC_601,
  291. V4L2_QUANTIZATION_FULL_RANGE,
  292. IPUV3_COLORSPACE_RGB,
  293. V4L2_YCBCR_ENC_601,
  294. V4L2_QUANTIZATION_FULL_RANGE,
  295. IPUV3_COLORSPACE_RGB);
  296. if (ret)
  297. goto unlock;
  298. /* need transparent CSC1 conversion */
  299. ret = init_csc(ic, &csc1, 0);
  300. if (ret)
  301. goto unlock;
  302. }
  303. ic->g_in_cs = *g_in_cs;
  304. csc2.in_cs = ic->g_in_cs;
  305. csc2.out_cs = ic->out_cs;
  306. ret = __ipu_ic_calc_csc(&csc2);
  307. if (ret)
  308. goto unlock;
  309. ret = init_csc(ic, &csc2, 1);
  310. if (ret)
  311. goto unlock;
  312. if (galpha_en) {
  313. ic_conf |= IC_CONF_IC_GLB_LOC_A;
  314. reg = ipu_ic_read(ic, IC_CMBP_1);
  315. reg &= ~(0xff << ic->bit->ic_cmb_galpha_bit);
  316. reg |= (galpha << ic->bit->ic_cmb_galpha_bit);
  317. ipu_ic_write(ic, reg, IC_CMBP_1);
  318. } else
  319. ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
  320. if (colorkey_en) {
  321. ic_conf |= IC_CONF_KEY_COLOR_EN;
  322. ipu_ic_write(ic, colorkey, IC_CMBP_2);
  323. } else
  324. ic_conf &= ~IC_CONF_KEY_COLOR_EN;
  325. ipu_ic_write(ic, ic_conf, IC_CONF);
  326. ic->graphics = true;
  327. unlock:
  328. spin_unlock_irqrestore(&priv->lock, flags);
  329. return ret;
  330. }
  331. EXPORT_SYMBOL_GPL(ipu_ic_task_graphics_init);
  332. int ipu_ic_task_init_rsc(struct ipu_ic *ic,
  333. const struct ipu_ic_csc *csc,
  334. int in_width, int in_height,
  335. int out_width, int out_height,
  336. u32 rsc)
  337. {
  338. struct ipu_ic_priv *priv = ic->priv;
  339. u32 downsize_coeff, resize_coeff;
  340. unsigned long flags;
  341. int ret = 0;
  342. if (!rsc) {
  343. /* Setup vertical resizing */
  344. ret = calc_resize_coeffs(ic, in_height, out_height,
  345. &resize_coeff, &downsize_coeff);
  346. if (ret)
  347. return ret;
  348. rsc = (downsize_coeff << 30) | (resize_coeff << 16);
  349. /* Setup horizontal resizing */
  350. ret = calc_resize_coeffs(ic, in_width, out_width,
  351. &resize_coeff, &downsize_coeff);
  352. if (ret)
  353. return ret;
  354. rsc |= (downsize_coeff << 14) | resize_coeff;
  355. }
  356. spin_lock_irqsave(&priv->lock, flags);
  357. ipu_ic_write(ic, rsc, ic->reg->rsc);
  358. /* Setup color space conversion */
  359. ic->in_cs = csc->in_cs;
  360. ic->out_cs = csc->out_cs;
  361. ret = init_csc(ic, csc, 0);
  362. spin_unlock_irqrestore(&priv->lock, flags);
  363. return ret;
  364. }
  365. int ipu_ic_task_init(struct ipu_ic *ic,
  366. const struct ipu_ic_csc *csc,
  367. int in_width, int in_height,
  368. int out_width, int out_height)
  369. {
  370. return ipu_ic_task_init_rsc(ic, csc,
  371. in_width, in_height,
  372. out_width, out_height, 0);
  373. }
  374. EXPORT_SYMBOL_GPL(ipu_ic_task_init);
  375. int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
  376. u32 width, u32 height, int burst_size,
  377. enum ipu_rotate_mode rot)
  378. {
  379. struct ipu_ic_priv *priv = ic->priv;
  380. struct ipu_soc *ipu = priv->ipu;
  381. u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
  382. u32 temp_rot = bitrev8(rot) >> 5;
  383. bool need_hor_flip = false;
  384. unsigned long flags;
  385. int ret = 0;
  386. if ((burst_size != 8) && (burst_size != 16)) {
  387. dev_err(ipu->dev, "Illegal burst length for IC\n");
  388. return -EINVAL;
  389. }
  390. width--;
  391. height--;
  392. if (temp_rot & 0x2) /* Need horizontal flip */
  393. need_hor_flip = true;
  394. spin_lock_irqsave(&priv->lock, flags);
  395. ic_idmac_1 = ipu_ic_read(ic, IC_IDMAC_1);
  396. ic_idmac_2 = ipu_ic_read(ic, IC_IDMAC_2);
  397. ic_idmac_3 = ipu_ic_read(ic, IC_IDMAC_3);
  398. switch (channel->num) {
  399. case IPUV3_CHANNEL_IC_PP_MEM:
  400. if (burst_size == 16)
  401. ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
  402. else
  403. ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
  404. if (need_hor_flip)
  405. ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
  406. else
  407. ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
  408. ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
  409. ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
  410. ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
  411. ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
  412. break;
  413. case IPUV3_CHANNEL_MEM_IC_PP:
  414. if (burst_size == 16)
  415. ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
  416. else
  417. ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
  418. break;
  419. case IPUV3_CHANNEL_MEM_ROT_PP:
  420. ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
  421. ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
  422. break;
  423. case IPUV3_CHANNEL_MEM_IC_PRP_VF:
  424. if (burst_size == 16)
  425. ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
  426. else
  427. ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
  428. break;
  429. case IPUV3_CHANNEL_IC_PRP_ENC_MEM:
  430. if (burst_size == 16)
  431. ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
  432. else
  433. ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
  434. if (need_hor_flip)
  435. ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
  436. else
  437. ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
  438. ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
  439. ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
  440. ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
  441. ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
  442. break;
  443. case IPUV3_CHANNEL_MEM_ROT_ENC:
  444. ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
  445. ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
  446. break;
  447. case IPUV3_CHANNEL_IC_PRP_VF_MEM:
  448. if (burst_size == 16)
  449. ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
  450. else
  451. ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
  452. if (need_hor_flip)
  453. ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
  454. else
  455. ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
  456. ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
  457. ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
  458. ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
  459. ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
  460. break;
  461. case IPUV3_CHANNEL_MEM_ROT_VF:
  462. ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
  463. ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
  464. break;
  465. case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
  466. if (burst_size == 16)
  467. ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
  468. else
  469. ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
  470. break;
  471. case IPUV3_CHANNEL_G_MEM_IC_PP:
  472. if (burst_size == 16)
  473. ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
  474. else
  475. ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
  476. break;
  477. case IPUV3_CHANNEL_VDI_MEM_IC_VF:
  478. if (burst_size == 16)
  479. ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
  480. else
  481. ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
  482. break;
  483. default:
  484. goto unlock;
  485. }
  486. ipu_ic_write(ic, ic_idmac_1, IC_IDMAC_1);
  487. ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2);
  488. ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3);
  489. if (ipu_rot_mode_is_irt(rot))
  490. ic->rotation = true;
  491. unlock:
  492. spin_unlock_irqrestore(&priv->lock, flags);
  493. return ret;
  494. }
  495. EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init);
  496. static void ipu_irt_enable(struct ipu_ic *ic)
  497. {
  498. struct ipu_ic_priv *priv = ic->priv;
  499. if (!priv->irt_use_count)
  500. ipu_module_enable(priv->ipu, IPU_CONF_ROT_EN);
  501. priv->irt_use_count++;
  502. }
  503. static void ipu_irt_disable(struct ipu_ic *ic)
  504. {
  505. struct ipu_ic_priv *priv = ic->priv;
  506. if (priv->irt_use_count) {
  507. if (!--priv->irt_use_count)
  508. ipu_module_disable(priv->ipu, IPU_CONF_ROT_EN);
  509. }
  510. }
  511. int ipu_ic_enable(struct ipu_ic *ic)
  512. {
  513. struct ipu_ic_priv *priv = ic->priv;
  514. unsigned long flags;
  515. spin_lock_irqsave(&priv->lock, flags);
  516. if (!priv->use_count)
  517. ipu_module_enable(priv->ipu, IPU_CONF_IC_EN);
  518. priv->use_count++;
  519. if (ic->rotation)
  520. ipu_irt_enable(ic);
  521. spin_unlock_irqrestore(&priv->lock, flags);
  522. return 0;
  523. }
  524. EXPORT_SYMBOL_GPL(ipu_ic_enable);
  525. int ipu_ic_disable(struct ipu_ic *ic)
  526. {
  527. struct ipu_ic_priv *priv = ic->priv;
  528. unsigned long flags;
  529. spin_lock_irqsave(&priv->lock, flags);
  530. priv->use_count--;
  531. if (!priv->use_count)
  532. ipu_module_disable(priv->ipu, IPU_CONF_IC_EN);
  533. if (priv->use_count < 0)
  534. priv->use_count = 0;
  535. if (ic->rotation)
  536. ipu_irt_disable(ic);
  537. ic->rotation = ic->graphics = false;
  538. spin_unlock_irqrestore(&priv->lock, flags);
  539. return 0;
  540. }
  541. EXPORT_SYMBOL_GPL(ipu_ic_disable);
  542. struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task)
  543. {
  544. struct ipu_ic_priv *priv = ipu->ic_priv;
  545. unsigned long flags;
  546. struct ipu_ic *ic, *ret;
  547. if (task >= IC_NUM_TASKS)
  548. return ERR_PTR(-EINVAL);
  549. ic = &priv->task[task];
  550. spin_lock_irqsave(&priv->lock, flags);
  551. if (ic->in_use) {
  552. ret = ERR_PTR(-EBUSY);
  553. goto unlock;
  554. }
  555. ic->in_use = true;
  556. ret = ic;
  557. unlock:
  558. spin_unlock_irqrestore(&priv->lock, flags);
  559. return ret;
  560. }
  561. EXPORT_SYMBOL_GPL(ipu_ic_get);
  562. void ipu_ic_put(struct ipu_ic *ic)
  563. {
  564. struct ipu_ic_priv *priv = ic->priv;
  565. unsigned long flags;
  566. spin_lock_irqsave(&priv->lock, flags);
  567. ic->in_use = false;
  568. spin_unlock_irqrestore(&priv->lock, flags);
  569. }
  570. EXPORT_SYMBOL_GPL(ipu_ic_put);
  571. int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
  572. unsigned long base, unsigned long tpmem_base)
  573. {
  574. struct ipu_ic_priv *priv;
  575. int i;
  576. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  577. if (!priv)
  578. return -ENOMEM;
  579. ipu->ic_priv = priv;
  580. spin_lock_init(&priv->lock);
  581. priv->base = devm_ioremap(dev, base, PAGE_SIZE);
  582. if (!priv->base)
  583. return -ENOMEM;
  584. priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K);
  585. if (!priv->tpmem_base)
  586. return -ENOMEM;
  587. dev_dbg(dev, "IC base: 0x%08lx remapped to %p\n", base, priv->base);
  588. priv->ipu = ipu;
  589. for (i = 0; i < IC_NUM_TASKS; i++) {
  590. priv->task[i].task = i;
  591. priv->task[i].priv = priv;
  592. priv->task[i].reg = &ic_task_reg[i];
  593. priv->task[i].bit = &ic_task_bit[i];
  594. }
  595. return 0;
  596. }
  597. void ipu_ic_exit(struct ipu_soc *ipu)
  598. {
  599. }
  600. void ipu_ic_dump(struct ipu_ic *ic)
  601. {
  602. struct ipu_ic_priv *priv = ic->priv;
  603. struct ipu_soc *ipu = priv->ipu;
  604. dev_dbg(ipu->dev, "IC_CONF = \t0x%08X\n",
  605. ipu_ic_read(ic, IC_CONF));
  606. dev_dbg(ipu->dev, "IC_PRP_ENC_RSC = \t0x%08X\n",
  607. ipu_ic_read(ic, IC_PRP_ENC_RSC));
  608. dev_dbg(ipu->dev, "IC_PRP_VF_RSC = \t0x%08X\n",
  609. ipu_ic_read(ic, IC_PRP_VF_RSC));
  610. dev_dbg(ipu->dev, "IC_PP_RSC = \t0x%08X\n",
  611. ipu_ic_read(ic, IC_PP_RSC));
  612. dev_dbg(ipu->dev, "IC_CMBP_1 = \t0x%08X\n",
  613. ipu_ic_read(ic, IC_CMBP_1));
  614. dev_dbg(ipu->dev, "IC_CMBP_2 = \t0x%08X\n",
  615. ipu_ic_read(ic, IC_CMBP_2));
  616. dev_dbg(ipu->dev, "IC_IDMAC_1 = \t0x%08X\n",
  617. ipu_ic_read(ic, IC_IDMAC_1));
  618. dev_dbg(ipu->dev, "IC_IDMAC_2 = \t0x%08X\n",
  619. ipu_ic_read(ic, IC_IDMAC_2));
  620. dev_dbg(ipu->dev, "IC_IDMAC_3 = \t0x%08X\n",
  621. ipu_ic_read(ic, IC_IDMAC_3));
  622. dev_dbg(ipu->dev, "IC_IDMAC_4 = \t0x%08X\n",
  623. ipu_ic_read(ic, IC_IDMAC_4));
  624. }
  625. EXPORT_SYMBOL_GPL(ipu_ic_dump);