ipu-dmfc.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
  4. * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
  5. */
  6. #include <linux/export.h>
  7. #include <linux/types.h>
  8. #include <linux/errno.h>
  9. #include <linux/io.h>
  10. #include <video/imx-ipu-v3.h>
  11. #include "ipu-prv.h"
  12. #define DMFC_RD_CHAN 0x0000
  13. #define DMFC_WR_CHAN 0x0004
  14. #define DMFC_WR_CHAN_DEF 0x0008
  15. #define DMFC_DP_CHAN 0x000c
  16. #define DMFC_DP_CHAN_DEF 0x0010
  17. #define DMFC_GENERAL1 0x0014
  18. #define DMFC_GENERAL2 0x0018
  19. #define DMFC_IC_CTRL 0x001c
  20. #define DMFC_WR_CHAN_ALT 0x0020
  21. #define DMFC_WR_CHAN_DEF_ALT 0x0024
  22. #define DMFC_DP_CHAN_ALT 0x0028
  23. #define DMFC_DP_CHAN_DEF_ALT 0x002c
  24. #define DMFC_GENERAL1_ALT 0x0030
  25. #define DMFC_STAT 0x0034
  26. #define DMFC_WR_CHAN_1_28 0
  27. #define DMFC_WR_CHAN_2_41 8
  28. #define DMFC_WR_CHAN_1C_42 16
  29. #define DMFC_WR_CHAN_2C_43 24
  30. #define DMFC_DP_CHAN_5B_23 0
  31. #define DMFC_DP_CHAN_5F_27 8
  32. #define DMFC_DP_CHAN_6B_24 16
  33. #define DMFC_DP_CHAN_6F_29 24
  34. struct dmfc_channel_data {
  35. int ipu_channel;
  36. unsigned long channel_reg;
  37. unsigned long shift;
  38. unsigned eot_shift;
  39. unsigned max_fifo_lines;
  40. };
  41. static const struct dmfc_channel_data dmfcdata[] = {
  42. {
  43. .ipu_channel = IPUV3_CHANNEL_MEM_BG_SYNC,
  44. .channel_reg = DMFC_DP_CHAN,
  45. .shift = DMFC_DP_CHAN_5B_23,
  46. .eot_shift = 20,
  47. .max_fifo_lines = 3,
  48. }, {
  49. .ipu_channel = 24,
  50. .channel_reg = DMFC_DP_CHAN,
  51. .shift = DMFC_DP_CHAN_6B_24,
  52. .eot_shift = 22,
  53. .max_fifo_lines = 1,
  54. }, {
  55. .ipu_channel = IPUV3_CHANNEL_MEM_FG_SYNC,
  56. .channel_reg = DMFC_DP_CHAN,
  57. .shift = DMFC_DP_CHAN_5F_27,
  58. .eot_shift = 21,
  59. .max_fifo_lines = 2,
  60. }, {
  61. .ipu_channel = IPUV3_CHANNEL_MEM_DC_SYNC,
  62. .channel_reg = DMFC_WR_CHAN,
  63. .shift = DMFC_WR_CHAN_1_28,
  64. .eot_shift = 16,
  65. .max_fifo_lines = 2,
  66. }, {
  67. .ipu_channel = 29,
  68. .channel_reg = DMFC_DP_CHAN,
  69. .shift = DMFC_DP_CHAN_6F_29,
  70. .eot_shift = 23,
  71. .max_fifo_lines = 1,
  72. },
  73. };
  74. #define DMFC_NUM_CHANNELS ARRAY_SIZE(dmfcdata)
  75. struct ipu_dmfc_priv;
  76. struct dmfc_channel {
  77. unsigned slots;
  78. struct ipu_soc *ipu;
  79. struct ipu_dmfc_priv *priv;
  80. const struct dmfc_channel_data *data;
  81. };
  82. struct ipu_dmfc_priv {
  83. struct ipu_soc *ipu;
  84. struct device *dev;
  85. struct dmfc_channel channels[DMFC_NUM_CHANNELS];
  86. struct mutex mutex;
  87. void __iomem *base;
  88. int use_count;
  89. };
  90. int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
  91. {
  92. struct ipu_dmfc_priv *priv = dmfc->priv;
  93. mutex_lock(&priv->mutex);
  94. if (!priv->use_count)
  95. ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
  96. priv->use_count++;
  97. mutex_unlock(&priv->mutex);
  98. return 0;
  99. }
  100. EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
  101. void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
  102. {
  103. struct ipu_dmfc_priv *priv = dmfc->priv;
  104. mutex_lock(&priv->mutex);
  105. priv->use_count--;
  106. if (!priv->use_count)
  107. ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
  108. if (priv->use_count < 0)
  109. priv->use_count = 0;
  110. mutex_unlock(&priv->mutex);
  111. }
  112. EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
  113. void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width)
  114. {
  115. struct ipu_dmfc_priv *priv = dmfc->priv;
  116. u32 dmfc_gen1;
  117. mutex_lock(&priv->mutex);
  118. dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
  119. if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
  120. dmfc_gen1 |= 1 << dmfc->data->eot_shift;
  121. else
  122. dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
  123. writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
  124. mutex_unlock(&priv->mutex);
  125. }
  126. EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot);
  127. struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
  128. {
  129. struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
  130. int i;
  131. for (i = 0; i < DMFC_NUM_CHANNELS; i++)
  132. if (dmfcdata[i].ipu_channel == ipu_channel)
  133. return &priv->channels[i];
  134. return ERR_PTR(-ENODEV);
  135. }
  136. EXPORT_SYMBOL_GPL(ipu_dmfc_get);
  137. void ipu_dmfc_put(struct dmfc_channel *dmfc)
  138. {
  139. }
  140. EXPORT_SYMBOL_GPL(ipu_dmfc_put);
  141. int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
  142. struct clk *ipu_clk)
  143. {
  144. struct ipu_dmfc_priv *priv;
  145. int i;
  146. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  147. if (!priv)
  148. return -ENOMEM;
  149. priv->base = devm_ioremap(dev, base, PAGE_SIZE);
  150. if (!priv->base)
  151. return -ENOMEM;
  152. priv->dev = dev;
  153. priv->ipu = ipu;
  154. mutex_init(&priv->mutex);
  155. ipu->dmfc_priv = priv;
  156. for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
  157. priv->channels[i].priv = priv;
  158. priv->channels[i].ipu = ipu;
  159. priv->channels[i].data = &dmfcdata[i];
  160. if (dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC ||
  161. dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_FG_SYNC ||
  162. dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_DC_SYNC)
  163. priv->channels[i].slots = 2;
  164. }
  165. writel(0x00000050, priv->base + DMFC_WR_CHAN);
  166. writel(0x00005654, priv->base + DMFC_DP_CHAN);
  167. writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
  168. writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
  169. writel(0x00000003, priv->base + DMFC_GENERAL1);
  170. return 0;
  171. }
  172. void ipu_dmfc_exit(struct ipu_soc *ipu)
  173. {
  174. }