ipu-dc.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
  4. * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
  5. */
  6. #include <linux/export.h>
  7. #include <linux/module.h>
  8. #include <linux/types.h>
  9. #include <linux/errno.h>
  10. #include <linux/delay.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <video/imx-ipu-v3.h>
  14. #include "ipu-prv.h"
  15. #define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
  16. #define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
  17. #define DC_EVT_NF 0
  18. #define DC_EVT_NL 1
  19. #define DC_EVT_EOF 2
  20. #define DC_EVT_NFIELD 3
  21. #define DC_EVT_EOL 4
  22. #define DC_EVT_EOFIELD 5
  23. #define DC_EVT_NEW_ADDR 6
  24. #define DC_EVT_NEW_CHAN 7
  25. #define DC_EVT_NEW_DATA 8
  26. #define DC_EVT_NEW_ADDR_W_0 0
  27. #define DC_EVT_NEW_ADDR_W_1 1
  28. #define DC_EVT_NEW_CHAN_W_0 2
  29. #define DC_EVT_NEW_CHAN_W_1 3
  30. #define DC_EVT_NEW_DATA_W_0 4
  31. #define DC_EVT_NEW_DATA_W_1 5
  32. #define DC_EVT_NEW_ADDR_R_0 6
  33. #define DC_EVT_NEW_ADDR_R_1 7
  34. #define DC_EVT_NEW_CHAN_R_0 8
  35. #define DC_EVT_NEW_CHAN_R_1 9
  36. #define DC_EVT_NEW_DATA_R_0 10
  37. #define DC_EVT_NEW_DATA_R_1 11
  38. #define DC_WR_CH_CONF 0x0
  39. #define DC_WR_CH_ADDR 0x4
  40. #define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
  41. #define DC_GEN 0xd4
  42. #define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
  43. #define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
  44. #define DC_STAT 0x1c8
  45. #define WROD(lf) (0x18 | ((lf) << 1))
  46. #define WRG 0x01
  47. #define WCLK 0xc9
  48. #define SYNC_WAVE 0
  49. #define NULL_WAVE (-1)
  50. #define DC_GEN_SYNC_1_6_SYNC (2 << 1)
  51. #define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
  52. #define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
  53. #define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
  54. #define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
  55. #define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
  56. #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
  57. #define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
  58. #define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
  59. #define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
  60. #define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
  61. #define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
  62. #define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
  63. #define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
  64. #define IPU_DC_NUM_CHANNELS 10
  65. struct ipu_dc_priv;
  66. enum ipu_dc_map {
  67. IPU_DC_MAP_RGB24,
  68. IPU_DC_MAP_RGB565,
  69. IPU_DC_MAP_GBR24, /* TVEv2 */
  70. IPU_DC_MAP_BGR666,
  71. IPU_DC_MAP_LVDS666,
  72. IPU_DC_MAP_BGR24,
  73. };
  74. struct ipu_dc {
  75. /* The display interface number assigned to this dc channel */
  76. unsigned int di;
  77. void __iomem *base;
  78. struct ipu_dc_priv *priv;
  79. int chno;
  80. bool in_use;
  81. };
  82. struct ipu_dc_priv {
  83. void __iomem *dc_reg;
  84. void __iomem *dc_tmpl_reg;
  85. struct ipu_soc *ipu;
  86. struct device *dev;
  87. struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
  88. struct mutex mutex;
  89. struct completion comp;
  90. int use_count;
  91. };
  92. static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
  93. {
  94. u32 reg;
  95. reg = readl(dc->base + DC_RL_CH(event));
  96. reg &= ~(0xffff << (16 * (event & 0x1)));
  97. reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
  98. writel(reg, dc->base + DC_RL_CH(event));
  99. }
  100. static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
  101. int map, int wave, int glue, int sync, int stop)
  102. {
  103. struct ipu_dc_priv *priv = dc->priv;
  104. u32 reg1, reg2;
  105. if (opcode == WCLK) {
  106. reg1 = (operand << 20) & 0xfff00000;
  107. reg2 = operand >> 12 | opcode << 1 | stop << 9;
  108. } else if (opcode == WRG) {
  109. reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
  110. reg2 = operand >> 17 | opcode << 7 | stop << 9;
  111. } else {
  112. reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
  113. reg2 = operand >> 12 | opcode << 4 | stop << 9;
  114. }
  115. writel(reg1, priv->dc_tmpl_reg + word * 8);
  116. writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
  117. }
  118. static int ipu_bus_format_to_map(u32 fmt)
  119. {
  120. switch (fmt) {
  121. default:
  122. WARN_ON(1);
  123. fallthrough;
  124. case MEDIA_BUS_FMT_RGB888_1X24:
  125. return IPU_DC_MAP_RGB24;
  126. case MEDIA_BUS_FMT_RGB565_1X16:
  127. return IPU_DC_MAP_RGB565;
  128. case MEDIA_BUS_FMT_GBR888_1X24:
  129. return IPU_DC_MAP_GBR24;
  130. case MEDIA_BUS_FMT_RGB666_1X18:
  131. return IPU_DC_MAP_BGR666;
  132. case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
  133. return IPU_DC_MAP_LVDS666;
  134. case MEDIA_BUS_FMT_BGR888_1X24:
  135. return IPU_DC_MAP_BGR24;
  136. }
  137. }
  138. int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
  139. u32 bus_format, u32 width)
  140. {
  141. struct ipu_dc_priv *priv = dc->priv;
  142. int addr, sync;
  143. u32 reg = 0;
  144. int map;
  145. dc->di = ipu_di_get_num(di);
  146. map = ipu_bus_format_to_map(bus_format);
  147. /*
  148. * In interlaced mode we need more counters to create the asymmetric
  149. * per-field VSYNC signals. The pixel active signal synchronising DC
  150. * to DI moves to signal generator #6 (see ipu-di.c). In progressive
  151. * mode counter #5 is used.
  152. */
  153. sync = interlaced ? 6 : 5;
  154. /* Reserve 5 microcode template words for each DI */
  155. if (dc->di)
  156. addr = 5;
  157. else
  158. addr = 0;
  159. if (interlaced) {
  160. dc_link_event(dc, DC_EVT_NL, addr, 3);
  161. dc_link_event(dc, DC_EVT_EOL, addr, 2);
  162. dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
  163. /* Init template microcode */
  164. dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
  165. } else {
  166. dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
  167. dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
  168. dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
  169. /* Init template microcode */
  170. dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
  171. dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
  172. dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
  173. dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
  174. }
  175. dc_link_event(dc, DC_EVT_NF, 0, 0);
  176. dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
  177. dc_link_event(dc, DC_EVT_EOF, 0, 0);
  178. dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
  179. dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
  180. dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
  181. reg = readl(dc->base + DC_WR_CH_CONF);
  182. if (interlaced)
  183. reg |= DC_WR_CH_CONF_FIELD_MODE;
  184. else
  185. reg &= ~DC_WR_CH_CONF_FIELD_MODE;
  186. writel(reg, dc->base + DC_WR_CH_CONF);
  187. writel(0x0, dc->base + DC_WR_CH_ADDR);
  188. writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
  189. return 0;
  190. }
  191. EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
  192. void ipu_dc_enable(struct ipu_soc *ipu)
  193. {
  194. struct ipu_dc_priv *priv = ipu->dc_priv;
  195. mutex_lock(&priv->mutex);
  196. if (!priv->use_count)
  197. ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
  198. priv->use_count++;
  199. mutex_unlock(&priv->mutex);
  200. }
  201. EXPORT_SYMBOL_GPL(ipu_dc_enable);
  202. void ipu_dc_enable_channel(struct ipu_dc *dc)
  203. {
  204. u32 reg;
  205. reg = readl(dc->base + DC_WR_CH_CONF);
  206. reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
  207. writel(reg, dc->base + DC_WR_CH_CONF);
  208. }
  209. EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
  210. void ipu_dc_disable_channel(struct ipu_dc *dc)
  211. {
  212. u32 val;
  213. val = readl(dc->base + DC_WR_CH_CONF);
  214. val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
  215. writel(val, dc->base + DC_WR_CH_CONF);
  216. }
  217. EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
  218. void ipu_dc_disable(struct ipu_soc *ipu)
  219. {
  220. struct ipu_dc_priv *priv = ipu->dc_priv;
  221. mutex_lock(&priv->mutex);
  222. priv->use_count--;
  223. if (!priv->use_count)
  224. ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
  225. if (priv->use_count < 0)
  226. priv->use_count = 0;
  227. mutex_unlock(&priv->mutex);
  228. }
  229. EXPORT_SYMBOL_GPL(ipu_dc_disable);
  230. static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
  231. int byte_num, int offset, int mask)
  232. {
  233. int ptr = map * 3 + byte_num;
  234. u32 reg;
  235. reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
  236. reg &= ~(0xffff << (16 * (ptr & 0x1)));
  237. reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
  238. writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
  239. reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
  240. reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
  241. reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
  242. writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
  243. }
  244. static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
  245. {
  246. u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
  247. writel(reg & ~(0xffff << (16 * (map & 0x1))),
  248. priv->dc_reg + DC_MAP_CONF_PTR(map));
  249. }
  250. struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
  251. {
  252. struct ipu_dc_priv *priv = ipu->dc_priv;
  253. struct ipu_dc *dc;
  254. if (channel >= IPU_DC_NUM_CHANNELS)
  255. return ERR_PTR(-ENODEV);
  256. dc = &priv->channels[channel];
  257. mutex_lock(&priv->mutex);
  258. if (dc->in_use) {
  259. mutex_unlock(&priv->mutex);
  260. return ERR_PTR(-EBUSY);
  261. }
  262. dc->in_use = true;
  263. mutex_unlock(&priv->mutex);
  264. return dc;
  265. }
  266. EXPORT_SYMBOL_GPL(ipu_dc_get);
  267. void ipu_dc_put(struct ipu_dc *dc)
  268. {
  269. struct ipu_dc_priv *priv = dc->priv;
  270. mutex_lock(&priv->mutex);
  271. dc->in_use = false;
  272. mutex_unlock(&priv->mutex);
  273. }
  274. EXPORT_SYMBOL_GPL(ipu_dc_put);
  275. int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
  276. unsigned long base, unsigned long template_base)
  277. {
  278. struct ipu_dc_priv *priv;
  279. static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
  280. 0x78, 0, 0x94, 0xb4};
  281. int i;
  282. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  283. if (!priv)
  284. return -ENOMEM;
  285. mutex_init(&priv->mutex);
  286. priv->dev = dev;
  287. priv->ipu = ipu;
  288. priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
  289. priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
  290. if (!priv->dc_reg || !priv->dc_tmpl_reg)
  291. return -ENOMEM;
  292. for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
  293. priv->channels[i].chno = i;
  294. priv->channels[i].priv = priv;
  295. priv->channels[i].base = priv->dc_reg + channel_offsets[i];
  296. }
  297. writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
  298. DC_WR_CH_CONF_PROG_DI_ID,
  299. priv->channels[1].base + DC_WR_CH_CONF);
  300. writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
  301. priv->channels[5].base + DC_WR_CH_CONF);
  302. writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
  303. priv->dc_reg + DC_GEN);
  304. ipu->dc_priv = priv;
  305. dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
  306. base, template_base);
  307. /* rgb24 */
  308. ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
  309. ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
  310. ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
  311. ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
  312. /* rgb565 */
  313. ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
  314. ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
  315. ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
  316. ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
  317. /* gbr24 */
  318. ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
  319. ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
  320. ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
  321. ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
  322. /* bgr666 */
  323. ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
  324. ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
  325. ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
  326. ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
  327. /* lvds666 */
  328. ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
  329. ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
  330. ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
  331. ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
  332. /* bgr24 */
  333. ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
  334. ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
  335. ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
  336. ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
  337. return 0;
  338. }
  339. void ipu_dc_exit(struct ipu_soc *ipu)
  340. {
  341. }