ipu-csi.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2012-2014 Mentor Graphics Inc.
  4. * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
  5. */
  6. #include <linux/export.h>
  7. #include <linux/module.h>
  8. #include <linux/types.h>
  9. #include <linux/errno.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/videodev2.h>
  15. #include <uapi/linux/v4l2-mediabus.h>
  16. #include <linux/clk.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/clkdev.h>
  19. #include "ipu-prv.h"
  20. struct ipu_csi {
  21. void __iomem *base;
  22. int id;
  23. u32 module;
  24. struct clk *clk_ipu; /* IPU bus clock */
  25. spinlock_t lock;
  26. bool inuse;
  27. struct ipu_soc *ipu;
  28. };
  29. /* CSI Register Offsets */
  30. #define CSI_SENS_CONF 0x0000
  31. #define CSI_SENS_FRM_SIZE 0x0004
  32. #define CSI_ACT_FRM_SIZE 0x0008
  33. #define CSI_OUT_FRM_CTRL 0x000c
  34. #define CSI_TST_CTRL 0x0010
  35. #define CSI_CCIR_CODE_1 0x0014
  36. #define CSI_CCIR_CODE_2 0x0018
  37. #define CSI_CCIR_CODE_3 0x001c
  38. #define CSI_MIPI_DI 0x0020
  39. #define CSI_SKIP 0x0024
  40. #define CSI_CPD_CTRL 0x0028
  41. #define CSI_CPD_RC(n) (0x002c + ((n)*4))
  42. #define CSI_CPD_RS(n) (0x004c + ((n)*4))
  43. #define CSI_CPD_GRC(n) (0x005c + ((n)*4))
  44. #define CSI_CPD_GRS(n) (0x007c + ((n)*4))
  45. #define CSI_CPD_GBC(n) (0x008c + ((n)*4))
  46. #define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
  47. #define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
  48. #define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
  49. #define CSI_CPD_OFFSET1 0x00ec
  50. #define CSI_CPD_OFFSET2 0x00f0
  51. /* CSI Register Fields */
  52. #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
  53. #define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
  54. #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
  55. #define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
  56. #define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
  57. #define CSI_SENS_CONF_DATA_FMT_BAYER 3L
  58. #define CSI_SENS_CONF_DATA_FMT_RGB565 4L
  59. #define CSI_SENS_CONF_DATA_FMT_RGB555 5L
  60. #define CSI_SENS_CONF_DATA_FMT_RGB444 6L
  61. #define CSI_SENS_CONF_DATA_FMT_JPEG 7L
  62. #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
  63. #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
  64. #define CSI_SENS_CONF_DATA_POL_SHIFT 2
  65. #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
  66. #define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
  67. #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
  68. #define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
  69. #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
  70. #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
  71. #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
  72. #define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
  73. #define CSI_SENS_CONF_DATA_DEST_SHIFT 24
  74. #define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
  75. #define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
  76. #define CSI_SENS_CONF_JPEG_EN_SHIFT 28
  77. #define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
  78. #define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
  79. #define CSI_DATA_DEST_IC 2
  80. #define CSI_DATA_DEST_IDMAC 4
  81. #define CSI_CCIR_ERR_DET_EN 0x01000000
  82. #define CSI_HORI_DOWNSIZE_EN 0x80000000
  83. #define CSI_VERT_DOWNSIZE_EN 0x40000000
  84. #define CSI_TEST_GEN_MODE_EN 0x01000000
  85. #define CSI_HSC_MASK 0x1fff0000
  86. #define CSI_HSC_SHIFT 16
  87. #define CSI_VSC_MASK 0x00000fff
  88. #define CSI_VSC_SHIFT 0
  89. #define CSI_TEST_GEN_R_MASK 0x000000ff
  90. #define CSI_TEST_GEN_R_SHIFT 0
  91. #define CSI_TEST_GEN_G_MASK 0x0000ff00
  92. #define CSI_TEST_GEN_G_SHIFT 8
  93. #define CSI_TEST_GEN_B_MASK 0x00ff0000
  94. #define CSI_TEST_GEN_B_SHIFT 16
  95. #define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
  96. #define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
  97. #define CSI_SKIP_SMFC_MASK 0x000000f8
  98. #define CSI_SKIP_SMFC_SHIFT 3
  99. #define CSI_ID_2_SKIP_MASK 0x00000300
  100. #define CSI_ID_2_SKIP_SHIFT 8
  101. #define CSI_COLOR_FIRST_ROW_MASK 0x00000002
  102. #define CSI_COLOR_FIRST_COMP_MASK 0x00000001
  103. /* MIPI CSI-2 data types */
  104. #define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
  105. #define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
  106. #define MIPI_DT_YUV422 0x1e /* UYVY... */
  107. #define MIPI_DT_RGB444 0x20
  108. #define MIPI_DT_RGB555 0x21
  109. #define MIPI_DT_RGB565 0x22
  110. #define MIPI_DT_RGB666 0x23
  111. #define MIPI_DT_RGB888 0x24
  112. #define MIPI_DT_RAW6 0x28
  113. #define MIPI_DT_RAW7 0x29
  114. #define MIPI_DT_RAW8 0x2a
  115. #define MIPI_DT_RAW10 0x2b
  116. #define MIPI_DT_RAW12 0x2c
  117. #define MIPI_DT_RAW14 0x2d
  118. /*
  119. * Bitfield of CSI bus signal polarities and modes.
  120. */
  121. struct ipu_csi_bus_config {
  122. unsigned data_width:4;
  123. unsigned clk_mode:3;
  124. unsigned ext_vsync:1;
  125. unsigned vsync_pol:1;
  126. unsigned hsync_pol:1;
  127. unsigned pixclk_pol:1;
  128. unsigned data_pol:1;
  129. unsigned sens_clksrc:1;
  130. unsigned pack_tight:1;
  131. unsigned force_eof:1;
  132. unsigned data_en_pol:1;
  133. unsigned data_fmt;
  134. unsigned mipi_dt;
  135. };
  136. /*
  137. * Enumeration of CSI data bus widths.
  138. */
  139. enum ipu_csi_data_width {
  140. IPU_CSI_DATA_WIDTH_4 = 0,
  141. IPU_CSI_DATA_WIDTH_8 = 1,
  142. IPU_CSI_DATA_WIDTH_10 = 3,
  143. IPU_CSI_DATA_WIDTH_12 = 5,
  144. IPU_CSI_DATA_WIDTH_16 = 9,
  145. };
  146. /*
  147. * Enumeration of CSI clock modes.
  148. */
  149. enum ipu_csi_clk_mode {
  150. IPU_CSI_CLK_MODE_GATED_CLK,
  151. IPU_CSI_CLK_MODE_NONGATED_CLK,
  152. IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
  153. IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
  154. IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
  155. IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
  156. IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
  157. IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
  158. };
  159. static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
  160. {
  161. return readl(csi->base + offset);
  162. }
  163. static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
  164. unsigned offset)
  165. {
  166. writel(value, csi->base + offset);
  167. }
  168. /*
  169. * Set mclk division ratio for generating test mode mclk. Only used
  170. * for test generator.
  171. */
  172. static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
  173. u32 ipu_clk)
  174. {
  175. u32 temp;
  176. int div_ratio;
  177. div_ratio = (ipu_clk / pixel_clk) - 1;
  178. if (div_ratio > 0xFF || div_ratio < 0) {
  179. dev_err(csi->ipu->dev,
  180. "value of pixel_clk extends normal range\n");
  181. return -EINVAL;
  182. }
  183. temp = ipu_csi_read(csi, CSI_SENS_CONF);
  184. temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
  185. ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
  186. CSI_SENS_CONF);
  187. return 0;
  188. }
  189. /*
  190. * Find the CSI data format and data width for the given V4L2 media
  191. * bus pixel format code.
  192. */
  193. static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code,
  194. enum v4l2_mbus_type mbus_type)
  195. {
  196. switch (mbus_code) {
  197. case MEDIA_BUS_FMT_BGR565_2X8_BE:
  198. case MEDIA_BUS_FMT_BGR565_2X8_LE:
  199. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  200. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  201. if (mbus_type == V4L2_MBUS_CSI2_DPHY)
  202. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
  203. else
  204. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
  205. cfg->mipi_dt = MIPI_DT_RGB565;
  206. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  207. break;
  208. case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
  209. case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
  210. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
  211. cfg->mipi_dt = MIPI_DT_RGB444;
  212. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  213. break;
  214. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
  215. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  216. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
  217. cfg->mipi_dt = MIPI_DT_RGB555;
  218. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  219. break;
  220. case MEDIA_BUS_FMT_RGB888_1X24:
  221. case MEDIA_BUS_FMT_BGR888_1X24:
  222. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
  223. cfg->mipi_dt = MIPI_DT_RGB888;
  224. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  225. break;
  226. case MEDIA_BUS_FMT_UYVY8_2X8:
  227. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
  228. cfg->mipi_dt = MIPI_DT_YUV422;
  229. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  230. break;
  231. case MEDIA_BUS_FMT_YUYV8_2X8:
  232. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
  233. cfg->mipi_dt = MIPI_DT_YUV422;
  234. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  235. break;
  236. case MEDIA_BUS_FMT_UYVY8_1X16:
  237. case MEDIA_BUS_FMT_YUYV8_1X16:
  238. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
  239. cfg->mipi_dt = MIPI_DT_YUV422;
  240. cfg->data_width = IPU_CSI_DATA_WIDTH_16;
  241. break;
  242. case MEDIA_BUS_FMT_SBGGR8_1X8:
  243. case MEDIA_BUS_FMT_SGBRG8_1X8:
  244. case MEDIA_BUS_FMT_SGRBG8_1X8:
  245. case MEDIA_BUS_FMT_SRGGB8_1X8:
  246. case MEDIA_BUS_FMT_Y8_1X8:
  247. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
  248. cfg->mipi_dt = MIPI_DT_RAW8;
  249. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  250. break;
  251. case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
  252. case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
  253. case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
  254. case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
  255. case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
  256. case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
  257. case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
  258. case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
  259. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
  260. cfg->mipi_dt = MIPI_DT_RAW10;
  261. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  262. break;
  263. case MEDIA_BUS_FMT_SBGGR10_1X10:
  264. case MEDIA_BUS_FMT_SGBRG10_1X10:
  265. case MEDIA_BUS_FMT_SGRBG10_1X10:
  266. case MEDIA_BUS_FMT_SRGGB10_1X10:
  267. case MEDIA_BUS_FMT_Y10_1X10:
  268. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
  269. cfg->mipi_dt = MIPI_DT_RAW10;
  270. cfg->data_width = IPU_CSI_DATA_WIDTH_10;
  271. break;
  272. case MEDIA_BUS_FMT_SBGGR12_1X12:
  273. case MEDIA_BUS_FMT_SGBRG12_1X12:
  274. case MEDIA_BUS_FMT_SGRBG12_1X12:
  275. case MEDIA_BUS_FMT_SRGGB12_1X12:
  276. case MEDIA_BUS_FMT_Y12_1X12:
  277. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
  278. cfg->mipi_dt = MIPI_DT_RAW12;
  279. cfg->data_width = IPU_CSI_DATA_WIDTH_12;
  280. break;
  281. case MEDIA_BUS_FMT_JPEG_1X8:
  282. /* TODO */
  283. cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
  284. cfg->mipi_dt = MIPI_DT_RAW8;
  285. cfg->data_width = IPU_CSI_DATA_WIDTH_8;
  286. break;
  287. default:
  288. return -EINVAL;
  289. }
  290. return 0;
  291. }
  292. /* translate alternate field mode based on given standard */
  293. static inline enum v4l2_field
  294. ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std)
  295. {
  296. return (field != V4L2_FIELD_ALTERNATE) ? field :
  297. ((std & V4L2_STD_525_60) ?
  298. V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB);
  299. }
  300. /*
  301. * Fill a CSI bus config struct from mbus_config and mbus_framefmt.
  302. */
  303. static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
  304. const struct v4l2_mbus_config *mbus_cfg,
  305. const struct v4l2_mbus_framefmt *mbus_fmt)
  306. {
  307. int ret;
  308. memset(csicfg, 0, sizeof(*csicfg));
  309. ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code, mbus_cfg->type);
  310. if (ret < 0)
  311. return ret;
  312. switch (mbus_cfg->type) {
  313. case V4L2_MBUS_PARALLEL:
  314. csicfg->ext_vsync = 1;
  315. csicfg->vsync_pol = (mbus_cfg->flags &
  316. V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
  317. csicfg->hsync_pol = (mbus_cfg->flags &
  318. V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
  319. csicfg->pixclk_pol = (mbus_cfg->flags &
  320. V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
  321. csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
  322. break;
  323. case V4L2_MBUS_BT656:
  324. csicfg->ext_vsync = 0;
  325. if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) ||
  326. mbus_fmt->field == V4L2_FIELD_ALTERNATE)
  327. csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
  328. else
  329. csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
  330. break;
  331. case V4L2_MBUS_CSI2_DPHY:
  332. /*
  333. * MIPI CSI-2 requires non gated clock mode, all other
  334. * parameters are not applicable for MIPI CSI-2 bus.
  335. */
  336. csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
  337. break;
  338. default:
  339. /* will never get here, keep compiler quiet */
  340. break;
  341. }
  342. return 0;
  343. }
  344. static int
  345. ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi,
  346. const struct v4l2_mbus_framefmt *infmt,
  347. const struct v4l2_mbus_framefmt *outfmt,
  348. v4l2_std_id std)
  349. {
  350. enum v4l2_field infield, outfield;
  351. bool swap_fields;
  352. /* get translated field type of input and output */
  353. infield = ipu_csi_translate_field(infmt->field, std);
  354. outfield = ipu_csi_translate_field(outfmt->field, std);
  355. /*
  356. * Write the H-V-F codes the CSI will match against the
  357. * incoming data for start/end of active and blanking
  358. * field intervals. If input and output field types are
  359. * sequential but not the same (one is SEQ_BT and the other
  360. * is SEQ_TB), swap the F-bit so that the CSI will capture
  361. * field 1 lines before field 0 lines.
  362. */
  363. swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) &&
  364. V4L2_FIELD_IS_SEQUENTIAL(outfield) &&
  365. infield != outfield);
  366. if (!swap_fields) {
  367. /*
  368. * Field0BlankEnd = 110, Field0BlankStart = 010
  369. * Field0ActiveEnd = 100, Field0ActiveStart = 000
  370. * Field1BlankEnd = 111, Field1BlankStart = 011
  371. * Field1ActiveEnd = 101, Field1ActiveStart = 001
  372. */
  373. ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
  374. CSI_CCIR_CODE_1);
  375. ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
  376. } else {
  377. dev_dbg(csi->ipu->dev, "capture field swap\n");
  378. /* same as above but with F-bit inverted */
  379. ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
  380. CSI_CCIR_CODE_1);
  381. ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
  382. }
  383. ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
  384. return 0;
  385. }
  386. int ipu_csi_init_interface(struct ipu_csi *csi,
  387. const struct v4l2_mbus_config *mbus_cfg,
  388. const struct v4l2_mbus_framefmt *infmt,
  389. const struct v4l2_mbus_framefmt *outfmt)
  390. {
  391. struct ipu_csi_bus_config cfg;
  392. unsigned long flags;
  393. u32 width, height, data = 0;
  394. v4l2_std_id std;
  395. int ret;
  396. ret = fill_csi_bus_cfg(&cfg, mbus_cfg, infmt);
  397. if (ret < 0)
  398. return ret;
  399. /* set default sensor frame width and height */
  400. width = infmt->width;
  401. height = infmt->height;
  402. if (infmt->field == V4L2_FIELD_ALTERNATE)
  403. height *= 2;
  404. /* Set the CSI_SENS_CONF register remaining fields */
  405. data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
  406. cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
  407. cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
  408. cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
  409. cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
  410. cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
  411. cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
  412. cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
  413. cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
  414. cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
  415. cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
  416. spin_lock_irqsave(&csi->lock, flags);
  417. ipu_csi_write(csi, data, CSI_SENS_CONF);
  418. /* Set CCIR registers */
  419. switch (cfg.clk_mode) {
  420. case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
  421. ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
  422. ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
  423. break;
  424. case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
  425. if (width == 720 && height == 480) {
  426. std = V4L2_STD_NTSC;
  427. height = 525;
  428. } else if (width == 720 && height == 576) {
  429. std = V4L2_STD_PAL;
  430. height = 625;
  431. } else {
  432. dev_err(csi->ipu->dev,
  433. "Unsupported interlaced video mode\n");
  434. ret = -EINVAL;
  435. goto out_unlock;
  436. }
  437. ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std);
  438. if (ret)
  439. goto out_unlock;
  440. break;
  441. case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
  442. case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
  443. case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
  444. case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
  445. ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
  446. CSI_CCIR_CODE_1);
  447. ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
  448. break;
  449. case IPU_CSI_CLK_MODE_GATED_CLK:
  450. case IPU_CSI_CLK_MODE_NONGATED_CLK:
  451. ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
  452. break;
  453. }
  454. /* Setup sensor frame size */
  455. ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
  456. CSI_SENS_FRM_SIZE);
  457. dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
  458. ipu_csi_read(csi, CSI_SENS_CONF));
  459. dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
  460. ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
  461. out_unlock:
  462. spin_unlock_irqrestore(&csi->lock, flags);
  463. return ret;
  464. }
  465. EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
  466. bool ipu_csi_is_interlaced(struct ipu_csi *csi)
  467. {
  468. unsigned long flags;
  469. u32 sensor_protocol;
  470. spin_lock_irqsave(&csi->lock, flags);
  471. sensor_protocol =
  472. (ipu_csi_read(csi, CSI_SENS_CONF) &
  473. CSI_SENS_CONF_SENS_PRTCL_MASK) >>
  474. CSI_SENS_CONF_SENS_PRTCL_SHIFT;
  475. spin_unlock_irqrestore(&csi->lock, flags);
  476. switch (sensor_protocol) {
  477. case IPU_CSI_CLK_MODE_GATED_CLK:
  478. case IPU_CSI_CLK_MODE_NONGATED_CLK:
  479. case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
  480. case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
  481. case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
  482. return false;
  483. case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
  484. case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
  485. case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
  486. return true;
  487. default:
  488. dev_err(csi->ipu->dev,
  489. "CSI %d sensor protocol unsupported\n", csi->id);
  490. return false;
  491. }
  492. }
  493. EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
  494. void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
  495. {
  496. unsigned long flags;
  497. u32 reg;
  498. spin_lock_irqsave(&csi->lock, flags);
  499. reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
  500. w->width = (reg & 0xFFFF) + 1;
  501. w->height = (reg >> 16 & 0xFFFF) + 1;
  502. reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
  503. w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
  504. w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
  505. spin_unlock_irqrestore(&csi->lock, flags);
  506. }
  507. EXPORT_SYMBOL_GPL(ipu_csi_get_window);
  508. void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
  509. {
  510. unsigned long flags;
  511. u32 reg;
  512. spin_lock_irqsave(&csi->lock, flags);
  513. ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
  514. CSI_ACT_FRM_SIZE);
  515. reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
  516. reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
  517. reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
  518. ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
  519. spin_unlock_irqrestore(&csi->lock, flags);
  520. }
  521. EXPORT_SYMBOL_GPL(ipu_csi_set_window);
  522. void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
  523. {
  524. unsigned long flags;
  525. u32 reg;
  526. spin_lock_irqsave(&csi->lock, flags);
  527. reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
  528. reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN);
  529. reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) |
  530. (vert ? CSI_VERT_DOWNSIZE_EN : 0);
  531. ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
  532. spin_unlock_irqrestore(&csi->lock, flags);
  533. }
  534. EXPORT_SYMBOL_GPL(ipu_csi_set_downsize);
  535. void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
  536. u32 r_value, u32 g_value, u32 b_value,
  537. u32 pix_clk)
  538. {
  539. unsigned long flags;
  540. u32 ipu_clk = clk_get_rate(csi->clk_ipu);
  541. u32 temp;
  542. spin_lock_irqsave(&csi->lock, flags);
  543. temp = ipu_csi_read(csi, CSI_TST_CTRL);
  544. if (!active) {
  545. temp &= ~CSI_TEST_GEN_MODE_EN;
  546. ipu_csi_write(csi, temp, CSI_TST_CTRL);
  547. } else {
  548. /* Set sensb_mclk div_ratio */
  549. ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
  550. temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
  551. CSI_TEST_GEN_B_MASK);
  552. temp |= CSI_TEST_GEN_MODE_EN;
  553. temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
  554. (g_value << CSI_TEST_GEN_G_SHIFT) |
  555. (b_value << CSI_TEST_GEN_B_SHIFT);
  556. ipu_csi_write(csi, temp, CSI_TST_CTRL);
  557. }
  558. spin_unlock_irqrestore(&csi->lock, flags);
  559. }
  560. EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
  561. int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
  562. struct v4l2_mbus_framefmt *mbus_fmt)
  563. {
  564. struct ipu_csi_bus_config cfg;
  565. unsigned long flags;
  566. u32 temp;
  567. int ret;
  568. if (vc > 3)
  569. return -EINVAL;
  570. ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code, V4L2_MBUS_CSI2_DPHY);
  571. if (ret < 0)
  572. return ret;
  573. spin_lock_irqsave(&csi->lock, flags);
  574. temp = ipu_csi_read(csi, CSI_MIPI_DI);
  575. temp &= ~(0xff << (vc * 8));
  576. temp |= (cfg.mipi_dt << (vc * 8));
  577. ipu_csi_write(csi, temp, CSI_MIPI_DI);
  578. spin_unlock_irqrestore(&csi->lock, flags);
  579. return 0;
  580. }
  581. EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
  582. int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
  583. u32 max_ratio, u32 id)
  584. {
  585. unsigned long flags;
  586. u32 temp;
  587. if (max_ratio > 5 || id > 3)
  588. return -EINVAL;
  589. spin_lock_irqsave(&csi->lock, flags);
  590. temp = ipu_csi_read(csi, CSI_SKIP);
  591. temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
  592. CSI_SKIP_SMFC_MASK);
  593. temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
  594. (id << CSI_ID_2_SKIP_SHIFT) |
  595. (skip << CSI_SKIP_SMFC_SHIFT);
  596. ipu_csi_write(csi, temp, CSI_SKIP);
  597. spin_unlock_irqrestore(&csi->lock, flags);
  598. return 0;
  599. }
  600. EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
  601. int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
  602. {
  603. unsigned long flags;
  604. u32 csi_sens_conf, dest;
  605. if (csi_dest == IPU_CSI_DEST_IDMAC)
  606. dest = CSI_DATA_DEST_IDMAC;
  607. else
  608. dest = CSI_DATA_DEST_IC; /* IC or VDIC */
  609. spin_lock_irqsave(&csi->lock, flags);
  610. csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
  611. csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
  612. csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
  613. ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
  614. spin_unlock_irqrestore(&csi->lock, flags);
  615. return 0;
  616. }
  617. EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
  618. int ipu_csi_enable(struct ipu_csi *csi)
  619. {
  620. ipu_module_enable(csi->ipu, csi->module);
  621. return 0;
  622. }
  623. EXPORT_SYMBOL_GPL(ipu_csi_enable);
  624. int ipu_csi_disable(struct ipu_csi *csi)
  625. {
  626. ipu_module_disable(csi->ipu, csi->module);
  627. return 0;
  628. }
  629. EXPORT_SYMBOL_GPL(ipu_csi_disable);
  630. struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
  631. {
  632. unsigned long flags;
  633. struct ipu_csi *csi, *ret;
  634. if (id > 1)
  635. return ERR_PTR(-EINVAL);
  636. csi = ipu->csi_priv[id];
  637. ret = csi;
  638. spin_lock_irqsave(&csi->lock, flags);
  639. if (csi->inuse) {
  640. ret = ERR_PTR(-EBUSY);
  641. goto unlock;
  642. }
  643. csi->inuse = true;
  644. unlock:
  645. spin_unlock_irqrestore(&csi->lock, flags);
  646. return ret;
  647. }
  648. EXPORT_SYMBOL_GPL(ipu_csi_get);
  649. void ipu_csi_put(struct ipu_csi *csi)
  650. {
  651. unsigned long flags;
  652. spin_lock_irqsave(&csi->lock, flags);
  653. csi->inuse = false;
  654. spin_unlock_irqrestore(&csi->lock, flags);
  655. }
  656. EXPORT_SYMBOL_GPL(ipu_csi_put);
  657. int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
  658. unsigned long base, u32 module, struct clk *clk_ipu)
  659. {
  660. struct ipu_csi *csi;
  661. if (id > 1)
  662. return -ENODEV;
  663. csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
  664. if (!csi)
  665. return -ENOMEM;
  666. ipu->csi_priv[id] = csi;
  667. spin_lock_init(&csi->lock);
  668. csi->module = module;
  669. csi->id = id;
  670. csi->clk_ipu = clk_ipu;
  671. csi->base = devm_ioremap(dev, base, PAGE_SIZE);
  672. if (!csi->base)
  673. return -ENOMEM;
  674. dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
  675. id, base, csi->base);
  676. csi->ipu = ipu;
  677. return 0;
  678. }
  679. void ipu_csi_exit(struct ipu_soc *ipu, int id)
  680. {
  681. }
  682. void ipu_csi_dump(struct ipu_csi *csi)
  683. {
  684. dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
  685. ipu_csi_read(csi, CSI_SENS_CONF));
  686. dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
  687. ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
  688. dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
  689. ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
  690. dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
  691. ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
  692. dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
  693. ipu_csi_read(csi, CSI_TST_CTRL));
  694. dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
  695. ipu_csi_read(csi, CSI_CCIR_CODE_1));
  696. dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
  697. ipu_csi_read(csi, CSI_CCIR_CODE_2));
  698. dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
  699. ipu_csi_read(csi, CSI_CCIR_CODE_3));
  700. dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
  701. ipu_csi_read(csi, CSI_MIPI_DI));
  702. dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
  703. ipu_csi_read(csi, CSI_SKIP));
  704. }
  705. EXPORT_SYMBOL_GPL(ipu_csi_dump);