ipu-cpmem.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2012 Mentor Graphics Inc.
  4. * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  5. */
  6. #include <linux/types.h>
  7. #include <linux/bitrev.h>
  8. #include <linux/io.h>
  9. #include <linux/sizes.h>
  10. #include <drm/drm_fourcc.h>
  11. #include "ipu-prv.h"
  12. struct ipu_cpmem_word {
  13. u32 data[5];
  14. u32 res[3];
  15. };
  16. struct ipu_ch_param {
  17. struct ipu_cpmem_word word[2];
  18. };
  19. struct ipu_cpmem {
  20. struct ipu_ch_param __iomem *base;
  21. u32 module;
  22. spinlock_t lock;
  23. int use_count;
  24. struct ipu_soc *ipu;
  25. };
  26. #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
  27. #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
  28. #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
  29. #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
  30. #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
  31. #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
  32. #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
  33. #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
  34. #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
  35. #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
  36. #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
  37. #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
  38. #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
  39. #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
  40. #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
  41. #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
  42. #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
  43. #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
  44. #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
  45. #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
  46. #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
  47. #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
  48. #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
  49. #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
  50. #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
  51. #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
  52. #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
  53. #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
  54. #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
  55. #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
  56. #define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3)
  57. #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
  58. #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
  59. #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
  60. #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
  61. #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
  62. #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
  63. #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
  64. #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
  65. #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
  66. #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
  67. #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
  68. #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
  69. #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
  70. #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
  71. #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
  72. #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
  73. #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
  74. #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
  75. #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
  76. #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
  77. #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
  78. #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
  79. #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
  80. #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
  81. #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
  82. #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
  83. #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
  84. #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
  85. static inline struct ipu_ch_param __iomem *
  86. ipu_get_cpmem(struct ipuv3_channel *ch)
  87. {
  88. struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;
  89. return cpmem->base + ch->num;
  90. }
  91. static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
  92. {
  93. struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
  94. u32 bit = (wbs >> 8) % 160;
  95. u32 size = wbs & 0xff;
  96. u32 word = (wbs >> 8) / 160;
  97. u32 i = bit / 32;
  98. u32 ofs = bit % 32;
  99. u32 mask = (1 << size) - 1;
  100. u32 val;
  101. pr_debug("%s %d %d %d\n", __func__, word, bit , size);
  102. val = readl(&base->word[word].data[i]);
  103. val &= ~(mask << ofs);
  104. val |= v << ofs;
  105. writel(val, &base->word[word].data[i]);
  106. if ((bit + size - 1) / 32 > i) {
  107. val = readl(&base->word[word].data[i + 1]);
  108. val &= ~(mask >> (ofs ? (32 - ofs) : 0));
  109. val |= v >> (ofs ? (32 - ofs) : 0);
  110. writel(val, &base->word[word].data[i + 1]);
  111. }
  112. }
  113. static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
  114. {
  115. struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
  116. u32 bit = (wbs >> 8) % 160;
  117. u32 size = wbs & 0xff;
  118. u32 word = (wbs >> 8) / 160;
  119. u32 i = bit / 32;
  120. u32 ofs = bit % 32;
  121. u32 mask = (1 << size) - 1;
  122. u32 val = 0;
  123. pr_debug("%s %d %d %d\n", __func__, word, bit , size);
  124. val = (readl(&base->word[word].data[i]) >> ofs) & mask;
  125. if ((bit + size - 1) / 32 > i) {
  126. u32 tmp;
  127. tmp = readl(&base->word[word].data[i + 1]);
  128. tmp &= mask >> (ofs ? (32 - ofs) : 0);
  129. val |= tmp << (ofs ? (32 - ofs) : 0);
  130. }
  131. return val;
  132. }
  133. /*
  134. * The V4L2 spec defines packed RGB formats in memory byte order, which from
  135. * point of view of the IPU corresponds to little-endian words with the first
  136. * component in the least significant bits.
  137. * The DRM pixel formats and IPU internal representation are ordered the other
  138. * way around, with the first named component ordered at the most significant
  139. * bits. Further, V4L2 formats are not well defined:
  140. * https://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
  141. * We choose the interpretation which matches GStreamer behavior.
  142. */
  143. static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
  144. {
  145. switch (pixelformat) {
  146. case V4L2_PIX_FMT_RGB565:
  147. /*
  148. * Here we choose the 'corrected' interpretation of RGBP, a
  149. * little-endian 16-bit word with the red component at the most
  150. * significant bits:
  151. * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
  152. */
  153. return DRM_FORMAT_RGB565;
  154. case V4L2_PIX_FMT_BGR24:
  155. /* B G R <=> [24:0] R:G:B */
  156. return DRM_FORMAT_RGB888;
  157. case V4L2_PIX_FMT_RGB24:
  158. /* R G B <=> [24:0] B:G:R */
  159. return DRM_FORMAT_BGR888;
  160. case V4L2_PIX_FMT_BGR32:
  161. /* B G R A <=> [32:0] A:B:G:R */
  162. return DRM_FORMAT_XRGB8888;
  163. case V4L2_PIX_FMT_RGB32:
  164. /* R G B A <=> [32:0] A:B:G:R */
  165. return DRM_FORMAT_XBGR8888;
  166. case V4L2_PIX_FMT_ABGR32:
  167. /* B G R A <=> [32:0] A:R:G:B */
  168. return DRM_FORMAT_ARGB8888;
  169. case V4L2_PIX_FMT_XBGR32:
  170. /* B G R X <=> [32:0] X:R:G:B */
  171. return DRM_FORMAT_XRGB8888;
  172. case V4L2_PIX_FMT_BGRA32:
  173. /* A B G R <=> [32:0] R:G:B:A */
  174. return DRM_FORMAT_RGBA8888;
  175. case V4L2_PIX_FMT_BGRX32:
  176. /* X B G R <=> [32:0] R:G:B:X */
  177. return DRM_FORMAT_RGBX8888;
  178. case V4L2_PIX_FMT_RGBA32:
  179. /* R G B A <=> [32:0] A:B:G:R */
  180. return DRM_FORMAT_ABGR8888;
  181. case V4L2_PIX_FMT_RGBX32:
  182. /* R G B X <=> [32:0] X:B:G:R */
  183. return DRM_FORMAT_XBGR8888;
  184. case V4L2_PIX_FMT_ARGB32:
  185. /* A R G B <=> [32:0] B:G:R:A */
  186. return DRM_FORMAT_BGRA8888;
  187. case V4L2_PIX_FMT_XRGB32:
  188. /* X R G B <=> [32:0] B:G:R:X */
  189. return DRM_FORMAT_BGRX8888;
  190. case V4L2_PIX_FMT_UYVY:
  191. return DRM_FORMAT_UYVY;
  192. case V4L2_PIX_FMT_YUYV:
  193. return DRM_FORMAT_YUYV;
  194. case V4L2_PIX_FMT_YUV420:
  195. return DRM_FORMAT_YUV420;
  196. case V4L2_PIX_FMT_YUV422P:
  197. return DRM_FORMAT_YUV422;
  198. case V4L2_PIX_FMT_YVU420:
  199. return DRM_FORMAT_YVU420;
  200. case V4L2_PIX_FMT_NV12:
  201. return DRM_FORMAT_NV12;
  202. case V4L2_PIX_FMT_NV16:
  203. return DRM_FORMAT_NV16;
  204. }
  205. return -EINVAL;
  206. }
  207. void ipu_cpmem_zero(struct ipuv3_channel *ch)
  208. {
  209. struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
  210. void __iomem *base = p;
  211. int i;
  212. for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
  213. writel(0, base + i * sizeof(u32));
  214. }
  215. EXPORT_SYMBOL_GPL(ipu_cpmem_zero);
  216. void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
  217. {
  218. ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
  219. ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
  220. }
  221. EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
  222. void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch)
  223. {
  224. ipu_ch_param_write_field(ch, IPU_FIELD_RDRW, 1);
  225. }
  226. EXPORT_SYMBOL_GPL(ipu_cpmem_skip_odd_chroma_rows);
  227. void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
  228. {
  229. ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
  230. }
  231. EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);
  232. void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
  233. {
  234. struct ipu_soc *ipu = ch->ipu;
  235. u32 val;
  236. if (ipu->ipu_type == IPUV3EX)
  237. ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);
  238. val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
  239. val |= 1 << (ch->num % 32);
  240. ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
  241. };
  242. EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
  243. void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
  244. {
  245. WARN_ON_ONCE(buf & 0x7);
  246. if (bufnum)
  247. ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
  248. else
  249. ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
  250. }
  251. EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
  252. void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off)
  253. {
  254. WARN_ON_ONCE((u_off & 0x7) || (v_off & 0x7));
  255. ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
  256. ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
  257. }
  258. EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
  259. void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
  260. u32 pixelformat)
  261. {
  262. u32 ilo, sly, sluv;
  263. if (stride < 0) {
  264. stride = -stride;
  265. ilo = 0x100000 - (stride / 8);
  266. } else {
  267. ilo = stride / 8;
  268. }
  269. sly = (stride * 2) - 1;
  270. switch (pixelformat) {
  271. case V4L2_PIX_FMT_YUV420:
  272. case V4L2_PIX_FMT_YVU420:
  273. sluv = stride / 2 - 1;
  274. break;
  275. case V4L2_PIX_FMT_NV12:
  276. sluv = stride - 1;
  277. break;
  278. case V4L2_PIX_FMT_YUV422P:
  279. sluv = stride - 1;
  280. break;
  281. case V4L2_PIX_FMT_NV16:
  282. sluv = stride * 2 - 1;
  283. break;
  284. default:
  285. sluv = 0;
  286. break;
  287. }
  288. ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
  289. ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo);
  290. ipu_ch_param_write_field(ch, IPU_FIELD_SLY, sly);
  291. if (sluv)
  292. ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, sluv);
  293. };
  294. EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
  295. void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
  296. {
  297. id &= 0x3;
  298. ipu_ch_param_write_field(ch, IPU_FIELD_ID, id);
  299. }
  300. EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);
  301. int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch)
  302. {
  303. return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1;
  304. }
  305. EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize);
  306. void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
  307. {
  308. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
  309. };
  310. EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);
  311. void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
  312. {
  313. ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
  314. }
  315. EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);
  316. void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
  317. enum ipu_rotate_mode rot)
  318. {
  319. u32 temp_rot = bitrev8(rot) >> 5;
  320. ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot);
  321. }
  322. EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation);
  323. int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
  324. const struct ipu_rgb *rgb)
  325. {
  326. int bpp = 0, npb = 0, ro, go, bo, to;
  327. ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
  328. go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
  329. bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
  330. to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
  331. ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
  332. ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
  333. ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
  334. ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
  335. ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
  336. ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);
  337. if (rgb->transp.length) {
  338. ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
  339. rgb->transp.length - 1);
  340. ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
  341. } else {
  342. ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
  343. ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
  344. rgb->bits_per_pixel);
  345. }
  346. switch (rgb->bits_per_pixel) {
  347. case 32:
  348. bpp = 0;
  349. npb = 15;
  350. break;
  351. case 24:
  352. bpp = 1;
  353. npb = 19;
  354. break;
  355. case 16:
  356. bpp = 3;
  357. npb = 31;
  358. break;
  359. case 8:
  360. bpp = 5;
  361. npb = 63;
  362. break;
  363. default:
  364. return -EINVAL;
  365. }
  366. ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
  367. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
  368. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */
  369. return 0;
  370. }
  371. EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
  372. int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
  373. {
  374. int bpp = 0, npb = 0;
  375. switch (width) {
  376. case 32:
  377. bpp = 0;
  378. npb = 15;
  379. break;
  380. case 24:
  381. bpp = 1;
  382. npb = 19;
  383. break;
  384. case 16:
  385. bpp = 3;
  386. npb = 31;
  387. break;
  388. case 8:
  389. bpp = 5;
  390. npb = 63;
  391. break;
  392. default:
  393. return -EINVAL;
  394. }
  395. ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
  396. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
  397. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */
  398. return 0;
  399. }
  400. EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
  401. void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
  402. {
  403. switch (pixel_format) {
  404. case V4L2_PIX_FMT_UYVY:
  405. ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
  406. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
  407. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
  408. break;
  409. case V4L2_PIX_FMT_YUYV:
  410. ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
  411. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
  412. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
  413. break;
  414. }
  415. }
  416. EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
  417. void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
  418. unsigned int uv_stride,
  419. unsigned int u_offset, unsigned int v_offset)
  420. {
  421. WARN_ON_ONCE((u_offset & 0x7) || (v_offset & 0x7));
  422. ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1);
  423. ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
  424. ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
  425. }
  426. EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
  427. static const struct ipu_rgb def_xrgb_32 = {
  428. .red = { .offset = 16, .length = 8, },
  429. .green = { .offset = 8, .length = 8, },
  430. .blue = { .offset = 0, .length = 8, },
  431. .transp = { .offset = 24, .length = 8, },
  432. .bits_per_pixel = 32,
  433. };
  434. static const struct ipu_rgb def_xbgr_32 = {
  435. .red = { .offset = 0, .length = 8, },
  436. .green = { .offset = 8, .length = 8, },
  437. .blue = { .offset = 16, .length = 8, },
  438. .transp = { .offset = 24, .length = 8, },
  439. .bits_per_pixel = 32,
  440. };
  441. static const struct ipu_rgb def_rgbx_32 = {
  442. .red = { .offset = 24, .length = 8, },
  443. .green = { .offset = 16, .length = 8, },
  444. .blue = { .offset = 8, .length = 8, },
  445. .transp = { .offset = 0, .length = 8, },
  446. .bits_per_pixel = 32,
  447. };
  448. static const struct ipu_rgb def_bgrx_32 = {
  449. .red = { .offset = 8, .length = 8, },
  450. .green = { .offset = 16, .length = 8, },
  451. .blue = { .offset = 24, .length = 8, },
  452. .transp = { .offset = 0, .length = 8, },
  453. .bits_per_pixel = 32,
  454. };
  455. static const struct ipu_rgb def_rgb_24 = {
  456. .red = { .offset = 16, .length = 8, },
  457. .green = { .offset = 8, .length = 8, },
  458. .blue = { .offset = 0, .length = 8, },
  459. .transp = { .offset = 0, .length = 0, },
  460. .bits_per_pixel = 24,
  461. };
  462. static const struct ipu_rgb def_bgr_24 = {
  463. .red = { .offset = 0, .length = 8, },
  464. .green = { .offset = 8, .length = 8, },
  465. .blue = { .offset = 16, .length = 8, },
  466. .transp = { .offset = 0, .length = 0, },
  467. .bits_per_pixel = 24,
  468. };
  469. static const struct ipu_rgb def_rgb_16 = {
  470. .red = { .offset = 11, .length = 5, },
  471. .green = { .offset = 5, .length = 6, },
  472. .blue = { .offset = 0, .length = 5, },
  473. .transp = { .offset = 0, .length = 0, },
  474. .bits_per_pixel = 16,
  475. };
  476. static const struct ipu_rgb def_bgr_16 = {
  477. .red = { .offset = 0, .length = 5, },
  478. .green = { .offset = 5, .length = 6, },
  479. .blue = { .offset = 11, .length = 5, },
  480. .transp = { .offset = 0, .length = 0, },
  481. .bits_per_pixel = 16,
  482. };
  483. static const struct ipu_rgb def_argb_16 = {
  484. .red = { .offset = 10, .length = 5, },
  485. .green = { .offset = 5, .length = 5, },
  486. .blue = { .offset = 0, .length = 5, },
  487. .transp = { .offset = 15, .length = 1, },
  488. .bits_per_pixel = 16,
  489. };
  490. static const struct ipu_rgb def_argb_16_4444 = {
  491. .red = { .offset = 8, .length = 4, },
  492. .green = { .offset = 4, .length = 4, },
  493. .blue = { .offset = 0, .length = 4, },
  494. .transp = { .offset = 12, .length = 4, },
  495. .bits_per_pixel = 16,
  496. };
  497. static const struct ipu_rgb def_abgr_16 = {
  498. .red = { .offset = 0, .length = 5, },
  499. .green = { .offset = 5, .length = 5, },
  500. .blue = { .offset = 10, .length = 5, },
  501. .transp = { .offset = 15, .length = 1, },
  502. .bits_per_pixel = 16,
  503. };
  504. static const struct ipu_rgb def_rgba_16 = {
  505. .red = { .offset = 11, .length = 5, },
  506. .green = { .offset = 6, .length = 5, },
  507. .blue = { .offset = 1, .length = 5, },
  508. .transp = { .offset = 0, .length = 1, },
  509. .bits_per_pixel = 16,
  510. };
  511. static const struct ipu_rgb def_bgra_16 = {
  512. .red = { .offset = 1, .length = 5, },
  513. .green = { .offset = 6, .length = 5, },
  514. .blue = { .offset = 11, .length = 5, },
  515. .transp = { .offset = 0, .length = 1, },
  516. .bits_per_pixel = 16,
  517. };
  518. #define Y_OFFSET(pix, x, y) ((x) + pix->bytesperline * (y))
  519. #define U_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \
  520. (pix->bytesperline * ((y) / 2) / 2) + (x) / 2)
  521. #define V_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \
  522. (pix->bytesperline * pix->height / 4) + \
  523. (pix->bytesperline * ((y) / 2) / 2) + (x) / 2)
  524. #define U2_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \
  525. (pix->bytesperline * (y) / 2) + (x) / 2)
  526. #define V2_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \
  527. (pix->bytesperline * pix->height / 2) + \
  528. (pix->bytesperline * (y) / 2) + (x) / 2)
  529. #define UV_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \
  530. (pix->bytesperline * ((y) / 2)) + (x))
  531. #define UV2_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \
  532. (pix->bytesperline * y) + (x))
  533. #define NUM_ALPHA_CHANNELS 7
  534. /* See Table 37-12. Alpha channels mapping. */
  535. static int ipu_channel_albm(int ch_num)
  536. {
  537. switch (ch_num) {
  538. case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: return 0;
  539. case IPUV3_CHANNEL_G_MEM_IC_PP: return 1;
  540. case IPUV3_CHANNEL_MEM_FG_SYNC: return 2;
  541. case IPUV3_CHANNEL_MEM_FG_ASYNC: return 3;
  542. case IPUV3_CHANNEL_MEM_BG_SYNC: return 4;
  543. case IPUV3_CHANNEL_MEM_BG_ASYNC: return 5;
  544. case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: return 6;
  545. default:
  546. return -EINVAL;
  547. }
  548. }
  549. static void ipu_cpmem_set_separate_alpha(struct ipuv3_channel *ch)
  550. {
  551. struct ipu_soc *ipu = ch->ipu;
  552. int albm;
  553. u32 val;
  554. albm = ipu_channel_albm(ch->num);
  555. if (albm < 0)
  556. return;
  557. ipu_ch_param_write_field(ch, IPU_FIELD_ALU, 1);
  558. ipu_ch_param_write_field(ch, IPU_FIELD_ALBM, albm);
  559. ipu_ch_param_write_field(ch, IPU_FIELD_CRE, 1);
  560. val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
  561. val |= BIT(ch->num);
  562. ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA);
  563. }
  564. int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
  565. {
  566. switch (drm_fourcc) {
  567. case DRM_FORMAT_YUV420:
  568. case DRM_FORMAT_YVU420:
  569. /* pix format */
  570. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
  571. /* burst size */
  572. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  573. break;
  574. case DRM_FORMAT_YUV422:
  575. case DRM_FORMAT_YVU422:
  576. /* pix format */
  577. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1);
  578. /* burst size */
  579. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  580. break;
  581. case DRM_FORMAT_YUV444:
  582. case DRM_FORMAT_YVU444:
  583. /* pix format */
  584. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0);
  585. /* burst size */
  586. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  587. break;
  588. case DRM_FORMAT_NV12:
  589. /* pix format */
  590. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4);
  591. /* burst size */
  592. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  593. break;
  594. case DRM_FORMAT_NV16:
  595. /* pix format */
  596. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3);
  597. /* burst size */
  598. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  599. break;
  600. case DRM_FORMAT_UYVY:
  601. /* bits/pixel */
  602. ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
  603. /* pix format */
  604. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
  605. /* burst size */
  606. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  607. break;
  608. case DRM_FORMAT_YUYV:
  609. /* bits/pixel */
  610. ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
  611. /* pix format */
  612. ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
  613. /* burst size */
  614. ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
  615. break;
  616. case DRM_FORMAT_ABGR8888:
  617. case DRM_FORMAT_XBGR8888:
  618. ipu_cpmem_set_format_rgb(ch, &def_xbgr_32);
  619. break;
  620. case DRM_FORMAT_ARGB8888:
  621. case DRM_FORMAT_XRGB8888:
  622. ipu_cpmem_set_format_rgb(ch, &def_xrgb_32);
  623. break;
  624. case DRM_FORMAT_RGBA8888:
  625. case DRM_FORMAT_RGBX8888:
  626. case DRM_FORMAT_RGBX8888_A8:
  627. ipu_cpmem_set_format_rgb(ch, &def_rgbx_32);
  628. break;
  629. case DRM_FORMAT_BGRA8888:
  630. case DRM_FORMAT_BGRX8888:
  631. case DRM_FORMAT_BGRX8888_A8:
  632. ipu_cpmem_set_format_rgb(ch, &def_bgrx_32);
  633. break;
  634. case DRM_FORMAT_BGR888:
  635. case DRM_FORMAT_BGR888_A8:
  636. ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
  637. break;
  638. case DRM_FORMAT_RGB888:
  639. case DRM_FORMAT_RGB888_A8:
  640. ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
  641. break;
  642. case DRM_FORMAT_RGB565:
  643. case DRM_FORMAT_RGB565_A8:
  644. ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
  645. break;
  646. case DRM_FORMAT_BGR565:
  647. case DRM_FORMAT_BGR565_A8:
  648. ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
  649. break;
  650. case DRM_FORMAT_ARGB1555:
  651. ipu_cpmem_set_format_rgb(ch, &def_argb_16);
  652. break;
  653. case DRM_FORMAT_ABGR1555:
  654. ipu_cpmem_set_format_rgb(ch, &def_abgr_16);
  655. break;
  656. case DRM_FORMAT_RGBA5551:
  657. ipu_cpmem_set_format_rgb(ch, &def_rgba_16);
  658. break;
  659. case DRM_FORMAT_BGRA5551:
  660. ipu_cpmem_set_format_rgb(ch, &def_bgra_16);
  661. break;
  662. case DRM_FORMAT_ARGB4444:
  663. ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444);
  664. break;
  665. default:
  666. return -EINVAL;
  667. }
  668. switch (drm_fourcc) {
  669. case DRM_FORMAT_RGB565_A8:
  670. case DRM_FORMAT_BGR565_A8:
  671. case DRM_FORMAT_RGB888_A8:
  672. case DRM_FORMAT_BGR888_A8:
  673. case DRM_FORMAT_RGBX8888_A8:
  674. case DRM_FORMAT_BGRX8888_A8:
  675. ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
  676. ipu_cpmem_set_separate_alpha(ch);
  677. break;
  678. default:
  679. break;
  680. }
  681. return 0;
  682. }
  683. EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
  684. int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
  685. {
  686. struct v4l2_pix_format *pix = &image->pix;
  687. int offset, u_offset, v_offset;
  688. int ret = 0;
  689. pr_debug("%s: resolution: %dx%d stride: %d\n",
  690. __func__, pix->width, pix->height,
  691. pix->bytesperline);
  692. ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
  693. ipu_cpmem_set_stride(ch, pix->bytesperline);
  694. ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
  695. switch (pix->pixelformat) {
  696. case V4L2_PIX_FMT_YUV420:
  697. offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
  698. u_offset = image->u_offset ?
  699. image->u_offset : U_OFFSET(pix, image->rect.left,
  700. image->rect.top) - offset;
  701. v_offset = image->v_offset ?
  702. image->v_offset : V_OFFSET(pix, image->rect.left,
  703. image->rect.top) - offset;
  704. ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
  705. u_offset, v_offset);
  706. break;
  707. case V4L2_PIX_FMT_YVU420:
  708. offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
  709. u_offset = image->u_offset ?
  710. image->u_offset : V_OFFSET(pix, image->rect.left,
  711. image->rect.top) - offset;
  712. v_offset = image->v_offset ?
  713. image->v_offset : U_OFFSET(pix, image->rect.left,
  714. image->rect.top) - offset;
  715. ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
  716. u_offset, v_offset);
  717. break;
  718. case V4L2_PIX_FMT_YUV422P:
  719. offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
  720. u_offset = image->u_offset ?
  721. image->u_offset : U2_OFFSET(pix, image->rect.left,
  722. image->rect.top) - offset;
  723. v_offset = image->v_offset ?
  724. image->v_offset : V2_OFFSET(pix, image->rect.left,
  725. image->rect.top) - offset;
  726. ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
  727. u_offset, v_offset);
  728. break;
  729. case V4L2_PIX_FMT_NV12:
  730. offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
  731. u_offset = image->u_offset ?
  732. image->u_offset : UV_OFFSET(pix, image->rect.left,
  733. image->rect.top) - offset;
  734. v_offset = image->v_offset ? image->v_offset : 0;
  735. ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
  736. u_offset, v_offset);
  737. break;
  738. case V4L2_PIX_FMT_NV16:
  739. offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
  740. u_offset = image->u_offset ?
  741. image->u_offset : UV2_OFFSET(pix, image->rect.left,
  742. image->rect.top) - offset;
  743. v_offset = image->v_offset ? image->v_offset : 0;
  744. ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
  745. u_offset, v_offset);
  746. break;
  747. case V4L2_PIX_FMT_UYVY:
  748. case V4L2_PIX_FMT_YUYV:
  749. case V4L2_PIX_FMT_RGB565:
  750. offset = image->rect.left * 2 +
  751. image->rect.top * pix->bytesperline;
  752. break;
  753. case V4L2_PIX_FMT_RGB32:
  754. case V4L2_PIX_FMT_BGR32:
  755. case V4L2_PIX_FMT_ABGR32:
  756. case V4L2_PIX_FMT_XBGR32:
  757. case V4L2_PIX_FMT_BGRA32:
  758. case V4L2_PIX_FMT_BGRX32:
  759. case V4L2_PIX_FMT_RGBA32:
  760. case V4L2_PIX_FMT_RGBX32:
  761. case V4L2_PIX_FMT_ARGB32:
  762. case V4L2_PIX_FMT_XRGB32:
  763. offset = image->rect.left * 4 +
  764. image->rect.top * pix->bytesperline;
  765. break;
  766. case V4L2_PIX_FMT_RGB24:
  767. case V4L2_PIX_FMT_BGR24:
  768. offset = image->rect.left * 3 +
  769. image->rect.top * pix->bytesperline;
  770. break;
  771. case V4L2_PIX_FMT_SBGGR8:
  772. case V4L2_PIX_FMT_SGBRG8:
  773. case V4L2_PIX_FMT_SGRBG8:
  774. case V4L2_PIX_FMT_SRGGB8:
  775. case V4L2_PIX_FMT_GREY:
  776. offset = image->rect.left + image->rect.top * pix->bytesperline;
  777. break;
  778. case V4L2_PIX_FMT_SBGGR16:
  779. case V4L2_PIX_FMT_SGBRG16:
  780. case V4L2_PIX_FMT_SGRBG16:
  781. case V4L2_PIX_FMT_SRGGB16:
  782. case V4L2_PIX_FMT_Y16:
  783. offset = image->rect.left * 2 +
  784. image->rect.top * pix->bytesperline;
  785. break;
  786. default:
  787. /* This should not happen */
  788. WARN_ON(1);
  789. offset = 0;
  790. ret = -EINVAL;
  791. }
  792. ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
  793. ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
  794. return ret;
  795. }
  796. EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
  797. void ipu_cpmem_dump(struct ipuv3_channel *ch)
  798. {
  799. struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
  800. struct ipu_soc *ipu = ch->ipu;
  801. int chno = ch->num;
  802. dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno,
  803. readl(&p->word[0].data[0]),
  804. readl(&p->word[0].data[1]),
  805. readl(&p->word[0].data[2]),
  806. readl(&p->word[0].data[3]),
  807. readl(&p->word[0].data[4]));
  808. dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno,
  809. readl(&p->word[1].data[0]),
  810. readl(&p->word[1].data[1]),
  811. readl(&p->word[1].data[2]),
  812. readl(&p->word[1].data[3]),
  813. readl(&p->word[1].data[4]));
  814. dev_dbg(ipu->dev, "PFS 0x%x, ",
  815. ipu_ch_param_read_field(ch, IPU_FIELD_PFS));
  816. dev_dbg(ipu->dev, "BPP 0x%x, ",
  817. ipu_ch_param_read_field(ch, IPU_FIELD_BPP));
  818. dev_dbg(ipu->dev, "NPB 0x%x\n",
  819. ipu_ch_param_read_field(ch, IPU_FIELD_NPB));
  820. dev_dbg(ipu->dev, "FW %d, ",
  821. ipu_ch_param_read_field(ch, IPU_FIELD_FW));
  822. dev_dbg(ipu->dev, "FH %d, ",
  823. ipu_ch_param_read_field(ch, IPU_FIELD_FH));
  824. dev_dbg(ipu->dev, "EBA0 0x%x\n",
  825. ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3);
  826. dev_dbg(ipu->dev, "EBA1 0x%x\n",
  827. ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3);
  828. dev_dbg(ipu->dev, "Stride %d\n",
  829. ipu_ch_param_read_field(ch, IPU_FIELD_SL));
  830. dev_dbg(ipu->dev, "scan_order %d\n",
  831. ipu_ch_param_read_field(ch, IPU_FIELD_SO));
  832. dev_dbg(ipu->dev, "uv_stride %d\n",
  833. ipu_ch_param_read_field(ch, IPU_FIELD_SLUV));
  834. dev_dbg(ipu->dev, "u_offset 0x%x\n",
  835. ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3);
  836. dev_dbg(ipu->dev, "v_offset 0x%x\n",
  837. ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3);
  838. dev_dbg(ipu->dev, "Width0 %d+1, ",
  839. ipu_ch_param_read_field(ch, IPU_FIELD_WID0));
  840. dev_dbg(ipu->dev, "Width1 %d+1, ",
  841. ipu_ch_param_read_field(ch, IPU_FIELD_WID1));
  842. dev_dbg(ipu->dev, "Width2 %d+1, ",
  843. ipu_ch_param_read_field(ch, IPU_FIELD_WID2));
  844. dev_dbg(ipu->dev, "Width3 %d+1, ",
  845. ipu_ch_param_read_field(ch, IPU_FIELD_WID3));
  846. dev_dbg(ipu->dev, "Offset0 %d, ",
  847. ipu_ch_param_read_field(ch, IPU_FIELD_OFS0));
  848. dev_dbg(ipu->dev, "Offset1 %d, ",
  849. ipu_ch_param_read_field(ch, IPU_FIELD_OFS1));
  850. dev_dbg(ipu->dev, "Offset2 %d, ",
  851. ipu_ch_param_read_field(ch, IPU_FIELD_OFS2));
  852. dev_dbg(ipu->dev, "Offset3 %d\n",
  853. ipu_ch_param_read_field(ch, IPU_FIELD_OFS3));
  854. }
  855. EXPORT_SYMBOL_GPL(ipu_cpmem_dump);
  856. int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
  857. {
  858. struct ipu_cpmem *cpmem;
  859. cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
  860. if (!cpmem)
  861. return -ENOMEM;
  862. ipu->cpmem_priv = cpmem;
  863. spin_lock_init(&cpmem->lock);
  864. cpmem->base = devm_ioremap(dev, base, SZ_128K);
  865. if (!cpmem->base)
  866. return -ENOMEM;
  867. dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
  868. base, cpmem->base);
  869. cpmem->ipu = ipu;
  870. return 0;
  871. }
  872. void ipu_cpmem_exit(struct ipu_soc *ipu)
  873. {
  874. }