gpio-zynq.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Xilinx Zynq GPIO device driver
  4. *
  5. * Copyright (C) 2009 - 2014 Xilinx, Inc.
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/of.h>
  18. #define DRIVER_NAME "zynq-gpio"
  19. /* Maximum banks */
  20. #define ZYNQ_GPIO_MAX_BANK 4
  21. #define ZYNQMP_GPIO_MAX_BANK 6
  22. #define VERSAL_GPIO_MAX_BANK 4
  23. #define PMC_GPIO_MAX_BANK 5
  24. #define VERSAL_UNUSED_BANKS 2
  25. #define ZYNQ_GPIO_BANK0_NGPIO 32
  26. #define ZYNQ_GPIO_BANK1_NGPIO 22
  27. #define ZYNQ_GPIO_BANK2_NGPIO 32
  28. #define ZYNQ_GPIO_BANK3_NGPIO 32
  29. #define ZYNQMP_GPIO_BANK0_NGPIO 26
  30. #define ZYNQMP_GPIO_BANK1_NGPIO 26
  31. #define ZYNQMP_GPIO_BANK2_NGPIO 26
  32. #define ZYNQMP_GPIO_BANK3_NGPIO 32
  33. #define ZYNQMP_GPIO_BANK4_NGPIO 32
  34. #define ZYNQMP_GPIO_BANK5_NGPIO 32
  35. #define ZYNQ_GPIO_NR_GPIOS 118
  36. #define ZYNQMP_GPIO_NR_GPIOS 174
  37. #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
  38. #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
  39. ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
  40. #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
  41. #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
  42. ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
  43. #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
  44. #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
  45. ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
  46. #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
  47. #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
  48. ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
  49. #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
  50. #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
  51. ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
  52. #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
  53. #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
  54. ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
  55. /* Register offsets for the GPIO device */
  56. /* LSW Mask & Data -WO */
  57. #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  58. /* MSW Mask & Data -WO */
  59. #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  60. /* Data Register-RW */
  61. #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
  62. #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
  63. /* Direction mode reg-RW */
  64. #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
  65. /* Output enable reg-RW */
  66. #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
  67. /* Interrupt mask reg-RO */
  68. #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
  69. /* Interrupt enable reg-WO */
  70. #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
  71. /* Interrupt disable reg-WO */
  72. #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
  73. /* Interrupt status reg-RO */
  74. #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
  75. /* Interrupt type reg-RW */
  76. #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
  77. /* Interrupt polarity reg-RW */
  78. #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
  79. /* Interrupt on any, reg-RW */
  80. #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
  81. /* Disable all interrupts mask */
  82. #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
  83. /* Mid pin number of a bank */
  84. #define ZYNQ_GPIO_MID_PIN_NUM 16
  85. /* GPIO upper 16 bit mask */
  86. #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  87. /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
  88. #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
  89. #define GPIO_QUIRK_DATA_RO_BUG BIT(1)
  90. #define GPIO_QUIRK_VERSAL BIT(2)
  91. struct gpio_regs {
  92. u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
  93. u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
  94. u32 dirm[ZYNQMP_GPIO_MAX_BANK];
  95. u32 outen[ZYNQMP_GPIO_MAX_BANK];
  96. u32 int_en[ZYNQMP_GPIO_MAX_BANK];
  97. u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
  98. u32 int_type[ZYNQMP_GPIO_MAX_BANK];
  99. u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
  100. u32 int_any[ZYNQMP_GPIO_MAX_BANK];
  101. };
  102. /**
  103. * struct zynq_gpio - gpio device private data structure
  104. * @chip: instance of the gpio_chip
  105. * @base_addr: base address of the GPIO device
  106. * @clk: clock resource for this controller
  107. * @irq: interrupt for the GPIO device
  108. * @p_data: pointer to platform data
  109. * @context: context registers
  110. * @dirlock: lock used for direction in/out synchronization
  111. */
  112. struct zynq_gpio {
  113. struct gpio_chip chip;
  114. void __iomem *base_addr;
  115. struct clk *clk;
  116. int irq;
  117. const struct zynq_platform_data *p_data;
  118. struct gpio_regs context;
  119. spinlock_t dirlock; /* lock */
  120. };
  121. /**
  122. * struct zynq_platform_data - zynq gpio platform data structure
  123. * @label: string to store in gpio->label
  124. * @quirks: Flags is used to identify the platform
  125. * @ngpio: max number of gpio pins
  126. * @max_bank: maximum number of gpio banks
  127. * @bank_min: this array represents bank's min pin
  128. * @bank_max: this array represents bank's max pin
  129. */
  130. struct zynq_platform_data {
  131. const char *label;
  132. u32 quirks;
  133. u16 ngpio;
  134. int max_bank;
  135. int bank_min[ZYNQMP_GPIO_MAX_BANK];
  136. int bank_max[ZYNQMP_GPIO_MAX_BANK];
  137. };
  138. static struct irq_chip zynq_gpio_level_irqchip;
  139. static struct irq_chip zynq_gpio_edge_irqchip;
  140. /**
  141. * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
  142. * @gpio: Pointer to driver data struct
  143. *
  144. * Return: 0 if zynqmp, 1 if zynq.
  145. */
  146. static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
  147. {
  148. return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
  149. }
  150. /**
  151. * gpio_data_ro_bug - test if HW bug exists or not
  152. * @gpio: Pointer to driver data struct
  153. *
  154. * Return: 0 if bug doesnot exist, 1 if bug exists.
  155. */
  156. static int gpio_data_ro_bug(struct zynq_gpio *gpio)
  157. {
  158. return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
  159. }
  160. /**
  161. * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
  162. * for a given pin in the GPIO device
  163. * @pin_num: gpio pin number within the device
  164. * @bank_num: an output parameter used to return the bank number of the gpio
  165. * pin
  166. * @bank_pin_num: an output parameter used to return pin number within a bank
  167. * for the given gpio pin
  168. * @gpio: gpio device data structure
  169. *
  170. * Returns the bank number and pin offset within the bank.
  171. */
  172. static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
  173. unsigned int *bank_num,
  174. unsigned int *bank_pin_num,
  175. struct zynq_gpio *gpio)
  176. {
  177. int bank;
  178. for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
  179. if ((pin_num >= gpio->p_data->bank_min[bank]) &&
  180. (pin_num <= gpio->p_data->bank_max[bank])) {
  181. *bank_num = bank;
  182. *bank_pin_num = pin_num -
  183. gpio->p_data->bank_min[bank];
  184. return;
  185. }
  186. if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
  187. bank = bank + VERSAL_UNUSED_BANKS;
  188. }
  189. /* default */
  190. WARN(true, "invalid GPIO pin number: %u", pin_num);
  191. *bank_num = 0;
  192. *bank_pin_num = 0;
  193. }
  194. /**
  195. * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
  196. * @chip: gpio_chip instance to be worked on
  197. * @pin: gpio pin number within the device
  198. *
  199. * This function reads the state of the specified pin of the GPIO device.
  200. *
  201. * Return: 0 if the pin is low, 1 if pin is high.
  202. */
  203. static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
  204. {
  205. u32 data;
  206. unsigned int bank_num, bank_pin_num;
  207. struct zynq_gpio *gpio = gpiochip_get_data(chip);
  208. zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
  209. if (gpio_data_ro_bug(gpio)) {
  210. if (zynq_gpio_is_zynq(gpio)) {
  211. if (bank_num <= 1) {
  212. data = readl_relaxed(gpio->base_addr +
  213. ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
  214. } else {
  215. data = readl_relaxed(gpio->base_addr +
  216. ZYNQ_GPIO_DATA_OFFSET(bank_num));
  217. }
  218. } else {
  219. if (bank_num <= 2) {
  220. data = readl_relaxed(gpio->base_addr +
  221. ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
  222. } else {
  223. data = readl_relaxed(gpio->base_addr +
  224. ZYNQ_GPIO_DATA_OFFSET(bank_num));
  225. }
  226. }
  227. } else {
  228. data = readl_relaxed(gpio->base_addr +
  229. ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
  230. }
  231. return (data >> bank_pin_num) & 1;
  232. }
  233. /**
  234. * zynq_gpio_set_value - Modify the state of the pin with specified value
  235. * @chip: gpio_chip instance to be worked on
  236. * @pin: gpio pin number within the device
  237. * @state: value used to modify the state of the specified pin
  238. *
  239. * This function calculates the register offset (i.e to lower 16 bits or
  240. * upper 16 bits) based on the given pin number and sets the state of a
  241. * gpio pin to the specified value. The state is either 0 or non-zero.
  242. */
  243. static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
  244. int state)
  245. {
  246. unsigned int reg_offset, bank_num, bank_pin_num;
  247. struct zynq_gpio *gpio = gpiochip_get_data(chip);
  248. zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
  249. if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
  250. /* only 16 data bits in bit maskable reg */
  251. bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
  252. reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
  253. } else {
  254. reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
  255. }
  256. /*
  257. * get the 32 bit value to be written to the mask/data register where
  258. * the upper 16 bits is the mask and lower 16 bits is the data
  259. */
  260. state = !!state;
  261. state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
  262. ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
  263. writel_relaxed(state, gpio->base_addr + reg_offset);
  264. }
  265. /**
  266. * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
  267. * @chip: gpio_chip instance to be worked on
  268. * @pin: gpio pin number within the device
  269. *
  270. * This function uses the read-modify-write sequence to set the direction of
  271. * the gpio pin as input.
  272. *
  273. * Return: 0 always
  274. */
  275. static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
  276. {
  277. u32 reg;
  278. unsigned int bank_num, bank_pin_num;
  279. unsigned long flags;
  280. struct zynq_gpio *gpio = gpiochip_get_data(chip);
  281. zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
  282. /*
  283. * On zynq bank 0 pins 7 and 8 are special and cannot be used
  284. * as inputs.
  285. */
  286. if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
  287. (bank_pin_num == 7 || bank_pin_num == 8))
  288. return -EINVAL;
  289. /* clear the bit in direction mode reg to set the pin as input */
  290. spin_lock_irqsave(&gpio->dirlock, flags);
  291. reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  292. reg &= ~BIT(bank_pin_num);
  293. writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  294. spin_unlock_irqrestore(&gpio->dirlock, flags);
  295. return 0;
  296. }
  297. /**
  298. * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
  299. * @chip: gpio_chip instance to be worked on
  300. * @pin: gpio pin number within the device
  301. * @state: value to be written to specified pin
  302. *
  303. * This function sets the direction of specified GPIO pin as output, configures
  304. * the Output Enable register for the pin and uses zynq_gpio_set to set
  305. * the state of the pin to the value specified.
  306. *
  307. * Return: 0 always
  308. */
  309. static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
  310. int state)
  311. {
  312. u32 reg;
  313. unsigned int bank_num, bank_pin_num;
  314. unsigned long flags;
  315. struct zynq_gpio *gpio = gpiochip_get_data(chip);
  316. zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
  317. /* set the GPIO pin as output */
  318. spin_lock_irqsave(&gpio->dirlock, flags);
  319. reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  320. reg |= BIT(bank_pin_num);
  321. writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  322. /* configure the output enable reg for the pin */
  323. reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
  324. reg |= BIT(bank_pin_num);
  325. writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
  326. spin_unlock_irqrestore(&gpio->dirlock, flags);
  327. /* set the state of the pin */
  328. zynq_gpio_set_value(chip, pin, state);
  329. return 0;
  330. }
  331. /**
  332. * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
  333. * @chip: gpio_chip instance to be worked on
  334. * @pin: gpio pin number within the device
  335. *
  336. * This function returns the direction of the specified GPIO.
  337. *
  338. * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
  339. */
  340. static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
  341. {
  342. u32 reg;
  343. unsigned int bank_num, bank_pin_num;
  344. struct zynq_gpio *gpio = gpiochip_get_data(chip);
  345. zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
  346. reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  347. if (reg & BIT(bank_pin_num))
  348. return GPIO_LINE_DIRECTION_OUT;
  349. return GPIO_LINE_DIRECTION_IN;
  350. }
  351. /**
  352. * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
  353. * @irq_data: per irq and chip data passed down to chip functions
  354. *
  355. * This function calculates gpio pin number from irq number and sets the
  356. * bit in the Interrupt Disable register of the corresponding bank to disable
  357. * interrupts for that pin.
  358. */
  359. static void zynq_gpio_irq_mask(struct irq_data *irq_data)
  360. {
  361. unsigned int device_pin_num, bank_num, bank_pin_num;
  362. struct zynq_gpio *gpio =
  363. gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
  364. device_pin_num = irq_data->hwirq;
  365. zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
  366. writel_relaxed(BIT(bank_pin_num),
  367. gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
  368. }
  369. /**
  370. * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
  371. * @irq_data: irq data containing irq number of gpio pin for the interrupt
  372. * to enable
  373. *
  374. * This function calculates the gpio pin number from irq number and sets the
  375. * bit in the Interrupt Enable register of the corresponding bank to enable
  376. * interrupts for that pin.
  377. */
  378. static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
  379. {
  380. unsigned int device_pin_num, bank_num, bank_pin_num;
  381. struct zynq_gpio *gpio =
  382. gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
  383. device_pin_num = irq_data->hwirq;
  384. zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
  385. writel_relaxed(BIT(bank_pin_num),
  386. gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
  387. }
  388. /**
  389. * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
  390. * @irq_data: irq data containing irq number of gpio pin for the interrupt
  391. * to ack
  392. *
  393. * This function calculates gpio pin number from irq number and sets the bit
  394. * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
  395. */
  396. static void zynq_gpio_irq_ack(struct irq_data *irq_data)
  397. {
  398. unsigned int device_pin_num, bank_num, bank_pin_num;
  399. struct zynq_gpio *gpio =
  400. gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
  401. device_pin_num = irq_data->hwirq;
  402. zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
  403. writel_relaxed(BIT(bank_pin_num),
  404. gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
  405. }
  406. /**
  407. * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
  408. * @irq_data: irq data containing irq number of gpio pin for the interrupt
  409. * to enable
  410. *
  411. * Clears the INTSTS bit and unmasks the given interrupt.
  412. */
  413. static void zynq_gpio_irq_enable(struct irq_data *irq_data)
  414. {
  415. /*
  416. * The Zynq GPIO controller does not disable interrupt detection when
  417. * the interrupt is masked and only disables the propagation of the
  418. * interrupt. This means when the controller detects an interrupt
  419. * condition while the interrupt is logically disabled it will propagate
  420. * that interrupt event once the interrupt is enabled. This will cause
  421. * the interrupt consumer to see spurious interrupts to prevent this
  422. * first make sure that the interrupt is not asserted and then enable
  423. * it.
  424. */
  425. zynq_gpio_irq_ack(irq_data);
  426. zynq_gpio_irq_unmask(irq_data);
  427. }
  428. /**
  429. * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
  430. * @irq_data: irq data containing irq number of gpio pin
  431. * @type: interrupt type that is to be set for the gpio pin
  432. *
  433. * This function gets the gpio pin number and its bank from the gpio pin number
  434. * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
  435. *
  436. * Return: 0, negative error otherwise.
  437. * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
  438. * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
  439. * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
  440. * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
  441. * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
  442. */
  443. static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
  444. {
  445. u32 int_type, int_pol, int_any;
  446. unsigned int device_pin_num, bank_num, bank_pin_num;
  447. struct zynq_gpio *gpio =
  448. gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
  449. device_pin_num = irq_data->hwirq;
  450. zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
  451. int_type = readl_relaxed(gpio->base_addr +
  452. ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
  453. int_pol = readl_relaxed(gpio->base_addr +
  454. ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
  455. int_any = readl_relaxed(gpio->base_addr +
  456. ZYNQ_GPIO_INTANY_OFFSET(bank_num));
  457. /*
  458. * based on the type requested, configure the INT_TYPE, INT_POLARITY
  459. * and INT_ANY registers
  460. */
  461. switch (type) {
  462. case IRQ_TYPE_EDGE_RISING:
  463. int_type |= BIT(bank_pin_num);
  464. int_pol |= BIT(bank_pin_num);
  465. int_any &= ~BIT(bank_pin_num);
  466. break;
  467. case IRQ_TYPE_EDGE_FALLING:
  468. int_type |= BIT(bank_pin_num);
  469. int_pol &= ~BIT(bank_pin_num);
  470. int_any &= ~BIT(bank_pin_num);
  471. break;
  472. case IRQ_TYPE_EDGE_BOTH:
  473. int_type |= BIT(bank_pin_num);
  474. int_any |= BIT(bank_pin_num);
  475. break;
  476. case IRQ_TYPE_LEVEL_HIGH:
  477. int_type &= ~BIT(bank_pin_num);
  478. int_pol |= BIT(bank_pin_num);
  479. break;
  480. case IRQ_TYPE_LEVEL_LOW:
  481. int_type &= ~BIT(bank_pin_num);
  482. int_pol &= ~BIT(bank_pin_num);
  483. break;
  484. default:
  485. return -EINVAL;
  486. }
  487. writel_relaxed(int_type,
  488. gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
  489. writel_relaxed(int_pol,
  490. gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
  491. writel_relaxed(int_any,
  492. gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
  493. if (type & IRQ_TYPE_LEVEL_MASK)
  494. irq_set_chip_handler_name_locked(irq_data,
  495. &zynq_gpio_level_irqchip,
  496. handle_fasteoi_irq, NULL);
  497. else
  498. irq_set_chip_handler_name_locked(irq_data,
  499. &zynq_gpio_edge_irqchip,
  500. handle_level_irq, NULL);
  501. return 0;
  502. }
  503. static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
  504. {
  505. struct zynq_gpio *gpio =
  506. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  507. irq_set_irq_wake(gpio->irq, on);
  508. return 0;
  509. }
  510. static int zynq_gpio_irq_reqres(struct irq_data *d)
  511. {
  512. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  513. int ret;
  514. ret = pm_runtime_resume_and_get(chip->parent);
  515. if (ret < 0)
  516. return ret;
  517. return gpiochip_reqres_irq(chip, d->hwirq);
  518. }
  519. static void zynq_gpio_irq_relres(struct irq_data *d)
  520. {
  521. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  522. gpiochip_relres_irq(chip, d->hwirq);
  523. pm_runtime_put(chip->parent);
  524. }
  525. /* irq chip descriptor */
  526. static struct irq_chip zynq_gpio_level_irqchip = {
  527. .name = DRIVER_NAME,
  528. .irq_enable = zynq_gpio_irq_enable,
  529. .irq_eoi = zynq_gpio_irq_ack,
  530. .irq_mask = zynq_gpio_irq_mask,
  531. .irq_unmask = zynq_gpio_irq_unmask,
  532. .irq_set_type = zynq_gpio_set_irq_type,
  533. .irq_set_wake = zynq_gpio_set_wake,
  534. .irq_request_resources = zynq_gpio_irq_reqres,
  535. .irq_release_resources = zynq_gpio_irq_relres,
  536. .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
  537. IRQCHIP_MASK_ON_SUSPEND,
  538. };
  539. static struct irq_chip zynq_gpio_edge_irqchip = {
  540. .name = DRIVER_NAME,
  541. .irq_enable = zynq_gpio_irq_enable,
  542. .irq_ack = zynq_gpio_irq_ack,
  543. .irq_mask = zynq_gpio_irq_mask,
  544. .irq_unmask = zynq_gpio_irq_unmask,
  545. .irq_set_type = zynq_gpio_set_irq_type,
  546. .irq_set_wake = zynq_gpio_set_wake,
  547. .irq_request_resources = zynq_gpio_irq_reqres,
  548. .irq_release_resources = zynq_gpio_irq_relres,
  549. .flags = IRQCHIP_MASK_ON_SUSPEND,
  550. };
  551. static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
  552. unsigned int bank_num,
  553. unsigned long pending)
  554. {
  555. unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
  556. struct irq_domain *irqdomain = gpio->chip.irq.domain;
  557. int offset;
  558. if (!pending)
  559. return;
  560. for_each_set_bit(offset, &pending, 32) {
  561. unsigned int gpio_irq;
  562. gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
  563. generic_handle_irq(gpio_irq);
  564. }
  565. }
  566. /**
  567. * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
  568. * @desc: irq descriptor instance of the 'irq'
  569. *
  570. * This function reads the Interrupt Status Register of each bank to get the
  571. * gpio pin number which has triggered an interrupt. It then acks the triggered
  572. * interrupt and calls the pin specific handler set by the higher layer
  573. * application for that pin.
  574. * Note: A bug is reported if no handler is set for the gpio pin.
  575. */
  576. static void zynq_gpio_irqhandler(struct irq_desc *desc)
  577. {
  578. u32 int_sts, int_enb;
  579. unsigned int bank_num;
  580. struct zynq_gpio *gpio =
  581. gpiochip_get_data(irq_desc_get_handler_data(desc));
  582. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  583. chained_irq_enter(irqchip, desc);
  584. for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
  585. int_sts = readl_relaxed(gpio->base_addr +
  586. ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
  587. int_enb = readl_relaxed(gpio->base_addr +
  588. ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
  589. zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
  590. if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
  591. bank_num = bank_num + VERSAL_UNUSED_BANKS;
  592. }
  593. chained_irq_exit(irqchip, desc);
  594. }
  595. static void zynq_gpio_save_context(struct zynq_gpio *gpio)
  596. {
  597. unsigned int bank_num;
  598. for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
  599. gpio->context.datalsw[bank_num] =
  600. readl_relaxed(gpio->base_addr +
  601. ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
  602. gpio->context.datamsw[bank_num] =
  603. readl_relaxed(gpio->base_addr +
  604. ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
  605. gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
  606. ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  607. gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
  608. ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
  609. gpio->context.int_type[bank_num] =
  610. readl_relaxed(gpio->base_addr +
  611. ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
  612. gpio->context.int_polarity[bank_num] =
  613. readl_relaxed(gpio->base_addr +
  614. ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
  615. gpio->context.int_any[bank_num] =
  616. readl_relaxed(gpio->base_addr +
  617. ZYNQ_GPIO_INTANY_OFFSET(bank_num));
  618. if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
  619. bank_num = bank_num + VERSAL_UNUSED_BANKS;
  620. }
  621. }
  622. static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
  623. {
  624. unsigned int bank_num;
  625. for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
  626. writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
  627. ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
  628. writel_relaxed(gpio->context.datalsw[bank_num],
  629. gpio->base_addr +
  630. ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
  631. writel_relaxed(gpio->context.datamsw[bank_num],
  632. gpio->base_addr +
  633. ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
  634. writel_relaxed(gpio->context.dirm[bank_num],
  635. gpio->base_addr +
  636. ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  637. writel_relaxed(gpio->context.int_type[bank_num],
  638. gpio->base_addr +
  639. ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
  640. writel_relaxed(gpio->context.int_polarity[bank_num],
  641. gpio->base_addr +
  642. ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
  643. writel_relaxed(gpio->context.int_any[bank_num],
  644. gpio->base_addr +
  645. ZYNQ_GPIO_INTANY_OFFSET(bank_num));
  646. writel_relaxed(~(gpio->context.int_en[bank_num]),
  647. gpio->base_addr +
  648. ZYNQ_GPIO_INTEN_OFFSET(bank_num));
  649. if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
  650. bank_num = bank_num + VERSAL_UNUSED_BANKS;
  651. }
  652. }
  653. static int __maybe_unused zynq_gpio_suspend(struct device *dev)
  654. {
  655. struct zynq_gpio *gpio = dev_get_drvdata(dev);
  656. struct irq_data *data = irq_get_irq_data(gpio->irq);
  657. if (!data) {
  658. dev_err(dev, "irq_get_irq_data() failed\n");
  659. return -EINVAL;
  660. }
  661. if (!device_may_wakeup(dev))
  662. disable_irq(gpio->irq);
  663. if (!irqd_is_wakeup_set(data)) {
  664. zynq_gpio_save_context(gpio);
  665. return pm_runtime_force_suspend(dev);
  666. }
  667. return 0;
  668. }
  669. static int __maybe_unused zynq_gpio_resume(struct device *dev)
  670. {
  671. struct zynq_gpio *gpio = dev_get_drvdata(dev);
  672. struct irq_data *data = irq_get_irq_data(gpio->irq);
  673. int ret;
  674. if (!data) {
  675. dev_err(dev, "irq_get_irq_data() failed\n");
  676. return -EINVAL;
  677. }
  678. if (!device_may_wakeup(dev))
  679. enable_irq(gpio->irq);
  680. if (!irqd_is_wakeup_set(data)) {
  681. ret = pm_runtime_force_resume(dev);
  682. zynq_gpio_restore_context(gpio);
  683. return ret;
  684. }
  685. return 0;
  686. }
  687. static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
  688. {
  689. struct zynq_gpio *gpio = dev_get_drvdata(dev);
  690. clk_disable_unprepare(gpio->clk);
  691. return 0;
  692. }
  693. static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
  694. {
  695. struct zynq_gpio *gpio = dev_get_drvdata(dev);
  696. return clk_prepare_enable(gpio->clk);
  697. }
  698. static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
  699. {
  700. int ret;
  701. ret = pm_runtime_get_sync(chip->parent);
  702. /*
  703. * If the device is already active pm_runtime_get() will return 1 on
  704. * success, but gpio_request still needs to return 0.
  705. */
  706. return ret < 0 ? ret : 0;
  707. }
  708. static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
  709. {
  710. pm_runtime_put(chip->parent);
  711. }
  712. static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
  713. SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
  714. SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
  715. zynq_gpio_runtime_resume, NULL)
  716. };
  717. static const struct zynq_platform_data versal_gpio_def = {
  718. .label = "versal_gpio",
  719. .quirks = GPIO_QUIRK_VERSAL,
  720. .ngpio = 58,
  721. .max_bank = VERSAL_GPIO_MAX_BANK,
  722. .bank_min[0] = 0,
  723. .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
  724. .bank_min[3] = 26,
  725. .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
  726. };
  727. static const struct zynq_platform_data pmc_gpio_def = {
  728. .label = "pmc_gpio",
  729. .ngpio = 116,
  730. .max_bank = PMC_GPIO_MAX_BANK,
  731. .bank_min[0] = 0,
  732. .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
  733. .bank_min[1] = 26,
  734. .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
  735. .bank_min[3] = 52,
  736. .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
  737. .bank_min[4] = 84,
  738. .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
  739. };
  740. static const struct zynq_platform_data zynqmp_gpio_def = {
  741. .label = "zynqmp_gpio",
  742. .quirks = GPIO_QUIRK_DATA_RO_BUG,
  743. .ngpio = ZYNQMP_GPIO_NR_GPIOS,
  744. .max_bank = ZYNQMP_GPIO_MAX_BANK,
  745. .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
  746. .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
  747. .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
  748. .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
  749. .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
  750. .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
  751. .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
  752. .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
  753. .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
  754. .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
  755. .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
  756. .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
  757. };
  758. static const struct zynq_platform_data zynq_gpio_def = {
  759. .label = "zynq_gpio",
  760. .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
  761. .ngpio = ZYNQ_GPIO_NR_GPIOS,
  762. .max_bank = ZYNQ_GPIO_MAX_BANK,
  763. .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
  764. .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
  765. .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
  766. .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
  767. .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
  768. .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
  769. .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
  770. .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
  771. };
  772. static const struct of_device_id zynq_gpio_of_match[] = {
  773. { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
  774. { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
  775. { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
  776. { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
  777. { /* end of table */ }
  778. };
  779. MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
  780. /**
  781. * zynq_gpio_probe - Initialization method for a zynq_gpio device
  782. * @pdev: platform device instance
  783. *
  784. * This function allocates memory resources for the gpio device and registers
  785. * all the banks of the device. It will also set up interrupts for the gpio
  786. * pins.
  787. * Note: Interrupts are disabled for all the banks during initialization.
  788. *
  789. * Return: 0 on success, negative error otherwise.
  790. */
  791. static int zynq_gpio_probe(struct platform_device *pdev)
  792. {
  793. int ret, bank_num;
  794. struct zynq_gpio *gpio;
  795. struct gpio_chip *chip;
  796. struct gpio_irq_chip *girq;
  797. const struct of_device_id *match;
  798. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  799. if (!gpio)
  800. return -ENOMEM;
  801. match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
  802. if (!match) {
  803. dev_err(&pdev->dev, "of_match_node() failed\n");
  804. return -EINVAL;
  805. }
  806. gpio->p_data = match->data;
  807. platform_set_drvdata(pdev, gpio);
  808. gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
  809. if (IS_ERR(gpio->base_addr))
  810. return PTR_ERR(gpio->base_addr);
  811. gpio->irq = platform_get_irq(pdev, 0);
  812. if (gpio->irq < 0)
  813. return gpio->irq;
  814. /* configure the gpio chip */
  815. chip = &gpio->chip;
  816. chip->label = gpio->p_data->label;
  817. chip->owner = THIS_MODULE;
  818. chip->parent = &pdev->dev;
  819. chip->get = zynq_gpio_get_value;
  820. chip->set = zynq_gpio_set_value;
  821. chip->request = zynq_gpio_request;
  822. chip->free = zynq_gpio_free;
  823. chip->direction_input = zynq_gpio_dir_in;
  824. chip->direction_output = zynq_gpio_dir_out;
  825. chip->get_direction = zynq_gpio_get_direction;
  826. chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
  827. chip->ngpio = gpio->p_data->ngpio;
  828. /* Retrieve GPIO clock */
  829. gpio->clk = devm_clk_get(&pdev->dev, NULL);
  830. if (IS_ERR(gpio->clk))
  831. return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
  832. ret = clk_prepare_enable(gpio->clk);
  833. if (ret) {
  834. dev_err(&pdev->dev, "Unable to enable clock.\n");
  835. return ret;
  836. }
  837. spin_lock_init(&gpio->dirlock);
  838. pm_runtime_set_active(&pdev->dev);
  839. pm_runtime_enable(&pdev->dev);
  840. ret = pm_runtime_resume_and_get(&pdev->dev);
  841. if (ret < 0)
  842. goto err_pm_dis;
  843. /* disable interrupts for all banks */
  844. for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
  845. writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
  846. ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
  847. if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
  848. bank_num = bank_num + VERSAL_UNUSED_BANKS;
  849. }
  850. /* Set up the GPIO irqchip */
  851. girq = &chip->irq;
  852. girq->chip = &zynq_gpio_edge_irqchip;
  853. girq->parent_handler = zynq_gpio_irqhandler;
  854. girq->num_parents = 1;
  855. girq->parents = devm_kcalloc(&pdev->dev, 1,
  856. sizeof(*girq->parents),
  857. GFP_KERNEL);
  858. if (!girq->parents) {
  859. ret = -ENOMEM;
  860. goto err_pm_put;
  861. }
  862. girq->parents[0] = gpio->irq;
  863. girq->default_type = IRQ_TYPE_NONE;
  864. girq->handler = handle_level_irq;
  865. /* report a bug if gpio chip registration fails */
  866. ret = gpiochip_add_data(chip, gpio);
  867. if (ret) {
  868. dev_err(&pdev->dev, "Failed to add gpio chip\n");
  869. goto err_pm_put;
  870. }
  871. irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
  872. device_init_wakeup(&pdev->dev, 1);
  873. pm_runtime_put(&pdev->dev);
  874. return 0;
  875. err_pm_put:
  876. pm_runtime_put(&pdev->dev);
  877. err_pm_dis:
  878. pm_runtime_disable(&pdev->dev);
  879. clk_disable_unprepare(gpio->clk);
  880. return ret;
  881. }
  882. /**
  883. * zynq_gpio_remove - Driver removal function
  884. * @pdev: platform device instance
  885. *
  886. * Return: 0 always
  887. */
  888. static int zynq_gpio_remove(struct platform_device *pdev)
  889. {
  890. struct zynq_gpio *gpio = platform_get_drvdata(pdev);
  891. int ret;
  892. ret = pm_runtime_get_sync(&pdev->dev);
  893. if (ret < 0)
  894. dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");
  895. gpiochip_remove(&gpio->chip);
  896. clk_disable_unprepare(gpio->clk);
  897. device_set_wakeup_capable(&pdev->dev, 0);
  898. pm_runtime_disable(&pdev->dev);
  899. return 0;
  900. }
  901. static struct platform_driver zynq_gpio_driver = {
  902. .driver = {
  903. .name = DRIVER_NAME,
  904. .pm = &zynq_gpio_dev_pm_ops,
  905. .of_match_table = zynq_gpio_of_match,
  906. },
  907. .probe = zynq_gpio_probe,
  908. .remove = zynq_gpio_remove,
  909. };
  910. /**
  911. * zynq_gpio_init - Initial driver registration call
  912. *
  913. * Return: value from platform_driver_register
  914. */
  915. static int __init zynq_gpio_init(void)
  916. {
  917. return platform_driver_register(&zynq_gpio_driver);
  918. }
  919. postcore_initcall(zynq_gpio_init);
  920. static void __exit zynq_gpio_exit(void)
  921. {
  922. platform_driver_unregister(&zynq_gpio_driver);
  923. }
  924. module_exit(zynq_gpio_exit);
  925. MODULE_AUTHOR("Xilinx Inc.");
  926. MODULE_DESCRIPTION("Zynq GPIO driver");
  927. MODULE_LICENSE("GPL");