gpio-xlp.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2003-2015 Broadcom Corporation
  4. * All Rights Reserved
  5. */
  6. #include <linux/gpio/driver.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/of_device.h>
  9. #include <linux/module.h>
  10. #include <linux/irq.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irqchip/chained_irq.h>
  13. #include <linux/acpi.h>
  14. /*
  15. * XLP GPIO has multiple 32 bit registers for each feature where each register
  16. * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
  17. * require 3 32-bit registers for each feature.
  18. * Here we only define offset of the first register for each feature. Offset of
  19. * the registers for pins greater than 32 can be calculated as following(Use
  20. * GPIO_INT_STAT as example):
  21. *
  22. * offset = (gpio / XLP_GPIO_REGSZ) * 4;
  23. * reg_addr = addr + offset;
  24. *
  25. * where addr is base address of the that feature register and gpio is the pin.
  26. */
  27. #define GPIO_OUTPUT_EN 0x00
  28. #define GPIO_PADDRV 0x08
  29. #define GPIO_INT_EN00 0x18
  30. #define GPIO_INT_EN10 0x20
  31. #define GPIO_INT_EN20 0x28
  32. #define GPIO_INT_EN30 0x30
  33. #define GPIO_INT_POL 0x38
  34. #define GPIO_INT_TYPE 0x40
  35. #define GPIO_INT_STAT 0x48
  36. #define GPIO_9XX_BYTESWAP 0X00
  37. #define GPIO_9XX_CTRL 0X04
  38. #define GPIO_9XX_OUTPUT_EN 0x14
  39. #define GPIO_9XX_PADDRV 0x24
  40. /*
  41. * Only for 4 interrupt enable reg are defined for now,
  42. * total reg available are 12.
  43. */
  44. #define GPIO_9XX_INT_EN00 0x44
  45. #define GPIO_9XX_INT_EN10 0x54
  46. #define GPIO_9XX_INT_EN20 0x64
  47. #define GPIO_9XX_INT_EN30 0x74
  48. #define GPIO_9XX_INT_POL 0x104
  49. #define GPIO_9XX_INT_TYPE 0x114
  50. #define GPIO_9XX_INT_STAT 0x124
  51. #define GPIO_3XX_INT_EN00 0x18
  52. #define GPIO_3XX_INT_EN10 0x20
  53. #define GPIO_3XX_INT_EN20 0x28
  54. #define GPIO_3XX_INT_EN30 0x30
  55. #define GPIO_3XX_INT_POL 0x78
  56. #define GPIO_3XX_INT_TYPE 0x80
  57. #define GPIO_3XX_INT_STAT 0x88
  58. /* Interrupt type register mask */
  59. #define XLP_GPIO_IRQ_TYPE_LVL 0x0
  60. #define XLP_GPIO_IRQ_TYPE_EDGE 0x1
  61. /* Interrupt polarity register mask */
  62. #define XLP_GPIO_IRQ_POL_HIGH 0x0
  63. #define XLP_GPIO_IRQ_POL_LOW 0x1
  64. #define XLP_GPIO_REGSZ 32
  65. #define XLP_GPIO_IRQ_BASE 768
  66. #define XLP_MAX_NR_GPIO 96
  67. /* XLP variants supported by this driver */
  68. enum {
  69. XLP_GPIO_VARIANT_XLP832 = 1,
  70. XLP_GPIO_VARIANT_XLP316,
  71. XLP_GPIO_VARIANT_XLP208,
  72. XLP_GPIO_VARIANT_XLP980,
  73. XLP_GPIO_VARIANT_XLP532,
  74. GPIO_VARIANT_VULCAN
  75. };
  76. struct xlp_gpio_priv {
  77. struct gpio_chip chip;
  78. DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
  79. void __iomem *gpio_intr_en; /* pointer to first intr enable reg */
  80. void __iomem *gpio_intr_stat; /* pointer to first intr status reg */
  81. void __iomem *gpio_intr_type; /* pointer to first intr type reg */
  82. void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */
  83. void __iomem *gpio_out_en; /* pointer to first output enable reg */
  84. void __iomem *gpio_paddrv; /* pointer to first pad drive reg */
  85. spinlock_t lock;
  86. };
  87. static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
  88. {
  89. u32 pos, regset;
  90. pos = gpio % XLP_GPIO_REGSZ;
  91. regset = (gpio / XLP_GPIO_REGSZ) * 4;
  92. return !!(readl(addr + regset) & BIT(pos));
  93. }
  94. static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
  95. {
  96. u32 value, pos, regset;
  97. pos = gpio % XLP_GPIO_REGSZ;
  98. regset = (gpio / XLP_GPIO_REGSZ) * 4;
  99. value = readl(addr + regset);
  100. if (state)
  101. value |= BIT(pos);
  102. else
  103. value &= ~BIT(pos);
  104. writel(value, addr + regset);
  105. }
  106. static void xlp_gpio_irq_disable(struct irq_data *d)
  107. {
  108. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  109. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  110. unsigned long flags;
  111. spin_lock_irqsave(&priv->lock, flags);
  112. xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
  113. __clear_bit(d->hwirq, priv->gpio_enabled_mask);
  114. spin_unlock_irqrestore(&priv->lock, flags);
  115. }
  116. static void xlp_gpio_irq_mask_ack(struct irq_data *d)
  117. {
  118. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  119. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  120. unsigned long flags;
  121. spin_lock_irqsave(&priv->lock, flags);
  122. xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
  123. xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
  124. __clear_bit(d->hwirq, priv->gpio_enabled_mask);
  125. spin_unlock_irqrestore(&priv->lock, flags);
  126. }
  127. static void xlp_gpio_irq_unmask(struct irq_data *d)
  128. {
  129. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  130. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  131. unsigned long flags;
  132. spin_lock_irqsave(&priv->lock, flags);
  133. xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
  134. __set_bit(d->hwirq, priv->gpio_enabled_mask);
  135. spin_unlock_irqrestore(&priv->lock, flags);
  136. }
  137. static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  138. {
  139. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  140. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  141. int pol, irq_type;
  142. switch (type) {
  143. case IRQ_TYPE_EDGE_RISING:
  144. irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
  145. pol = XLP_GPIO_IRQ_POL_HIGH;
  146. break;
  147. case IRQ_TYPE_EDGE_FALLING:
  148. irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
  149. pol = XLP_GPIO_IRQ_POL_LOW;
  150. break;
  151. case IRQ_TYPE_LEVEL_HIGH:
  152. irq_type = XLP_GPIO_IRQ_TYPE_LVL;
  153. pol = XLP_GPIO_IRQ_POL_HIGH;
  154. break;
  155. case IRQ_TYPE_LEVEL_LOW:
  156. irq_type = XLP_GPIO_IRQ_TYPE_LVL;
  157. pol = XLP_GPIO_IRQ_POL_LOW;
  158. break;
  159. default:
  160. return -EINVAL;
  161. }
  162. xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
  163. xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
  164. return 0;
  165. }
  166. static struct irq_chip xlp_gpio_irq_chip = {
  167. .name = "XLP-GPIO",
  168. .irq_mask_ack = xlp_gpio_irq_mask_ack,
  169. .irq_disable = xlp_gpio_irq_disable,
  170. .irq_set_type = xlp_gpio_set_irq_type,
  171. .irq_unmask = xlp_gpio_irq_unmask,
  172. .flags = IRQCHIP_ONESHOT_SAFE,
  173. };
  174. static void xlp_gpio_generic_handler(struct irq_desc *desc)
  175. {
  176. struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
  177. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  178. int gpio, regoff;
  179. u32 gpio_stat;
  180. regoff = -1;
  181. gpio_stat = 0;
  182. chained_irq_enter(irqchip, desc);
  183. for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
  184. if (regoff != gpio / XLP_GPIO_REGSZ) {
  185. regoff = gpio / XLP_GPIO_REGSZ;
  186. gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
  187. }
  188. if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
  189. generic_handle_irq(irq_find_mapping(
  190. priv->chip.irq.domain, gpio));
  191. }
  192. chained_irq_exit(irqchip, desc);
  193. }
  194. static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
  195. {
  196. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  197. BUG_ON(gpio >= gc->ngpio);
  198. xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
  199. return 0;
  200. }
  201. static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
  202. {
  203. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  204. BUG_ON(gpio >= gc->ngpio);
  205. xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
  206. return 0;
  207. }
  208. static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
  209. {
  210. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  211. BUG_ON(gpio >= gc->ngpio);
  212. return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
  213. }
  214. static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
  215. {
  216. struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
  217. BUG_ON(gpio >= gc->ngpio);
  218. xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
  219. }
  220. static const struct of_device_id xlp_gpio_of_ids[] = {
  221. {
  222. .compatible = "netlogic,xlp832-gpio",
  223. .data = (void *)XLP_GPIO_VARIANT_XLP832,
  224. },
  225. {
  226. .compatible = "netlogic,xlp316-gpio",
  227. .data = (void *)XLP_GPIO_VARIANT_XLP316,
  228. },
  229. {
  230. .compatible = "netlogic,xlp208-gpio",
  231. .data = (void *)XLP_GPIO_VARIANT_XLP208,
  232. },
  233. {
  234. .compatible = "netlogic,xlp980-gpio",
  235. .data = (void *)XLP_GPIO_VARIANT_XLP980,
  236. },
  237. {
  238. .compatible = "netlogic,xlp532-gpio",
  239. .data = (void *)XLP_GPIO_VARIANT_XLP532,
  240. },
  241. {
  242. .compatible = "brcm,vulcan-gpio",
  243. .data = (void *)GPIO_VARIANT_VULCAN,
  244. },
  245. { /* sentinel */ },
  246. };
  247. MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
  248. static int xlp_gpio_probe(struct platform_device *pdev)
  249. {
  250. struct gpio_chip *gc;
  251. struct gpio_irq_chip *girq;
  252. struct xlp_gpio_priv *priv;
  253. void __iomem *gpio_base;
  254. int irq_base, irq, err;
  255. int ngpio;
  256. u32 soc_type;
  257. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  258. if (!priv)
  259. return -ENOMEM;
  260. gpio_base = devm_platform_ioremap_resource(pdev, 0);
  261. if (IS_ERR(gpio_base))
  262. return PTR_ERR(gpio_base);
  263. irq = platform_get_irq(pdev, 0);
  264. if (irq < 0)
  265. return irq;
  266. if (pdev->dev.of_node) {
  267. soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
  268. } else {
  269. const struct acpi_device_id *acpi_id;
  270. acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
  271. &pdev->dev);
  272. if (!acpi_id || !acpi_id->driver_data) {
  273. dev_err(&pdev->dev, "Unable to match ACPI ID\n");
  274. return -ENODEV;
  275. }
  276. soc_type = (uintptr_t) acpi_id->driver_data;
  277. }
  278. switch (soc_type) {
  279. case XLP_GPIO_VARIANT_XLP832:
  280. priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
  281. priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
  282. priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
  283. priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
  284. priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
  285. priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
  286. ngpio = 41;
  287. break;
  288. case XLP_GPIO_VARIANT_XLP208:
  289. case XLP_GPIO_VARIANT_XLP316:
  290. priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
  291. priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
  292. priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
  293. priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
  294. priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
  295. priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
  296. ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
  297. break;
  298. case XLP_GPIO_VARIANT_XLP980:
  299. case XLP_GPIO_VARIANT_XLP532:
  300. case GPIO_VARIANT_VULCAN:
  301. priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
  302. priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
  303. priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
  304. priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
  305. priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
  306. priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
  307. if (soc_type == XLP_GPIO_VARIANT_XLP980)
  308. ngpio = 66;
  309. else if (soc_type == XLP_GPIO_VARIANT_XLP532)
  310. ngpio = 67;
  311. else
  312. ngpio = 70;
  313. break;
  314. default:
  315. dev_err(&pdev->dev, "Unknown Processor type!\n");
  316. return -ENODEV;
  317. }
  318. bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
  319. gc = &priv->chip;
  320. gc->owner = THIS_MODULE;
  321. gc->label = dev_name(&pdev->dev);
  322. gc->base = 0;
  323. gc->parent = &pdev->dev;
  324. gc->ngpio = ngpio;
  325. gc->of_node = pdev->dev.of_node;
  326. gc->direction_output = xlp_gpio_dir_output;
  327. gc->direction_input = xlp_gpio_dir_input;
  328. gc->set = xlp_gpio_set;
  329. gc->get = xlp_gpio_get;
  330. spin_lock_init(&priv->lock);
  331. /* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
  332. if (soc_type != GPIO_VARIANT_VULCAN) {
  333. irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
  334. XLP_GPIO_IRQ_BASE,
  335. gc->ngpio, 0);
  336. if (irq_base < 0) {
  337. dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
  338. return irq_base;
  339. }
  340. } else {
  341. irq_base = 0;
  342. }
  343. girq = &gc->irq;
  344. girq->chip = &xlp_gpio_irq_chip;
  345. girq->parent_handler = xlp_gpio_generic_handler;
  346. girq->num_parents = 1;
  347. girq->parents = devm_kcalloc(&pdev->dev, 1,
  348. sizeof(*girq->parents),
  349. GFP_KERNEL);
  350. if (!girq->parents)
  351. return -ENOMEM;
  352. girq->parents[0] = irq;
  353. girq->first = irq_base;
  354. girq->default_type = IRQ_TYPE_NONE;
  355. girq->handler = handle_level_irq;
  356. err = gpiochip_add_data(gc, priv);
  357. if (err < 0)
  358. return err;
  359. dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
  360. return 0;
  361. }
  362. #ifdef CONFIG_ACPI
  363. static const struct acpi_device_id xlp_gpio_acpi_match[] = {
  364. { "BRCM9006", GPIO_VARIANT_VULCAN },
  365. { "CAV9006", GPIO_VARIANT_VULCAN },
  366. {},
  367. };
  368. MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
  369. #endif
  370. static struct platform_driver xlp_gpio_driver = {
  371. .driver = {
  372. .name = "xlp-gpio",
  373. .of_match_table = xlp_gpio_of_ids,
  374. .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
  375. },
  376. .probe = xlp_gpio_probe,
  377. };
  378. module_platform_driver(xlp_gpio_driver);
  379. MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
  380. MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
  381. MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
  382. MODULE_LICENSE("GPL v2");