gpio-xilinx.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xilinx gpio driver for xps/axi_gpio IP.
  4. *
  5. * Copyright 2008 - 2013 Xilinx, Inc.
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/init.h>
  9. #include <linux/errno.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/io.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/slab.h>
  16. /* Register Offset Definitions */
  17. #define XGPIO_DATA_OFFSET (0x0) /* Data register */
  18. #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
  19. #define XGPIO_CHANNEL_OFFSET 0x8
  20. /* Read/Write access to the GPIO registers */
  21. #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
  22. # define xgpio_readreg(offset) readl(offset)
  23. # define xgpio_writereg(offset, val) writel(val, offset)
  24. #else
  25. # define xgpio_readreg(offset) __raw_readl(offset)
  26. # define xgpio_writereg(offset, val) __raw_writel(val, offset)
  27. #endif
  28. /**
  29. * struct xgpio_instance - Stores information about GPIO device
  30. * @gc: GPIO chip
  31. * @regs: register block
  32. * @gpio_width: GPIO width for every channel
  33. * @gpio_state: GPIO state shadow register
  34. * @gpio_dir: GPIO direction shadow register
  35. * @gpio_lock: Lock used for synchronization
  36. */
  37. struct xgpio_instance {
  38. struct gpio_chip gc;
  39. void __iomem *regs;
  40. unsigned int gpio_width[2];
  41. u32 gpio_state[2];
  42. u32 gpio_dir[2];
  43. spinlock_t gpio_lock[2];
  44. };
  45. static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
  46. {
  47. if (gpio >= chip->gpio_width[0])
  48. return 1;
  49. return 0;
  50. }
  51. static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
  52. {
  53. if (xgpio_index(chip, gpio))
  54. return XGPIO_CHANNEL_OFFSET;
  55. return 0;
  56. }
  57. static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
  58. {
  59. if (xgpio_index(chip, gpio))
  60. return gpio - chip->gpio_width[0];
  61. return gpio;
  62. }
  63. /**
  64. * xgpio_get - Read the specified signal of the GPIO device.
  65. * @gc: Pointer to gpio_chip device structure.
  66. * @gpio: GPIO signal number.
  67. *
  68. * This function reads the specified signal of the GPIO device.
  69. *
  70. * Return:
  71. * 0 if direction of GPIO signals is set as input otherwise it
  72. * returns negative error value.
  73. */
  74. static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
  75. {
  76. struct xgpio_instance *chip = gpiochip_get_data(gc);
  77. u32 val;
  78. val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
  79. xgpio_regoffset(chip, gpio));
  80. return !!(val & BIT(xgpio_offset(chip, gpio)));
  81. }
  82. /**
  83. * xgpio_set - Write the specified signal of the GPIO device.
  84. * @gc: Pointer to gpio_chip device structure.
  85. * @gpio: GPIO signal number.
  86. * @val: Value to be written to specified signal.
  87. *
  88. * This function writes the specified value in to the specified signal of the
  89. * GPIO device.
  90. */
  91. static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  92. {
  93. unsigned long flags;
  94. struct xgpio_instance *chip = gpiochip_get_data(gc);
  95. int index = xgpio_index(chip, gpio);
  96. int offset = xgpio_offset(chip, gpio);
  97. spin_lock_irqsave(&chip->gpio_lock[index], flags);
  98. /* Write to GPIO signal and set its direction to output */
  99. if (val)
  100. chip->gpio_state[index] |= BIT(offset);
  101. else
  102. chip->gpio_state[index] &= ~BIT(offset);
  103. xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
  104. xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
  105. spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
  106. }
  107. /**
  108. * xgpio_set_multiple - Write the specified signals of the GPIO device.
  109. * @gc: Pointer to gpio_chip device structure.
  110. * @mask: Mask of the GPIOS to modify.
  111. * @bits: Value to be wrote on each GPIO
  112. *
  113. * This function writes the specified values into the specified signals of the
  114. * GPIO devices.
  115. */
  116. static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
  117. unsigned long *bits)
  118. {
  119. unsigned long flags;
  120. struct xgpio_instance *chip = gpiochip_get_data(gc);
  121. int index = xgpio_index(chip, 0);
  122. int offset, i;
  123. spin_lock_irqsave(&chip->gpio_lock[index], flags);
  124. /* Write to GPIO signals */
  125. for (i = 0; i < gc->ngpio; i++) {
  126. if (*mask == 0)
  127. break;
  128. /* Once finished with an index write it out to the register */
  129. if (index != xgpio_index(chip, i)) {
  130. xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
  131. index * XGPIO_CHANNEL_OFFSET,
  132. chip->gpio_state[index]);
  133. spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
  134. index = xgpio_index(chip, i);
  135. spin_lock_irqsave(&chip->gpio_lock[index], flags);
  136. }
  137. if (__test_and_clear_bit(i, mask)) {
  138. offset = xgpio_offset(chip, i);
  139. if (test_bit(i, bits))
  140. chip->gpio_state[index] |= BIT(offset);
  141. else
  142. chip->gpio_state[index] &= ~BIT(offset);
  143. }
  144. }
  145. xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
  146. index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
  147. spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
  148. }
  149. /**
  150. * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
  151. * @gc: Pointer to gpio_chip device structure.
  152. * @gpio: GPIO signal number.
  153. *
  154. * Return:
  155. * 0 - if direction of GPIO signals is set as input
  156. * otherwise it returns negative error value.
  157. */
  158. static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
  159. {
  160. unsigned long flags;
  161. struct xgpio_instance *chip = gpiochip_get_data(gc);
  162. int index = xgpio_index(chip, gpio);
  163. int offset = xgpio_offset(chip, gpio);
  164. spin_lock_irqsave(&chip->gpio_lock[index], flags);
  165. /* Set the GPIO bit in shadow register and set direction as input */
  166. chip->gpio_dir[index] |= BIT(offset);
  167. xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
  168. xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
  169. spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
  170. return 0;
  171. }
  172. /**
  173. * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
  174. * @gc: Pointer to gpio_chip device structure.
  175. * @gpio: GPIO signal number.
  176. * @val: Value to be written to specified signal.
  177. *
  178. * This function sets the direction of specified GPIO signal as output.
  179. *
  180. * Return:
  181. * If all GPIO signals of GPIO chip is configured as input then it returns
  182. * error otherwise it returns 0.
  183. */
  184. static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  185. {
  186. unsigned long flags;
  187. struct xgpio_instance *chip = gpiochip_get_data(gc);
  188. int index = xgpio_index(chip, gpio);
  189. int offset = xgpio_offset(chip, gpio);
  190. spin_lock_irqsave(&chip->gpio_lock[index], flags);
  191. /* Write state of GPIO signal */
  192. if (val)
  193. chip->gpio_state[index] |= BIT(offset);
  194. else
  195. chip->gpio_state[index] &= ~BIT(offset);
  196. xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
  197. xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
  198. /* Clear the GPIO bit in shadow register and set direction as output */
  199. chip->gpio_dir[index] &= ~BIT(offset);
  200. xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
  201. xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
  202. spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
  203. return 0;
  204. }
  205. /**
  206. * xgpio_save_regs - Set initial values of GPIO pins
  207. * @chip: Pointer to GPIO instance
  208. */
  209. static void xgpio_save_regs(struct xgpio_instance *chip)
  210. {
  211. xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]);
  212. xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
  213. if (!chip->gpio_width[1])
  214. return;
  215. xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
  216. chip->gpio_state[1]);
  217. xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
  218. chip->gpio_dir[1]);
  219. }
  220. /**
  221. * xgpio_of_probe - Probe method for the GPIO device.
  222. * @pdev: pointer to the platform device
  223. *
  224. * Return:
  225. * It returns 0, if the driver is bound to the GPIO device, or
  226. * a negative value if there is an error.
  227. */
  228. static int xgpio_probe(struct platform_device *pdev)
  229. {
  230. struct xgpio_instance *chip;
  231. int status = 0;
  232. struct device_node *np = pdev->dev.of_node;
  233. u32 is_dual;
  234. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  235. if (!chip)
  236. return -ENOMEM;
  237. platform_set_drvdata(pdev, chip);
  238. /* Update GPIO state shadow register with default value */
  239. of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
  240. /* Update GPIO direction shadow register with default value */
  241. if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
  242. chip->gpio_dir[0] = 0xFFFFFFFF;
  243. /*
  244. * Check device node and parent device node for device width
  245. * and assume default width of 32
  246. */
  247. if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
  248. chip->gpio_width[0] = 32;
  249. spin_lock_init(&chip->gpio_lock[0]);
  250. if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
  251. is_dual = 0;
  252. if (is_dual) {
  253. /* Update GPIO state shadow register with default value */
  254. of_property_read_u32(np, "xlnx,dout-default-2",
  255. &chip->gpio_state[1]);
  256. /* Update GPIO direction shadow register with default value */
  257. if (of_property_read_u32(np, "xlnx,tri-default-2",
  258. &chip->gpio_dir[1]))
  259. chip->gpio_dir[1] = 0xFFFFFFFF;
  260. /*
  261. * Check device node and parent device node for device width
  262. * and assume default width of 32
  263. */
  264. if (of_property_read_u32(np, "xlnx,gpio2-width",
  265. &chip->gpio_width[1]))
  266. chip->gpio_width[1] = 32;
  267. spin_lock_init(&chip->gpio_lock[1]);
  268. }
  269. chip->gc.base = -1;
  270. chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
  271. chip->gc.parent = &pdev->dev;
  272. chip->gc.direction_input = xgpio_dir_in;
  273. chip->gc.direction_output = xgpio_dir_out;
  274. chip->gc.get = xgpio_get;
  275. chip->gc.set = xgpio_set;
  276. chip->gc.set_multiple = xgpio_set_multiple;
  277. chip->gc.label = dev_name(&pdev->dev);
  278. chip->regs = devm_platform_ioremap_resource(pdev, 0);
  279. if (IS_ERR(chip->regs)) {
  280. dev_err(&pdev->dev, "failed to ioremap memory resource\n");
  281. return PTR_ERR(chip->regs);
  282. }
  283. xgpio_save_regs(chip);
  284. status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
  285. if (status) {
  286. dev_err(&pdev->dev, "failed to add GPIO chip\n");
  287. return status;
  288. }
  289. return 0;
  290. }
  291. static const struct of_device_id xgpio_of_match[] = {
  292. { .compatible = "xlnx,xps-gpio-1.00.a", },
  293. { /* end of list */ },
  294. };
  295. MODULE_DEVICE_TABLE(of, xgpio_of_match);
  296. static struct platform_driver xgpio_plat_driver = {
  297. .probe = xgpio_probe,
  298. .driver = {
  299. .name = "gpio-xilinx",
  300. .of_match_table = xgpio_of_match,
  301. },
  302. };
  303. static int __init xgpio_init(void)
  304. {
  305. return platform_driver_register(&xgpio_plat_driver);
  306. }
  307. subsys_initcall(xgpio_init);
  308. static void __exit xgpio_exit(void)
  309. {
  310. platform_driver_unregister(&xgpio_plat_driver);
  311. }
  312. module_exit(xgpio_exit);
  313. MODULE_AUTHOR("Xilinx, Inc.");
  314. MODULE_DESCRIPTION("Xilinx GPIO driver");
  315. MODULE_LICENSE("GPL");