gpio-xgs-iproc.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 Broadcom
  4. */
  5. #include <linux/gpio/driver.h>
  6. #include <linux/init.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/irq.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/spinlock.h>
  14. #define IPROC_CCA_INT_F_GPIOINT BIT(0)
  15. #define IPROC_CCA_INT_STS 0x20
  16. #define IPROC_CCA_INT_MASK 0x24
  17. #define IPROC_GPIO_CCA_DIN 0x0
  18. #define IPROC_GPIO_CCA_DOUT 0x4
  19. #define IPROC_GPIO_CCA_OUT_EN 0x8
  20. #define IPROC_GPIO_CCA_INT_LEVEL 0x10
  21. #define IPROC_GPIO_CCA_INT_LEVEL_MASK 0x14
  22. #define IPROC_GPIO_CCA_INT_EVENT 0x18
  23. #define IPROC_GPIO_CCA_INT_EVENT_MASK 0x1C
  24. #define IPROC_GPIO_CCA_INT_EDGE 0x24
  25. struct iproc_gpio_chip {
  26. struct irq_chip irqchip;
  27. struct gpio_chip gc;
  28. spinlock_t lock;
  29. struct device *dev;
  30. void __iomem *base;
  31. void __iomem *intr;
  32. };
  33. static inline struct iproc_gpio_chip *
  34. to_iproc_gpio(struct gpio_chip *gc)
  35. {
  36. return container_of(gc, struct iproc_gpio_chip, gc);
  37. }
  38. static void iproc_gpio_irq_ack(struct irq_data *d)
  39. {
  40. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  41. struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
  42. int pin = d->hwirq;
  43. unsigned long flags;
  44. u32 irq = d->irq;
  45. u32 irq_type, event_status = 0;
  46. spin_lock_irqsave(&chip->lock, flags);
  47. irq_type = irq_get_trigger_type(irq);
  48. if (irq_type & IRQ_TYPE_EDGE_BOTH) {
  49. event_status |= BIT(pin);
  50. writel_relaxed(event_status,
  51. chip->base + IPROC_GPIO_CCA_INT_EVENT);
  52. }
  53. spin_unlock_irqrestore(&chip->lock, flags);
  54. }
  55. static void iproc_gpio_irq_unmask(struct irq_data *d)
  56. {
  57. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  58. struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
  59. int pin = d->hwirq;
  60. unsigned long flags;
  61. u32 irq = d->irq;
  62. u32 int_mask, irq_type, event_mask;
  63. spin_lock_irqsave(&chip->lock, flags);
  64. irq_type = irq_get_trigger_type(irq);
  65. event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
  66. int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
  67. if (irq_type & IRQ_TYPE_EDGE_BOTH) {
  68. event_mask |= 1 << pin;
  69. writel_relaxed(event_mask,
  70. chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
  71. } else {
  72. int_mask |= 1 << pin;
  73. writel_relaxed(int_mask,
  74. chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
  75. }
  76. spin_unlock_irqrestore(&chip->lock, flags);
  77. }
  78. static void iproc_gpio_irq_mask(struct irq_data *d)
  79. {
  80. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  81. struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
  82. int pin = d->hwirq;
  83. unsigned long flags;
  84. u32 irq = d->irq;
  85. u32 irq_type, int_mask, event_mask;
  86. spin_lock_irqsave(&chip->lock, flags);
  87. irq_type = irq_get_trigger_type(irq);
  88. event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
  89. int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
  90. if (irq_type & IRQ_TYPE_EDGE_BOTH) {
  91. event_mask &= ~BIT(pin);
  92. writel_relaxed(event_mask,
  93. chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
  94. } else {
  95. int_mask &= ~BIT(pin);
  96. writel_relaxed(int_mask,
  97. chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
  98. }
  99. spin_unlock_irqrestore(&chip->lock, flags);
  100. }
  101. static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type)
  102. {
  103. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  104. struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
  105. int pin = d->hwirq;
  106. unsigned long flags;
  107. u32 irq = d->irq;
  108. u32 event_pol, int_pol;
  109. int ret = 0;
  110. spin_lock_irqsave(&chip->lock, flags);
  111. switch (type & IRQ_TYPE_SENSE_MASK) {
  112. case IRQ_TYPE_EDGE_RISING:
  113. event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
  114. event_pol &= ~BIT(pin);
  115. writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
  116. break;
  117. case IRQ_TYPE_EDGE_FALLING:
  118. event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
  119. event_pol |= BIT(pin);
  120. writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
  121. break;
  122. case IRQ_TYPE_LEVEL_HIGH:
  123. int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
  124. int_pol &= ~BIT(pin);
  125. writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
  126. break;
  127. case IRQ_TYPE_LEVEL_LOW:
  128. int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
  129. int_pol |= BIT(pin);
  130. writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
  131. break;
  132. default:
  133. /* should not come here */
  134. ret = -EINVAL;
  135. goto out_unlock;
  136. }
  137. if (type & IRQ_TYPE_LEVEL_MASK)
  138. irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq);
  139. else if (type & IRQ_TYPE_EDGE_BOTH)
  140. irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq);
  141. out_unlock:
  142. spin_unlock_irqrestore(&chip->lock, flags);
  143. return ret;
  144. }
  145. static irqreturn_t iproc_gpio_irq_handler(int irq, void *data)
  146. {
  147. struct gpio_chip *gc = (struct gpio_chip *)data;
  148. struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
  149. int bit;
  150. unsigned long int_bits = 0;
  151. u32 int_status;
  152. /* go through the entire GPIOs and handle all interrupts */
  153. int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS);
  154. if (int_status & IPROC_CCA_INT_F_GPIOINT) {
  155. u32 event, level;
  156. /* Get level and edge interrupts */
  157. event =
  158. readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
  159. event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT);
  160. level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN);
  161. level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
  162. level &=
  163. readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
  164. int_bits = level | event;
  165. for_each_set_bit(bit, &int_bits, gc->ngpio)
  166. generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
  167. }
  168. return int_bits ? IRQ_HANDLED : IRQ_NONE;
  169. }
  170. static int iproc_gpio_probe(struct platform_device *pdev)
  171. {
  172. struct device *dev = &pdev->dev;
  173. struct device_node *dn = pdev->dev.of_node;
  174. struct iproc_gpio_chip *chip;
  175. u32 num_gpios;
  176. int irq, ret;
  177. chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  178. if (!chip)
  179. return -ENOMEM;
  180. chip->dev = dev;
  181. platform_set_drvdata(pdev, chip);
  182. spin_lock_init(&chip->lock);
  183. chip->base = devm_platform_ioremap_resource(pdev, 0);
  184. if (IS_ERR(chip->base))
  185. return PTR_ERR(chip->base);
  186. ret = bgpio_init(&chip->gc, dev, 4,
  187. chip->base + IPROC_GPIO_CCA_DIN,
  188. chip->base + IPROC_GPIO_CCA_DOUT,
  189. NULL,
  190. chip->base + IPROC_GPIO_CCA_OUT_EN,
  191. NULL,
  192. 0);
  193. if (ret) {
  194. dev_err(dev, "unable to init GPIO chip\n");
  195. return ret;
  196. }
  197. chip->gc.label = dev_name(dev);
  198. if (!of_property_read_u32(dn, "ngpios", &num_gpios))
  199. chip->gc.ngpio = num_gpios;
  200. irq = platform_get_irq(pdev, 0);
  201. if (irq > 0) {
  202. struct gpio_irq_chip *girq;
  203. struct irq_chip *irqc;
  204. u32 val;
  205. irqc = &chip->irqchip;
  206. irqc->name = dev_name(dev);
  207. irqc->irq_ack = iproc_gpio_irq_ack;
  208. irqc->irq_mask = iproc_gpio_irq_mask;
  209. irqc->irq_unmask = iproc_gpio_irq_unmask;
  210. irqc->irq_set_type = iproc_gpio_irq_set_type;
  211. chip->intr = devm_platform_ioremap_resource(pdev, 1);
  212. if (IS_ERR(chip->intr))
  213. return PTR_ERR(chip->intr);
  214. /* Enable GPIO interrupts for CCA GPIO */
  215. val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
  216. val |= IPROC_CCA_INT_F_GPIOINT;
  217. writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
  218. /*
  219. * Directly request the irq here instead of passing
  220. * a flow-handler because the irq is shared.
  221. */
  222. ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
  223. IRQF_SHARED, chip->gc.label, &chip->gc);
  224. if (ret) {
  225. dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret);
  226. return ret;
  227. }
  228. girq = &chip->gc.irq;
  229. girq->chip = irqc;
  230. /* This will let us handle the parent IRQ in the driver */
  231. girq->parent_handler = NULL;
  232. girq->num_parents = 0;
  233. girq->parents = NULL;
  234. girq->default_type = IRQ_TYPE_NONE;
  235. girq->handler = handle_simple_irq;
  236. }
  237. ret = devm_gpiochip_add_data(dev, &chip->gc, chip);
  238. if (ret) {
  239. dev_err(dev, "unable to add GPIO chip\n");
  240. return ret;
  241. }
  242. return 0;
  243. }
  244. static int iproc_gpio_remove(struct platform_device *pdev)
  245. {
  246. struct iproc_gpio_chip *chip;
  247. chip = platform_get_drvdata(pdev);
  248. if (!chip)
  249. return -ENODEV;
  250. if (chip->intr) {
  251. u32 val;
  252. val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
  253. val &= ~IPROC_CCA_INT_F_GPIOINT;
  254. writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
  255. }
  256. return 0;
  257. }
  258. static const struct of_device_id bcm_iproc_gpio_of_match[] = {
  259. { .compatible = "brcm,iproc-gpio-cca" },
  260. {}
  261. };
  262. MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match);
  263. static struct platform_driver bcm_iproc_gpio_driver = {
  264. .driver = {
  265. .name = "iproc-xgs-gpio",
  266. .of_match_table = bcm_iproc_gpio_of_match,
  267. },
  268. .probe = iproc_gpio_probe,
  269. .remove = iproc_gpio_remove,
  270. };
  271. module_platform_driver(bcm_iproc_gpio_driver);
  272. MODULE_DESCRIPTION("XGS IPROC GPIO driver");
  273. MODULE_LICENSE("GPL v2");