gpio-xgene-sb.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * AppliedMicro X-Gene SoC GPIO-Standby Driver
  4. *
  5. * Copyright (c) 2014, Applied Micro Circuits Corporation
  6. * Author: Tin Huynh <tnhuynh@apm.com>.
  7. * Y Vo <yvo@apm.com>.
  8. * Quan Nguyen <qnguyen@apm.com>.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/acpi.h>
  16. #include "gpiolib.h"
  17. #include "gpiolib-acpi.h"
  18. /* Common property names */
  19. #define XGENE_NIRQ_PROPERTY "apm,nr-irqs"
  20. #define XGENE_NGPIO_PROPERTY "apm,nr-gpios"
  21. #define XGENE_IRQ_START_PROPERTY "apm,irq-start"
  22. #define XGENE_DFLT_MAX_NGPIO 22
  23. #define XGENE_DFLT_MAX_NIRQ 6
  24. #define XGENE_DFLT_IRQ_START_PIN 8
  25. #define GPIO_MASK(x) (1U << ((x) % 32))
  26. #define MPA_GPIO_INT_LVL 0x0290
  27. #define MPA_GPIO_OE_ADDR 0x029c
  28. #define MPA_GPIO_OUT_ADDR 0x02a0
  29. #define MPA_GPIO_IN_ADDR 0x02a4
  30. #define MPA_GPIO_SEL_LO 0x0294
  31. #define GPIO_INT_LEVEL_H 0x000001
  32. #define GPIO_INT_LEVEL_L 0x000000
  33. /**
  34. * struct xgene_gpio_sb - GPIO-Standby private data structure.
  35. * @gc: memory-mapped GPIO controllers.
  36. * @regs: GPIO register base offset
  37. * @irq_domain: GPIO interrupt domain
  38. * @irq_start: GPIO pin that start support interrupt
  39. * @nirq: Number of GPIO pins that supports interrupt
  40. * @parent_irq_base: Start parent HWIRQ
  41. */
  42. struct xgene_gpio_sb {
  43. struct gpio_chip gc;
  44. void __iomem *regs;
  45. struct irq_domain *irq_domain;
  46. u16 irq_start;
  47. u16 nirq;
  48. u16 parent_irq_base;
  49. };
  50. #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
  51. #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
  52. static void xgene_gpio_set_bit(struct gpio_chip *gc,
  53. void __iomem *reg, u32 gpio, int val)
  54. {
  55. u32 data;
  56. data = gc->read_reg(reg);
  57. if (val)
  58. data |= GPIO_MASK(gpio);
  59. else
  60. data &= ~GPIO_MASK(gpio);
  61. gc->write_reg(reg, data);
  62. }
  63. static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
  64. {
  65. struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
  66. int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
  67. int lvl_type = GPIO_INT_LEVEL_H;
  68. switch (type & IRQ_TYPE_SENSE_MASK) {
  69. case IRQ_TYPE_EDGE_RISING:
  70. case IRQ_TYPE_LEVEL_HIGH:
  71. lvl_type = GPIO_INT_LEVEL_H;
  72. break;
  73. case IRQ_TYPE_EDGE_FALLING:
  74. case IRQ_TYPE_LEVEL_LOW:
  75. lvl_type = GPIO_INT_LEVEL_L;
  76. break;
  77. default:
  78. break;
  79. }
  80. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
  81. gpio * 2, 1);
  82. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
  83. d->hwirq, lvl_type);
  84. /* Propagate IRQ type setting to parent */
  85. if (type & IRQ_TYPE_EDGE_BOTH)
  86. return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
  87. else
  88. return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
  89. }
  90. static struct irq_chip xgene_gpio_sb_irq_chip = {
  91. .name = "sbgpio",
  92. .irq_eoi = irq_chip_eoi_parent,
  93. .irq_mask = irq_chip_mask_parent,
  94. .irq_unmask = irq_chip_unmask_parent,
  95. .irq_set_type = xgene_gpio_sb_irq_set_type,
  96. };
  97. static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
  98. {
  99. struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
  100. struct irq_fwspec fwspec;
  101. if ((gpio < priv->irq_start) ||
  102. (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
  103. return -ENXIO;
  104. fwspec.fwnode = gc->parent->fwnode;
  105. fwspec.param_count = 2;
  106. fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
  107. fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
  108. return irq_create_fwspec_mapping(&fwspec);
  109. }
  110. static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
  111. struct irq_data *irq_data,
  112. bool reserve)
  113. {
  114. struct xgene_gpio_sb *priv = d->host_data;
  115. u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
  116. int ret;
  117. ret = gpiochip_lock_as_irq(&priv->gc, gpio);
  118. if (ret) {
  119. dev_err(priv->gc.parent,
  120. "Unable to configure XGene GPIO standby pin %d as IRQ\n",
  121. gpio);
  122. return ret;
  123. }
  124. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
  125. gpio * 2, 1);
  126. return 0;
  127. }
  128. static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
  129. struct irq_data *irq_data)
  130. {
  131. struct xgene_gpio_sb *priv = d->host_data;
  132. u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
  133. gpiochip_unlock_as_irq(&priv->gc, gpio);
  134. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
  135. gpio * 2, 0);
  136. }
  137. static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
  138. struct irq_fwspec *fwspec,
  139. unsigned long *hwirq,
  140. unsigned int *type)
  141. {
  142. struct xgene_gpio_sb *priv = d->host_data;
  143. if ((fwspec->param_count != 2) ||
  144. (fwspec->param[0] >= priv->nirq))
  145. return -EINVAL;
  146. *hwirq = fwspec->param[0];
  147. *type = fwspec->param[1];
  148. return 0;
  149. }
  150. static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
  151. unsigned int virq,
  152. unsigned int nr_irqs, void *data)
  153. {
  154. struct irq_fwspec *fwspec = data;
  155. struct irq_fwspec parent_fwspec;
  156. struct xgene_gpio_sb *priv = domain->host_data;
  157. irq_hw_number_t hwirq;
  158. unsigned int i;
  159. hwirq = fwspec->param[0];
  160. for (i = 0; i < nr_irqs; i++)
  161. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  162. &xgene_gpio_sb_irq_chip, priv);
  163. parent_fwspec.fwnode = domain->parent->fwnode;
  164. if (is_of_node(parent_fwspec.fwnode)) {
  165. parent_fwspec.param_count = 3;
  166. parent_fwspec.param[0] = 0;/* SPI */
  167. /* Skip SGIs and PPIs*/
  168. parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
  169. parent_fwspec.param[2] = fwspec->param[1];
  170. } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
  171. parent_fwspec.param_count = 2;
  172. parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
  173. parent_fwspec.param[1] = fwspec->param[1];
  174. } else
  175. return -EINVAL;
  176. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  177. &parent_fwspec);
  178. }
  179. static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
  180. .translate = xgene_gpio_sb_domain_translate,
  181. .alloc = xgene_gpio_sb_domain_alloc,
  182. .free = irq_domain_free_irqs_common,
  183. .activate = xgene_gpio_sb_domain_activate,
  184. .deactivate = xgene_gpio_sb_domain_deactivate,
  185. };
  186. static int xgene_gpio_sb_probe(struct platform_device *pdev)
  187. {
  188. struct xgene_gpio_sb *priv;
  189. int ret;
  190. void __iomem *regs;
  191. struct irq_domain *parent_domain = NULL;
  192. u32 val32;
  193. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  194. if (!priv)
  195. return -ENOMEM;
  196. regs = devm_platform_ioremap_resource(pdev, 0);
  197. if (IS_ERR(regs))
  198. return PTR_ERR(regs);
  199. priv->regs = regs;
  200. ret = platform_get_irq(pdev, 0);
  201. if (ret > 0) {
  202. priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
  203. parent_domain = irq_get_irq_data(ret)->domain;
  204. }
  205. if (!parent_domain) {
  206. dev_err(&pdev->dev, "unable to obtain parent domain\n");
  207. return -ENODEV;
  208. }
  209. ret = bgpio_init(&priv->gc, &pdev->dev, 4,
  210. regs + MPA_GPIO_IN_ADDR,
  211. regs + MPA_GPIO_OUT_ADDR, NULL,
  212. regs + MPA_GPIO_OE_ADDR, NULL, 0);
  213. if (ret)
  214. return ret;
  215. priv->gc.to_irq = xgene_gpio_sb_to_irq;
  216. /* Retrieve start irq pin, use default if property not found */
  217. priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
  218. if (!device_property_read_u32(&pdev->dev,
  219. XGENE_IRQ_START_PROPERTY, &val32))
  220. priv->irq_start = val32;
  221. /* Retrieve number irqs, use default if property not found */
  222. priv->nirq = XGENE_DFLT_MAX_NIRQ;
  223. if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
  224. priv->nirq = val32;
  225. /* Retrieve number gpio, use default if property not found */
  226. priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
  227. if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
  228. priv->gc.ngpio = val32;
  229. dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
  230. priv->gc.ngpio, priv->nirq, priv->irq_start);
  231. platform_set_drvdata(pdev, priv);
  232. priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
  233. 0, priv->nirq, pdev->dev.fwnode,
  234. &xgene_gpio_sb_domain_ops, priv);
  235. if (!priv->irq_domain)
  236. return -ENODEV;
  237. priv->gc.irq.domain = priv->irq_domain;
  238. ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
  239. if (ret) {
  240. dev_err(&pdev->dev,
  241. "failed to register X-Gene GPIO Standby driver\n");
  242. irq_domain_remove(priv->irq_domain);
  243. return ret;
  244. }
  245. dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
  246. /* Register interrupt handlers for GPIO signaled ACPI Events */
  247. acpi_gpiochip_request_interrupts(&priv->gc);
  248. return ret;
  249. }
  250. static int xgene_gpio_sb_remove(struct platform_device *pdev)
  251. {
  252. struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
  253. acpi_gpiochip_free_interrupts(&priv->gc);
  254. irq_domain_remove(priv->irq_domain);
  255. return 0;
  256. }
  257. static const struct of_device_id xgene_gpio_sb_of_match[] = {
  258. {.compatible = "apm,xgene-gpio-sb", },
  259. {},
  260. };
  261. MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
  262. #ifdef CONFIG_ACPI
  263. static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
  264. {"APMC0D15", 0},
  265. {},
  266. };
  267. MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
  268. #endif
  269. static struct platform_driver xgene_gpio_sb_driver = {
  270. .driver = {
  271. .name = "xgene-gpio-sb",
  272. .of_match_table = xgene_gpio_sb_of_match,
  273. .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
  274. },
  275. .probe = xgene_gpio_sb_probe,
  276. .remove = xgene_gpio_sb_remove,
  277. };
  278. module_platform_driver(xgene_gpio_sb_driver);
  279. MODULE_AUTHOR("AppliedMicro");
  280. MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
  281. MODULE_LICENSE("GPL");