gpio-ws16c48.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPIO driver for the WinSystems WS16C48
  4. * Copyright (C) 2016 William Breathitt Gray
  5. */
  6. #include <linux/bitmap.h>
  7. #include <linux/bitops.h>
  8. #include <linux/device.h>
  9. #include <linux/errno.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/io.h>
  12. #include <linux/ioport.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irqdesc.h>
  15. #include <linux/isa.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/spinlock.h>
  20. #define WS16C48_EXTENT 16
  21. #define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
  22. static unsigned int base[MAX_NUM_WS16C48];
  23. static unsigned int num_ws16c48;
  24. module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
  25. MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
  26. static unsigned int irq[MAX_NUM_WS16C48];
  27. module_param_hw_array(irq, uint, irq, NULL, 0);
  28. MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
  29. /**
  30. * struct ws16c48_gpio - GPIO device private data structure
  31. * @chip: instance of the gpio_chip
  32. * @io_state: bit I/O state (whether bit is set to input or output)
  33. * @out_state: output bits state
  34. * @lock: synchronization lock to prevent I/O race conditions
  35. * @irq_mask: I/O bits affected by interrupts
  36. * @flow_mask: IRQ flow type mask for the respective I/O bits
  37. * @base: base port address of the GPIO device
  38. */
  39. struct ws16c48_gpio {
  40. struct gpio_chip chip;
  41. unsigned char io_state[6];
  42. unsigned char out_state[6];
  43. raw_spinlock_t lock;
  44. unsigned long irq_mask;
  45. unsigned long flow_mask;
  46. unsigned base;
  47. };
  48. static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  49. {
  50. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  51. const unsigned port = offset / 8;
  52. const unsigned mask = BIT(offset % 8);
  53. if (ws16c48gpio->io_state[port] & mask)
  54. return GPIO_LINE_DIRECTION_IN;
  55. return GPIO_LINE_DIRECTION_OUT;
  56. }
  57. static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  58. {
  59. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  60. const unsigned port = offset / 8;
  61. const unsigned mask = BIT(offset % 8);
  62. unsigned long flags;
  63. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  64. ws16c48gpio->io_state[port] |= mask;
  65. ws16c48gpio->out_state[port] &= ~mask;
  66. outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
  67. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  68. return 0;
  69. }
  70. static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
  71. unsigned offset, int value)
  72. {
  73. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  74. const unsigned port = offset / 8;
  75. const unsigned mask = BIT(offset % 8);
  76. unsigned long flags;
  77. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  78. ws16c48gpio->io_state[port] &= ~mask;
  79. if (value)
  80. ws16c48gpio->out_state[port] |= mask;
  81. else
  82. ws16c48gpio->out_state[port] &= ~mask;
  83. outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
  84. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  85. return 0;
  86. }
  87. static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
  88. {
  89. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  90. const unsigned port = offset / 8;
  91. const unsigned mask = BIT(offset % 8);
  92. unsigned long flags;
  93. unsigned port_state;
  94. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  95. /* ensure that GPIO is set for input */
  96. if (!(ws16c48gpio->io_state[port] & mask)) {
  97. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  98. return -EINVAL;
  99. }
  100. port_state = inb(ws16c48gpio->base + port);
  101. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  102. return !!(port_state & mask);
  103. }
  104. static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
  105. unsigned long *mask, unsigned long *bits)
  106. {
  107. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  108. unsigned long offset;
  109. unsigned long gpio_mask;
  110. unsigned int port_addr;
  111. unsigned long port_state;
  112. /* clear bits array to a clean slate */
  113. bitmap_zero(bits, chip->ngpio);
  114. for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
  115. port_addr = ws16c48gpio->base + offset / 8;
  116. port_state = inb(port_addr) & gpio_mask;
  117. bitmap_set_value8(bits, port_state, offset);
  118. }
  119. return 0;
  120. }
  121. static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  122. {
  123. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  124. const unsigned port = offset / 8;
  125. const unsigned mask = BIT(offset % 8);
  126. unsigned long flags;
  127. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  128. /* ensure that GPIO is set for output */
  129. if (ws16c48gpio->io_state[port] & mask) {
  130. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  131. return;
  132. }
  133. if (value)
  134. ws16c48gpio->out_state[port] |= mask;
  135. else
  136. ws16c48gpio->out_state[port] &= ~mask;
  137. outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
  138. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  139. }
  140. static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
  141. unsigned long *mask, unsigned long *bits)
  142. {
  143. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  144. unsigned long offset;
  145. unsigned long gpio_mask;
  146. size_t index;
  147. unsigned int port_addr;
  148. unsigned long bitmask;
  149. unsigned long flags;
  150. for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
  151. index = offset / 8;
  152. port_addr = ws16c48gpio->base + index;
  153. /* mask out GPIO configured for input */
  154. gpio_mask &= ~ws16c48gpio->io_state[index];
  155. bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
  156. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  157. /* update output state data and set device gpio register */
  158. ws16c48gpio->out_state[index] &= ~gpio_mask;
  159. ws16c48gpio->out_state[index] |= bitmask;
  160. outb(ws16c48gpio->out_state[index], port_addr);
  161. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  162. }
  163. }
  164. static void ws16c48_irq_ack(struct irq_data *data)
  165. {
  166. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  167. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  168. const unsigned long offset = irqd_to_hwirq(data);
  169. const unsigned port = offset / 8;
  170. const unsigned mask = BIT(offset % 8);
  171. unsigned long flags;
  172. unsigned port_state;
  173. /* only the first 3 ports support interrupts */
  174. if (port > 2)
  175. return;
  176. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  177. port_state = ws16c48gpio->irq_mask >> (8*port);
  178. outb(0x80, ws16c48gpio->base + 7);
  179. outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
  180. outb(port_state | mask, ws16c48gpio->base + 8 + port);
  181. outb(0xC0, ws16c48gpio->base + 7);
  182. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  183. }
  184. static void ws16c48_irq_mask(struct irq_data *data)
  185. {
  186. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  187. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  188. const unsigned long offset = irqd_to_hwirq(data);
  189. const unsigned long mask = BIT(offset);
  190. const unsigned port = offset / 8;
  191. unsigned long flags;
  192. /* only the first 3 ports support interrupts */
  193. if (port > 2)
  194. return;
  195. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  196. ws16c48gpio->irq_mask &= ~mask;
  197. outb(0x80, ws16c48gpio->base + 7);
  198. outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
  199. outb(0xC0, ws16c48gpio->base + 7);
  200. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  201. }
  202. static void ws16c48_irq_unmask(struct irq_data *data)
  203. {
  204. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  205. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  206. const unsigned long offset = irqd_to_hwirq(data);
  207. const unsigned long mask = BIT(offset);
  208. const unsigned port = offset / 8;
  209. unsigned long flags;
  210. /* only the first 3 ports support interrupts */
  211. if (port > 2)
  212. return;
  213. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  214. ws16c48gpio->irq_mask |= mask;
  215. outb(0x80, ws16c48gpio->base + 7);
  216. outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
  217. outb(0xC0, ws16c48gpio->base + 7);
  218. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  219. }
  220. static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
  221. {
  222. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  223. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
  224. const unsigned long offset = irqd_to_hwirq(data);
  225. const unsigned long mask = BIT(offset);
  226. const unsigned port = offset / 8;
  227. unsigned long flags;
  228. /* only the first 3 ports support interrupts */
  229. if (port > 2)
  230. return -EINVAL;
  231. raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
  232. switch (flow_type) {
  233. case IRQ_TYPE_NONE:
  234. break;
  235. case IRQ_TYPE_EDGE_RISING:
  236. ws16c48gpio->flow_mask |= mask;
  237. break;
  238. case IRQ_TYPE_EDGE_FALLING:
  239. ws16c48gpio->flow_mask &= ~mask;
  240. break;
  241. default:
  242. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  243. return -EINVAL;
  244. }
  245. outb(0x40, ws16c48gpio->base + 7);
  246. outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
  247. outb(0xC0, ws16c48gpio->base + 7);
  248. raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
  249. return 0;
  250. }
  251. static struct irq_chip ws16c48_irqchip = {
  252. .name = "ws16c48",
  253. .irq_ack = ws16c48_irq_ack,
  254. .irq_mask = ws16c48_irq_mask,
  255. .irq_unmask = ws16c48_irq_unmask,
  256. .irq_set_type = ws16c48_irq_set_type
  257. };
  258. static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
  259. {
  260. struct ws16c48_gpio *const ws16c48gpio = dev_id;
  261. struct gpio_chip *const chip = &ws16c48gpio->chip;
  262. unsigned long int_pending;
  263. unsigned long port;
  264. unsigned long int_id;
  265. unsigned long gpio;
  266. int_pending = inb(ws16c48gpio->base + 6) & 0x7;
  267. if (!int_pending)
  268. return IRQ_NONE;
  269. /* loop until all pending interrupts are handled */
  270. do {
  271. for_each_set_bit(port, &int_pending, 3) {
  272. int_id = inb(ws16c48gpio->base + 8 + port);
  273. for_each_set_bit(gpio, &int_id, 8)
  274. generic_handle_irq(irq_find_mapping(
  275. chip->irq.domain, gpio + 8*port));
  276. }
  277. int_pending = inb(ws16c48gpio->base + 6) & 0x7;
  278. } while (int_pending);
  279. return IRQ_HANDLED;
  280. }
  281. #define WS16C48_NGPIO 48
  282. static const char *ws16c48_names[WS16C48_NGPIO] = {
  283. "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
  284. "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
  285. "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
  286. "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
  287. "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
  288. "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
  289. "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
  290. "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
  291. "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
  292. "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
  293. "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
  294. "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
  295. };
  296. static int ws16c48_irq_init_hw(struct gpio_chip *gc)
  297. {
  298. struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
  299. /* Disable IRQ by default */
  300. outb(0x80, ws16c48gpio->base + 7);
  301. outb(0, ws16c48gpio->base + 8);
  302. outb(0, ws16c48gpio->base + 9);
  303. outb(0, ws16c48gpio->base + 10);
  304. outb(0xC0, ws16c48gpio->base + 7);
  305. return 0;
  306. }
  307. static int ws16c48_probe(struct device *dev, unsigned int id)
  308. {
  309. struct ws16c48_gpio *ws16c48gpio;
  310. const char *const name = dev_name(dev);
  311. struct gpio_irq_chip *girq;
  312. int err;
  313. ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
  314. if (!ws16c48gpio)
  315. return -ENOMEM;
  316. if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
  317. dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
  318. base[id], base[id] + WS16C48_EXTENT);
  319. return -EBUSY;
  320. }
  321. ws16c48gpio->chip.label = name;
  322. ws16c48gpio->chip.parent = dev;
  323. ws16c48gpio->chip.owner = THIS_MODULE;
  324. ws16c48gpio->chip.base = -1;
  325. ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
  326. ws16c48gpio->chip.names = ws16c48_names;
  327. ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
  328. ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
  329. ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
  330. ws16c48gpio->chip.get = ws16c48_gpio_get;
  331. ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
  332. ws16c48gpio->chip.set = ws16c48_gpio_set;
  333. ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
  334. ws16c48gpio->base = base[id];
  335. girq = &ws16c48gpio->chip.irq;
  336. girq->chip = &ws16c48_irqchip;
  337. /* This will let us handle the parent IRQ in the driver */
  338. girq->parent_handler = NULL;
  339. girq->num_parents = 0;
  340. girq->parents = NULL;
  341. girq->default_type = IRQ_TYPE_NONE;
  342. girq->handler = handle_edge_irq;
  343. girq->init_hw = ws16c48_irq_init_hw;
  344. raw_spin_lock_init(&ws16c48gpio->lock);
  345. err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
  346. if (err) {
  347. dev_err(dev, "GPIO registering failed (%d)\n", err);
  348. return err;
  349. }
  350. err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
  351. name, ws16c48gpio);
  352. if (err) {
  353. dev_err(dev, "IRQ handler registering failed (%d)\n", err);
  354. return err;
  355. }
  356. return 0;
  357. }
  358. static struct isa_driver ws16c48_driver = {
  359. .probe = ws16c48_probe,
  360. .driver = {
  361. .name = "ws16c48"
  362. },
  363. };
  364. module_isa_driver(ws16c48_driver, num_ws16c48);
  365. MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
  366. MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
  367. MODULE_LICENSE("GPL v2");