gpio-wcove.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Whiskey Cove PMIC GPIO Driver
  4. *
  5. * This driver is written based on gpio-crystalcove.c
  6. *
  7. * Copyright (C) 2016 Intel Corporation. All rights reserved.
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/mfd/intel_soc_pmic.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/seq_file.h>
  17. /*
  18. * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
  19. * Bank 0: Pin 0 - 6
  20. * Bank 1: Pin 7 - 10
  21. * Bank 2: Pin 11 - 12
  22. * Each pin has one output control register and one input control register.
  23. */
  24. #define BANK0_NR_PINS 7
  25. #define BANK1_NR_PINS 4
  26. #define BANK2_NR_PINS 2
  27. #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
  28. #define WCOVE_VGPIO_NUM 94
  29. /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
  30. #define GPIO_OUT_CTRL_BASE 0x4e44
  31. /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
  32. #define GPIO_IN_CTRL_BASE 0x4e51
  33. /*
  34. * GPIO interrupts are organized in two groups:
  35. * Group 0: Bank 0 pins (Pin 0 - 6)
  36. * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
  37. * Each group has two registers (one bit per pin): status and mask.
  38. */
  39. #define GROUP0_NR_IRQS 7
  40. #define GROUP1_NR_IRQS 6
  41. #define IRQ_MASK_BASE 0x4e19
  42. #define IRQ_STATUS_BASE 0x4e0b
  43. #define GPIO_IRQ0_MASK GENMASK(6, 0)
  44. #define GPIO_IRQ1_MASK GENMASK(5, 0)
  45. #define UPDATE_IRQ_TYPE BIT(0)
  46. #define UPDATE_IRQ_MASK BIT(1)
  47. #define CTLI_INTCNT_DIS (0 << 1)
  48. #define CTLI_INTCNT_NE (1 << 1)
  49. #define CTLI_INTCNT_PE (2 << 1)
  50. #define CTLI_INTCNT_BE (3 << 1)
  51. #define CTLO_DIR_IN (0 << 5)
  52. #define CTLO_DIR_OUT (1 << 5)
  53. #define CTLO_DRV_MASK (1 << 4)
  54. #define CTLO_DRV_OD (0 << 4)
  55. #define CTLO_DRV_CMOS (1 << 4)
  56. #define CTLO_DRV_REN (1 << 3)
  57. #define CTLO_RVAL_2KDOWN (0 << 1)
  58. #define CTLO_RVAL_2KUP (1 << 1)
  59. #define CTLO_RVAL_50KDOWN (2 << 1)
  60. #define CTLO_RVAL_50KUP (3 << 1)
  61. #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  62. #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  63. enum ctrl_register {
  64. CTRL_IN,
  65. CTRL_OUT,
  66. };
  67. /*
  68. * struct wcove_gpio - Whiskey Cove GPIO controller
  69. * @buslock: for bus lock/sync and unlock.
  70. * @chip: the abstract gpio_chip structure.
  71. * @dev: the gpio device
  72. * @regmap: the regmap from the parent device.
  73. * @regmap_irq_chip: the regmap of the gpio irq chip.
  74. * @update: pending IRQ setting update, to be written to the chip upon unlock.
  75. * @intcnt: the Interrupt Detect value to be written.
  76. * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  77. */
  78. struct wcove_gpio {
  79. struct mutex buslock;
  80. struct gpio_chip chip;
  81. struct device *dev;
  82. struct regmap *regmap;
  83. struct regmap_irq_chip_data *regmap_irq_chip;
  84. int update;
  85. int intcnt;
  86. bool set_irq_mask;
  87. };
  88. static inline int to_reg(int gpio, enum ctrl_register reg_type)
  89. {
  90. unsigned int reg;
  91. if (gpio >= WCOVE_GPIO_NUM)
  92. return -EOPNOTSUPP;
  93. if (reg_type == CTRL_IN)
  94. reg = GPIO_IN_CTRL_BASE + gpio;
  95. else
  96. reg = GPIO_OUT_CTRL_BASE + gpio;
  97. return reg;
  98. }
  99. static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
  100. {
  101. unsigned int reg, mask;
  102. if (gpio < GROUP0_NR_IRQS) {
  103. reg = IRQ_MASK_BASE;
  104. mask = BIT(gpio % GROUP0_NR_IRQS);
  105. } else {
  106. reg = IRQ_MASK_BASE + 1;
  107. mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
  108. }
  109. if (wg->set_irq_mask)
  110. regmap_update_bits(wg->regmap, reg, mask, mask);
  111. else
  112. regmap_update_bits(wg->regmap, reg, mask, 0);
  113. }
  114. static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
  115. {
  116. int reg = to_reg(gpio, CTRL_IN);
  117. if (reg < 0)
  118. return;
  119. regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
  120. }
  121. static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
  122. {
  123. struct wcove_gpio *wg = gpiochip_get_data(chip);
  124. int reg = to_reg(gpio, CTRL_OUT);
  125. if (reg < 0)
  126. return 0;
  127. return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
  128. }
  129. static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
  130. int value)
  131. {
  132. struct wcove_gpio *wg = gpiochip_get_data(chip);
  133. int reg = to_reg(gpio, CTRL_OUT);
  134. if (reg < 0)
  135. return 0;
  136. return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
  137. }
  138. static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
  139. {
  140. struct wcove_gpio *wg = gpiochip_get_data(chip);
  141. unsigned int val;
  142. int ret, reg = to_reg(gpio, CTRL_OUT);
  143. if (reg < 0)
  144. return GPIO_LINE_DIRECTION_OUT;
  145. ret = regmap_read(wg->regmap, reg, &val);
  146. if (ret)
  147. return ret;
  148. if (val & CTLO_DIR_OUT)
  149. return GPIO_LINE_DIRECTION_OUT;
  150. return GPIO_LINE_DIRECTION_IN;
  151. }
  152. static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
  153. {
  154. struct wcove_gpio *wg = gpiochip_get_data(chip);
  155. unsigned int val;
  156. int ret, reg = to_reg(gpio, CTRL_IN);
  157. if (reg < 0)
  158. return 0;
  159. ret = regmap_read(wg->regmap, reg, &val);
  160. if (ret)
  161. return ret;
  162. return val & 0x1;
  163. }
  164. static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
  165. {
  166. struct wcove_gpio *wg = gpiochip_get_data(chip);
  167. int reg = to_reg(gpio, CTRL_OUT);
  168. if (reg < 0)
  169. return;
  170. if (value)
  171. regmap_update_bits(wg->regmap, reg, 1, 1);
  172. else
  173. regmap_update_bits(wg->regmap, reg, 1, 0);
  174. }
  175. static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
  176. unsigned long config)
  177. {
  178. struct wcove_gpio *wg = gpiochip_get_data(chip);
  179. int reg = to_reg(gpio, CTRL_OUT);
  180. if (reg < 0)
  181. return 0;
  182. switch (pinconf_to_config_param(config)) {
  183. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  184. return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
  185. CTLO_DRV_OD);
  186. case PIN_CONFIG_DRIVE_PUSH_PULL:
  187. return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
  188. CTLO_DRV_CMOS);
  189. default:
  190. break;
  191. }
  192. return -ENOTSUPP;
  193. }
  194. static int wcove_irq_type(struct irq_data *data, unsigned int type)
  195. {
  196. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  197. struct wcove_gpio *wg = gpiochip_get_data(chip);
  198. if (data->hwirq >= WCOVE_GPIO_NUM)
  199. return 0;
  200. switch (type) {
  201. case IRQ_TYPE_NONE:
  202. wg->intcnt = CTLI_INTCNT_DIS;
  203. break;
  204. case IRQ_TYPE_EDGE_BOTH:
  205. wg->intcnt = CTLI_INTCNT_BE;
  206. break;
  207. case IRQ_TYPE_EDGE_RISING:
  208. wg->intcnt = CTLI_INTCNT_PE;
  209. break;
  210. case IRQ_TYPE_EDGE_FALLING:
  211. wg->intcnt = CTLI_INTCNT_NE;
  212. break;
  213. default:
  214. return -EINVAL;
  215. }
  216. wg->update |= UPDATE_IRQ_TYPE;
  217. return 0;
  218. }
  219. static void wcove_bus_lock(struct irq_data *data)
  220. {
  221. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  222. struct wcove_gpio *wg = gpiochip_get_data(chip);
  223. mutex_lock(&wg->buslock);
  224. }
  225. static void wcove_bus_sync_unlock(struct irq_data *data)
  226. {
  227. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  228. struct wcove_gpio *wg = gpiochip_get_data(chip);
  229. int gpio = data->hwirq;
  230. if (wg->update & UPDATE_IRQ_TYPE)
  231. wcove_update_irq_ctrl(wg, gpio);
  232. if (wg->update & UPDATE_IRQ_MASK)
  233. wcove_update_irq_mask(wg, gpio);
  234. wg->update = 0;
  235. mutex_unlock(&wg->buslock);
  236. }
  237. static void wcove_irq_unmask(struct irq_data *data)
  238. {
  239. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  240. struct wcove_gpio *wg = gpiochip_get_data(chip);
  241. if (data->hwirq >= WCOVE_GPIO_NUM)
  242. return;
  243. wg->set_irq_mask = false;
  244. wg->update |= UPDATE_IRQ_MASK;
  245. }
  246. static void wcove_irq_mask(struct irq_data *data)
  247. {
  248. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  249. struct wcove_gpio *wg = gpiochip_get_data(chip);
  250. if (data->hwirq >= WCOVE_GPIO_NUM)
  251. return;
  252. wg->set_irq_mask = true;
  253. wg->update |= UPDATE_IRQ_MASK;
  254. }
  255. static struct irq_chip wcove_irqchip = {
  256. .name = "Whiskey Cove",
  257. .irq_mask = wcove_irq_mask,
  258. .irq_unmask = wcove_irq_unmask,
  259. .irq_set_type = wcove_irq_type,
  260. .irq_bus_lock = wcove_bus_lock,
  261. .irq_bus_sync_unlock = wcove_bus_sync_unlock,
  262. };
  263. static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
  264. {
  265. struct wcove_gpio *wg = (struct wcove_gpio *)data;
  266. unsigned int pending, virq, gpio, mask, offset;
  267. u8 p[2];
  268. if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
  269. dev_err(wg->dev, "Failed to read irq status register\n");
  270. return IRQ_NONE;
  271. }
  272. pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
  273. if (!pending)
  274. return IRQ_NONE;
  275. /* Iterate until no interrupt is pending */
  276. while (pending) {
  277. /* One iteration is for all pending bits */
  278. for_each_set_bit(gpio, (const unsigned long *)&pending,
  279. WCOVE_GPIO_NUM) {
  280. offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
  281. mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
  282. BIT(gpio);
  283. virq = irq_find_mapping(wg->chip.irq.domain, gpio);
  284. handle_nested_irq(virq);
  285. regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
  286. mask, mask);
  287. }
  288. /* Next iteration */
  289. if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
  290. dev_err(wg->dev, "Failed to read irq status\n");
  291. break;
  292. }
  293. pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
  294. }
  295. return IRQ_HANDLED;
  296. }
  297. static void wcove_gpio_dbg_show(struct seq_file *s,
  298. struct gpio_chip *chip)
  299. {
  300. unsigned int ctlo, ctli, irq_mask, irq_status;
  301. struct wcove_gpio *wg = gpiochip_get_data(chip);
  302. int gpio, offset, group, ret = 0;
  303. for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
  304. group = gpio < GROUP0_NR_IRQS ? 0 : 1;
  305. ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
  306. ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
  307. ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
  308. &irq_mask);
  309. ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
  310. &irq_status);
  311. if (ret) {
  312. pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
  313. break;
  314. }
  315. offset = gpio % 8;
  316. seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
  317. gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
  318. ctli & 0x1 ? "hi" : "lo",
  319. ctli & CTLI_INTCNT_NE ? "fall" : " ",
  320. ctli & CTLI_INTCNT_PE ? "rise" : " ",
  321. ctlo,
  322. irq_mask & BIT(offset) ? "mask " : "unmask",
  323. irq_status & BIT(offset) ? "pending" : " ");
  324. }
  325. }
  326. static int wcove_gpio_probe(struct platform_device *pdev)
  327. {
  328. struct intel_soc_pmic *pmic;
  329. struct wcove_gpio *wg;
  330. int virq, ret, irq;
  331. struct device *dev;
  332. struct gpio_irq_chip *girq;
  333. /*
  334. * This gpio platform device is created by a mfd device (see
  335. * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
  336. * shared by all sub-devices created by the mfd device, the regmap
  337. * pointer for instance, is stored as driver data of the mfd device
  338. * driver.
  339. */
  340. pmic = dev_get_drvdata(pdev->dev.parent);
  341. if (!pmic)
  342. return -ENODEV;
  343. irq = platform_get_irq(pdev, 0);
  344. if (irq < 0)
  345. return irq;
  346. dev = &pdev->dev;
  347. wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
  348. if (!wg)
  349. return -ENOMEM;
  350. wg->regmap_irq_chip = pmic->irq_chip_data;
  351. platform_set_drvdata(pdev, wg);
  352. mutex_init(&wg->buslock);
  353. wg->chip.label = KBUILD_MODNAME;
  354. wg->chip.direction_input = wcove_gpio_dir_in;
  355. wg->chip.direction_output = wcove_gpio_dir_out;
  356. wg->chip.get_direction = wcove_gpio_get_direction;
  357. wg->chip.get = wcove_gpio_get;
  358. wg->chip.set = wcove_gpio_set;
  359. wg->chip.set_config = wcove_gpio_set_config,
  360. wg->chip.base = -1;
  361. wg->chip.ngpio = WCOVE_VGPIO_NUM;
  362. wg->chip.can_sleep = true;
  363. wg->chip.parent = pdev->dev.parent;
  364. wg->chip.dbg_show = wcove_gpio_dbg_show;
  365. wg->dev = dev;
  366. wg->regmap = pmic->regmap;
  367. virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
  368. if (virq < 0) {
  369. dev_err(dev, "Failed to get virq by irq %d\n", irq);
  370. return virq;
  371. }
  372. girq = &wg->chip.irq;
  373. girq->chip = &wcove_irqchip;
  374. /* This will let us handle the parent IRQ in the driver */
  375. girq->parent_handler = NULL;
  376. girq->num_parents = 0;
  377. girq->parents = NULL;
  378. girq->default_type = IRQ_TYPE_NONE;
  379. girq->handler = handle_simple_irq;
  380. girq->threaded = true;
  381. ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
  382. IRQF_ONESHOT, pdev->name, wg);
  383. if (ret) {
  384. dev_err(dev, "Failed to request irq %d\n", virq);
  385. return ret;
  386. }
  387. ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
  388. if (ret) {
  389. dev_err(dev, "Failed to add gpiochip: %d\n", ret);
  390. return ret;
  391. }
  392. /* Enable GPIO0 interrupts */
  393. ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
  394. 0x00);
  395. if (ret)
  396. return ret;
  397. /* Enable GPIO1 interrupts */
  398. ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
  399. 0x00);
  400. if (ret)
  401. return ret;
  402. return 0;
  403. }
  404. /*
  405. * Whiskey Cove PMIC itself is a analog device(but with digital control
  406. * interface) providing power management support for other devices in
  407. * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
  408. */
  409. static struct platform_driver wcove_gpio_driver = {
  410. .driver = {
  411. .name = "bxt_wcove_gpio",
  412. },
  413. .probe = wcove_gpio_probe,
  414. };
  415. module_platform_driver(wcove_gpio_driver);
  416. MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
  417. MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
  418. MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
  419. MODULE_LICENSE("GPL v2");
  420. MODULE_ALIAS("platform:bxt_wcove_gpio");