gpio-vr41xx.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for NEC VR4100 series General-purpose I/O Unit.
  4. *
  5. * Copyright (C) 2002 MontaVista Software Inc.
  6. * Author: Yoichi Yuasa <source@mvista.com>
  7. * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
  8. */
  9. #include <linux/errno.h>
  10. #include <linux/fs.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/irq.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/types.h>
  21. #include <asm/vr41xx/giu.h>
  22. #include <asm/vr41xx/irq.h>
  23. #include <asm/vr41xx/vr41xx.h>
  24. MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
  25. MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
  26. MODULE_LICENSE("GPL");
  27. #define GIUIOSELL 0x00
  28. #define GIUIOSELH 0x02
  29. #define GIUPIODL 0x04
  30. #define GIUPIODH 0x06
  31. #define GIUINTSTATL 0x08
  32. #define GIUINTSTATH 0x0a
  33. #define GIUINTENL 0x0c
  34. #define GIUINTENH 0x0e
  35. #define GIUINTTYPL 0x10
  36. #define GIUINTTYPH 0x12
  37. #define GIUINTALSELL 0x14
  38. #define GIUINTALSELH 0x16
  39. #define GIUINTHTSELL 0x18
  40. #define GIUINTHTSELH 0x1a
  41. #define GIUPODATL 0x1c
  42. #define GIUPODATEN 0x1c
  43. #define GIUPODATH 0x1e
  44. #define PIOEN0 0x0100
  45. #define PIOEN1 0x0200
  46. #define GIUPODAT 0x1e
  47. #define GIUFEDGEINHL 0x20
  48. #define GIUFEDGEINHH 0x22
  49. #define GIUREDGEINHL 0x24
  50. #define GIUREDGEINHH 0x26
  51. #define GIUUSEUPDN 0x1e0
  52. #define GIUTERMUPDN 0x1e2
  53. #define GPIO_HAS_PULLUPDOWN_IO 0x0001
  54. #define GPIO_HAS_OUTPUT_ENABLE 0x0002
  55. #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
  56. enum {
  57. GPIO_INPUT,
  58. GPIO_OUTPUT,
  59. };
  60. static DEFINE_SPINLOCK(giu_lock);
  61. static unsigned long giu_flags;
  62. static void __iomem *giu_base;
  63. static struct gpio_chip vr41xx_gpio_chip;
  64. #define giu_read(offset) readw(giu_base + (offset))
  65. #define giu_write(offset, value) writew((value), giu_base + (offset))
  66. #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
  67. #define GIUINT_HIGH_OFFSET 16
  68. #define GIUINT_HIGH_MAX 32
  69. static inline u16 giu_set(u16 offset, u16 set)
  70. {
  71. u16 data;
  72. data = giu_read(offset);
  73. data |= set;
  74. giu_write(offset, data);
  75. return data;
  76. }
  77. static inline u16 giu_clear(u16 offset, u16 clear)
  78. {
  79. u16 data;
  80. data = giu_read(offset);
  81. data &= ~clear;
  82. giu_write(offset, data);
  83. return data;
  84. }
  85. static void ack_giuint_low(struct irq_data *d)
  86. {
  87. giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
  88. }
  89. static void mask_giuint_low(struct irq_data *d)
  90. {
  91. giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
  92. }
  93. static void mask_ack_giuint_low(struct irq_data *d)
  94. {
  95. unsigned int pin;
  96. pin = GPIO_PIN_OF_IRQ(d->irq);
  97. giu_clear(GIUINTENL, 1 << pin);
  98. giu_write(GIUINTSTATL, 1 << pin);
  99. }
  100. static void unmask_giuint_low(struct irq_data *d)
  101. {
  102. giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
  103. }
  104. static unsigned int startup_giuint(struct irq_data *data)
  105. {
  106. int ret;
  107. ret = gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data));
  108. if (ret) {
  109. dev_err(vr41xx_gpio_chip.parent,
  110. "unable to lock HW IRQ %lu for IRQ\n",
  111. data->hwirq);
  112. return ret;
  113. }
  114. /* Satisfy the .enable semantics by unmasking the line */
  115. unmask_giuint_low(data);
  116. return 0;
  117. }
  118. static void shutdown_giuint(struct irq_data *data)
  119. {
  120. mask_giuint_low(data);
  121. gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
  122. }
  123. static struct irq_chip giuint_low_irq_chip = {
  124. .name = "GIUINTL",
  125. .irq_ack = ack_giuint_low,
  126. .irq_mask = mask_giuint_low,
  127. .irq_mask_ack = mask_ack_giuint_low,
  128. .irq_unmask = unmask_giuint_low,
  129. .irq_startup = startup_giuint,
  130. .irq_shutdown = shutdown_giuint,
  131. };
  132. static void ack_giuint_high(struct irq_data *d)
  133. {
  134. giu_write(GIUINTSTATH,
  135. 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
  136. }
  137. static void mask_giuint_high(struct irq_data *d)
  138. {
  139. giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
  140. }
  141. static void mask_ack_giuint_high(struct irq_data *d)
  142. {
  143. unsigned int pin;
  144. pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
  145. giu_clear(GIUINTENH, 1 << pin);
  146. giu_write(GIUINTSTATH, 1 << pin);
  147. }
  148. static void unmask_giuint_high(struct irq_data *d)
  149. {
  150. giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
  151. }
  152. static struct irq_chip giuint_high_irq_chip = {
  153. .name = "GIUINTH",
  154. .irq_ack = ack_giuint_high,
  155. .irq_mask = mask_giuint_high,
  156. .irq_mask_ack = mask_ack_giuint_high,
  157. .irq_unmask = unmask_giuint_high,
  158. };
  159. static int giu_get_irq(unsigned int irq)
  160. {
  161. u16 pendl, pendh, maskl, maskh;
  162. int i;
  163. pendl = giu_read(GIUINTSTATL);
  164. pendh = giu_read(GIUINTSTATH);
  165. maskl = giu_read(GIUINTENL);
  166. maskh = giu_read(GIUINTENH);
  167. maskl &= pendl;
  168. maskh &= pendh;
  169. if (maskl) {
  170. for (i = 0; i < 16; i++) {
  171. if (maskl & (1 << i))
  172. return GIU_IRQ(i);
  173. }
  174. } else if (maskh) {
  175. for (i = 0; i < 16; i++) {
  176. if (maskh & (1 << i))
  177. return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
  178. }
  179. }
  180. printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
  181. maskl, pendl, maskh, pendh);
  182. atomic_inc(&irq_err_count);
  183. return -EINVAL;
  184. }
  185. void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
  186. irq_signal_t signal)
  187. {
  188. u16 mask;
  189. if (pin < GIUINT_HIGH_OFFSET) {
  190. mask = 1 << pin;
  191. if (trigger != IRQ_TRIGGER_LEVEL) {
  192. giu_set(GIUINTTYPL, mask);
  193. if (signal == IRQ_SIGNAL_HOLD)
  194. giu_set(GIUINTHTSELL, mask);
  195. else
  196. giu_clear(GIUINTHTSELL, mask);
  197. if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
  198. switch (trigger) {
  199. case IRQ_TRIGGER_EDGE_FALLING:
  200. giu_set(GIUFEDGEINHL, mask);
  201. giu_clear(GIUREDGEINHL, mask);
  202. break;
  203. case IRQ_TRIGGER_EDGE_RISING:
  204. giu_clear(GIUFEDGEINHL, mask);
  205. giu_set(GIUREDGEINHL, mask);
  206. break;
  207. default:
  208. giu_set(GIUFEDGEINHL, mask);
  209. giu_set(GIUREDGEINHL, mask);
  210. break;
  211. }
  212. }
  213. irq_set_chip_and_handler(GIU_IRQ(pin),
  214. &giuint_low_irq_chip,
  215. handle_edge_irq);
  216. } else {
  217. giu_clear(GIUINTTYPL, mask);
  218. giu_clear(GIUINTHTSELL, mask);
  219. irq_set_chip_and_handler(GIU_IRQ(pin),
  220. &giuint_low_irq_chip,
  221. handle_level_irq);
  222. }
  223. giu_write(GIUINTSTATL, mask);
  224. } else if (pin < GIUINT_HIGH_MAX) {
  225. mask = 1 << (pin - GIUINT_HIGH_OFFSET);
  226. if (trigger != IRQ_TRIGGER_LEVEL) {
  227. giu_set(GIUINTTYPH, mask);
  228. if (signal == IRQ_SIGNAL_HOLD)
  229. giu_set(GIUINTHTSELH, mask);
  230. else
  231. giu_clear(GIUINTHTSELH, mask);
  232. if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
  233. switch (trigger) {
  234. case IRQ_TRIGGER_EDGE_FALLING:
  235. giu_set(GIUFEDGEINHH, mask);
  236. giu_clear(GIUREDGEINHH, mask);
  237. break;
  238. case IRQ_TRIGGER_EDGE_RISING:
  239. giu_clear(GIUFEDGEINHH, mask);
  240. giu_set(GIUREDGEINHH, mask);
  241. break;
  242. default:
  243. giu_set(GIUFEDGEINHH, mask);
  244. giu_set(GIUREDGEINHH, mask);
  245. break;
  246. }
  247. }
  248. irq_set_chip_and_handler(GIU_IRQ(pin),
  249. &giuint_high_irq_chip,
  250. handle_edge_irq);
  251. } else {
  252. giu_clear(GIUINTTYPH, mask);
  253. giu_clear(GIUINTHTSELH, mask);
  254. irq_set_chip_and_handler(GIU_IRQ(pin),
  255. &giuint_high_irq_chip,
  256. handle_level_irq);
  257. }
  258. giu_write(GIUINTSTATH, mask);
  259. }
  260. }
  261. EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
  262. void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
  263. {
  264. u16 mask;
  265. if (pin < GIUINT_HIGH_OFFSET) {
  266. mask = 1 << pin;
  267. if (level == IRQ_LEVEL_HIGH)
  268. giu_set(GIUINTALSELL, mask);
  269. else
  270. giu_clear(GIUINTALSELL, mask);
  271. giu_write(GIUINTSTATL, mask);
  272. } else if (pin < GIUINT_HIGH_MAX) {
  273. mask = 1 << (pin - GIUINT_HIGH_OFFSET);
  274. if (level == IRQ_LEVEL_HIGH)
  275. giu_set(GIUINTALSELH, mask);
  276. else
  277. giu_clear(GIUINTALSELH, mask);
  278. giu_write(GIUINTSTATH, mask);
  279. }
  280. }
  281. EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
  282. static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
  283. {
  284. u16 offset, mask, reg;
  285. unsigned long flags;
  286. if (pin >= chip->ngpio)
  287. return -EINVAL;
  288. if (pin < 16) {
  289. offset = GIUIOSELL;
  290. mask = 1 << pin;
  291. } else if (pin < 32) {
  292. offset = GIUIOSELH;
  293. mask = 1 << (pin - 16);
  294. } else {
  295. if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
  296. offset = GIUPODATEN;
  297. mask = 1 << (pin - 32);
  298. } else {
  299. switch (pin) {
  300. case 48:
  301. offset = GIUPODATH;
  302. mask = PIOEN0;
  303. break;
  304. case 49:
  305. offset = GIUPODATH;
  306. mask = PIOEN1;
  307. break;
  308. default:
  309. return -EINVAL;
  310. }
  311. }
  312. }
  313. spin_lock_irqsave(&giu_lock, flags);
  314. reg = giu_read(offset);
  315. if (dir == GPIO_OUTPUT)
  316. reg |= mask;
  317. else
  318. reg &= ~mask;
  319. giu_write(offset, reg);
  320. spin_unlock_irqrestore(&giu_lock, flags);
  321. return 0;
  322. }
  323. static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
  324. {
  325. u16 reg, mask;
  326. if (pin >= chip->ngpio)
  327. return -EINVAL;
  328. if (pin < 16) {
  329. reg = giu_read(GIUPIODL);
  330. mask = 1 << pin;
  331. } else if (pin < 32) {
  332. reg = giu_read(GIUPIODH);
  333. mask = 1 << (pin - 16);
  334. } else if (pin < 48) {
  335. reg = giu_read(GIUPODATL);
  336. mask = 1 << (pin - 32);
  337. } else {
  338. reg = giu_read(GIUPODATH);
  339. mask = 1 << (pin - 48);
  340. }
  341. if (reg & mask)
  342. return 1;
  343. return 0;
  344. }
  345. static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
  346. int value)
  347. {
  348. u16 offset, mask, reg;
  349. unsigned long flags;
  350. if (pin >= chip->ngpio)
  351. return;
  352. if (pin < 16) {
  353. offset = GIUPIODL;
  354. mask = 1 << pin;
  355. } else if (pin < 32) {
  356. offset = GIUPIODH;
  357. mask = 1 << (pin - 16);
  358. } else if (pin < 48) {
  359. offset = GIUPODATL;
  360. mask = 1 << (pin - 32);
  361. } else {
  362. offset = GIUPODATH;
  363. mask = 1 << (pin - 48);
  364. }
  365. spin_lock_irqsave(&giu_lock, flags);
  366. reg = giu_read(offset);
  367. if (value)
  368. reg |= mask;
  369. else
  370. reg &= ~mask;
  371. giu_write(offset, reg);
  372. spin_unlock_irqrestore(&giu_lock, flags);
  373. }
  374. static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  375. {
  376. return giu_set_direction(chip, offset, GPIO_INPUT);
  377. }
  378. static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  379. int value)
  380. {
  381. vr41xx_gpio_set(chip, offset, value);
  382. return giu_set_direction(chip, offset, GPIO_OUTPUT);
  383. }
  384. static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  385. {
  386. if (offset >= chip->ngpio)
  387. return -EINVAL;
  388. return GIU_IRQ_BASE + offset;
  389. }
  390. static struct gpio_chip vr41xx_gpio_chip = {
  391. .label = "vr41xx",
  392. .owner = THIS_MODULE,
  393. .direction_input = vr41xx_gpio_direction_input,
  394. .get = vr41xx_gpio_get,
  395. .direction_output = vr41xx_gpio_direction_output,
  396. .set = vr41xx_gpio_set,
  397. .to_irq = vr41xx_gpio_to_irq,
  398. };
  399. static int giu_probe(struct platform_device *pdev)
  400. {
  401. unsigned int trigger, i, pin;
  402. struct irq_chip *chip;
  403. int irq;
  404. switch (pdev->id) {
  405. case GPIO_50PINS_PULLUPDOWN:
  406. giu_flags = GPIO_HAS_PULLUPDOWN_IO;
  407. vr41xx_gpio_chip.ngpio = 50;
  408. break;
  409. case GPIO_36PINS:
  410. vr41xx_gpio_chip.ngpio = 36;
  411. break;
  412. case GPIO_48PINS_EDGE_SELECT:
  413. giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
  414. vr41xx_gpio_chip.ngpio = 48;
  415. break;
  416. default:
  417. dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
  418. return -ENODEV;
  419. }
  420. giu_base = devm_platform_ioremap_resource(pdev, 0);
  421. if (IS_ERR(giu_base))
  422. return PTR_ERR(giu_base);
  423. vr41xx_gpio_chip.parent = &pdev->dev;
  424. if (gpiochip_add_data(&vr41xx_gpio_chip, NULL))
  425. return -ENODEV;
  426. giu_write(GIUINTENL, 0);
  427. giu_write(GIUINTENH, 0);
  428. trigger = giu_read(GIUINTTYPH) << 16;
  429. trigger |= giu_read(GIUINTTYPL);
  430. for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
  431. pin = GPIO_PIN_OF_IRQ(i);
  432. if (pin < GIUINT_HIGH_OFFSET)
  433. chip = &giuint_low_irq_chip;
  434. else
  435. chip = &giuint_high_irq_chip;
  436. if (trigger & (1 << pin))
  437. irq_set_chip_and_handler(i, chip, handle_edge_irq);
  438. else
  439. irq_set_chip_and_handler(i, chip, handle_level_irq);
  440. }
  441. irq = platform_get_irq(pdev, 0);
  442. if (irq < 0 || irq >= nr_irqs)
  443. return -EBUSY;
  444. return cascade_irq(irq, giu_get_irq);
  445. }
  446. static int giu_remove(struct platform_device *pdev)
  447. {
  448. if (giu_base) {
  449. giu_base = NULL;
  450. }
  451. return 0;
  452. }
  453. static struct platform_driver giu_device_driver = {
  454. .probe = giu_probe,
  455. .remove = giu_remove,
  456. .driver = {
  457. .name = "GIU",
  458. },
  459. };
  460. module_platform_driver(giu_device_driver);