gpio-vf610.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale vf610 GPIO support through PORT and GPIO
  4. *
  5. * Copyright (c) 2014 Toradex AG.
  6. *
  7. * Author: Stefan Agner <stefan@agner.ch>.
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/ioport.h>
  17. #include <linux/irq.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/of_irq.h>
  22. #define VF610_GPIO_PER_PORT 32
  23. struct fsl_gpio_soc_data {
  24. /* SoCs has a Port Data Direction Register (PDDR) */
  25. bool have_paddr;
  26. };
  27. struct vf610_gpio_port {
  28. struct gpio_chip gc;
  29. struct irq_chip ic;
  30. void __iomem *base;
  31. void __iomem *gpio_base;
  32. const struct fsl_gpio_soc_data *sdata;
  33. u8 irqc[VF610_GPIO_PER_PORT];
  34. struct clk *clk_port;
  35. struct clk *clk_gpio;
  36. int irq;
  37. };
  38. #define GPIO_PDOR 0x00
  39. #define GPIO_PSOR 0x04
  40. #define GPIO_PCOR 0x08
  41. #define GPIO_PTOR 0x0c
  42. #define GPIO_PDIR 0x10
  43. #define GPIO_PDDR 0x14
  44. #define PORT_PCR(n) ((n) * 0x4)
  45. #define PORT_PCR_IRQC_OFFSET 16
  46. #define PORT_ISFR 0xa0
  47. #define PORT_DFER 0xc0
  48. #define PORT_DFCR 0xc4
  49. #define PORT_DFWR 0xc8
  50. #define PORT_INT_OFF 0x0
  51. #define PORT_INT_LOGIC_ZERO 0x8
  52. #define PORT_INT_RISING_EDGE 0x9
  53. #define PORT_INT_FALLING_EDGE 0xa
  54. #define PORT_INT_EITHER_EDGE 0xb
  55. #define PORT_INT_LOGIC_ONE 0xc
  56. static const struct fsl_gpio_soc_data imx_data = {
  57. .have_paddr = true,
  58. };
  59. static const struct of_device_id vf610_gpio_dt_ids[] = {
  60. { .compatible = "fsl,vf610-gpio", .data = NULL, },
  61. { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
  62. { /* sentinel */ }
  63. };
  64. static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
  65. {
  66. writel_relaxed(val, reg);
  67. }
  68. static inline u32 vf610_gpio_readl(void __iomem *reg)
  69. {
  70. return readl_relaxed(reg);
  71. }
  72. static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  73. {
  74. struct vf610_gpio_port *port = gpiochip_get_data(gc);
  75. unsigned long mask = BIT(gpio);
  76. unsigned long offset = GPIO_PDIR;
  77. if (port->sdata && port->sdata->have_paddr) {
  78. mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
  79. if (mask)
  80. offset = GPIO_PDOR;
  81. }
  82. return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
  83. }
  84. static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  85. {
  86. struct vf610_gpio_port *port = gpiochip_get_data(gc);
  87. unsigned long mask = BIT(gpio);
  88. unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
  89. vf610_gpio_writel(mask, port->gpio_base + offset);
  90. }
  91. static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  92. {
  93. struct vf610_gpio_port *port = gpiochip_get_data(chip);
  94. unsigned long mask = BIT(gpio);
  95. u32 val;
  96. if (port->sdata && port->sdata->have_paddr) {
  97. val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
  98. val &= ~mask;
  99. vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
  100. }
  101. return pinctrl_gpio_direction_input(chip->base + gpio);
  102. }
  103. static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
  104. int value)
  105. {
  106. struct vf610_gpio_port *port = gpiochip_get_data(chip);
  107. unsigned long mask = BIT(gpio);
  108. if (port->sdata && port->sdata->have_paddr)
  109. vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
  110. vf610_gpio_set(chip, gpio, value);
  111. return pinctrl_gpio_direction_output(chip->base + gpio);
  112. }
  113. static void vf610_gpio_irq_handler(struct irq_desc *desc)
  114. {
  115. struct vf610_gpio_port *port =
  116. gpiochip_get_data(irq_desc_get_handler_data(desc));
  117. struct irq_chip *chip = irq_desc_get_chip(desc);
  118. int pin;
  119. unsigned long irq_isfr;
  120. chained_irq_enter(chip, desc);
  121. irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
  122. for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
  123. vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
  124. generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
  125. }
  126. chained_irq_exit(chip, desc);
  127. }
  128. static void vf610_gpio_irq_ack(struct irq_data *d)
  129. {
  130. struct vf610_gpio_port *port =
  131. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  132. int gpio = d->hwirq;
  133. vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
  134. }
  135. static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
  136. {
  137. struct vf610_gpio_port *port =
  138. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  139. u8 irqc;
  140. switch (type) {
  141. case IRQ_TYPE_EDGE_RISING:
  142. irqc = PORT_INT_RISING_EDGE;
  143. break;
  144. case IRQ_TYPE_EDGE_FALLING:
  145. irqc = PORT_INT_FALLING_EDGE;
  146. break;
  147. case IRQ_TYPE_EDGE_BOTH:
  148. irqc = PORT_INT_EITHER_EDGE;
  149. break;
  150. case IRQ_TYPE_LEVEL_LOW:
  151. irqc = PORT_INT_LOGIC_ZERO;
  152. break;
  153. case IRQ_TYPE_LEVEL_HIGH:
  154. irqc = PORT_INT_LOGIC_ONE;
  155. break;
  156. default:
  157. return -EINVAL;
  158. }
  159. port->irqc[d->hwirq] = irqc;
  160. if (type & IRQ_TYPE_LEVEL_MASK)
  161. irq_set_handler_locked(d, handle_level_irq);
  162. else
  163. irq_set_handler_locked(d, handle_edge_irq);
  164. return 0;
  165. }
  166. static void vf610_gpio_irq_mask(struct irq_data *d)
  167. {
  168. struct vf610_gpio_port *port =
  169. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  170. void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
  171. vf610_gpio_writel(0, pcr_base);
  172. }
  173. static void vf610_gpio_irq_unmask(struct irq_data *d)
  174. {
  175. struct vf610_gpio_port *port =
  176. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  177. void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
  178. vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
  179. pcr_base);
  180. }
  181. static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
  182. {
  183. struct vf610_gpio_port *port =
  184. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  185. if (enable)
  186. enable_irq_wake(port->irq);
  187. else
  188. disable_irq_wake(port->irq);
  189. return 0;
  190. }
  191. static void vf610_gpio_disable_clk(void *data)
  192. {
  193. clk_disable_unprepare(data);
  194. }
  195. static int vf610_gpio_probe(struct platform_device *pdev)
  196. {
  197. struct device *dev = &pdev->dev;
  198. struct device_node *np = dev->of_node;
  199. struct vf610_gpio_port *port;
  200. struct gpio_chip *gc;
  201. struct gpio_irq_chip *girq;
  202. struct irq_chip *ic;
  203. int i;
  204. int ret;
  205. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  206. if (!port)
  207. return -ENOMEM;
  208. port->sdata = of_device_get_match_data(dev);
  209. port->base = devm_platform_ioremap_resource(pdev, 0);
  210. if (IS_ERR(port->base))
  211. return PTR_ERR(port->base);
  212. port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
  213. if (IS_ERR(port->gpio_base))
  214. return PTR_ERR(port->gpio_base);
  215. port->irq = platform_get_irq(pdev, 0);
  216. if (port->irq < 0)
  217. return port->irq;
  218. port->clk_port = devm_clk_get(dev, "port");
  219. ret = PTR_ERR_OR_ZERO(port->clk_port);
  220. if (!ret) {
  221. ret = clk_prepare_enable(port->clk_port);
  222. if (ret)
  223. return ret;
  224. ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
  225. port->clk_port);
  226. if (ret)
  227. return ret;
  228. } else if (ret == -EPROBE_DEFER) {
  229. /*
  230. * Percolate deferrals, for anything else,
  231. * just live without the clocking.
  232. */
  233. return ret;
  234. }
  235. port->clk_gpio = devm_clk_get(dev, "gpio");
  236. ret = PTR_ERR_OR_ZERO(port->clk_gpio);
  237. if (!ret) {
  238. ret = clk_prepare_enable(port->clk_gpio);
  239. if (ret)
  240. return ret;
  241. ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
  242. port->clk_gpio);
  243. if (ret)
  244. return ret;
  245. } else if (ret == -EPROBE_DEFER) {
  246. return ret;
  247. }
  248. gc = &port->gc;
  249. gc->of_node = np;
  250. gc->parent = dev;
  251. gc->label = "vf610-gpio";
  252. gc->ngpio = VF610_GPIO_PER_PORT;
  253. gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
  254. gc->request = gpiochip_generic_request;
  255. gc->free = gpiochip_generic_free;
  256. gc->direction_input = vf610_gpio_direction_input;
  257. gc->get = vf610_gpio_get;
  258. gc->direction_output = vf610_gpio_direction_output;
  259. gc->set = vf610_gpio_set;
  260. ic = &port->ic;
  261. ic->name = "gpio-vf610";
  262. ic->irq_ack = vf610_gpio_irq_ack;
  263. ic->irq_mask = vf610_gpio_irq_mask;
  264. ic->irq_unmask = vf610_gpio_irq_unmask;
  265. ic->irq_set_type = vf610_gpio_irq_set_type;
  266. ic->irq_set_wake = vf610_gpio_irq_set_wake;
  267. /* Mask all GPIO interrupts */
  268. for (i = 0; i < gc->ngpio; i++)
  269. vf610_gpio_writel(0, port->base + PORT_PCR(i));
  270. /* Clear the interrupt status register for all GPIO's */
  271. vf610_gpio_writel(~0, port->base + PORT_ISFR);
  272. girq = &gc->irq;
  273. girq->chip = ic;
  274. girq->parent_handler = vf610_gpio_irq_handler;
  275. girq->num_parents = 1;
  276. girq->parents = devm_kcalloc(&pdev->dev, 1,
  277. sizeof(*girq->parents),
  278. GFP_KERNEL);
  279. if (!girq->parents)
  280. return -ENOMEM;
  281. girq->parents[0] = port->irq;
  282. girq->default_type = IRQ_TYPE_NONE;
  283. girq->handler = handle_edge_irq;
  284. return devm_gpiochip_add_data(dev, gc, port);
  285. }
  286. static struct platform_driver vf610_gpio_driver = {
  287. .driver = {
  288. .name = "gpio-vf610",
  289. .of_match_table = vf610_gpio_dt_ids,
  290. },
  291. .probe = vf610_gpio_probe,
  292. };
  293. builtin_platform_driver(vf610_gpio_driver);