gpio-uniphier.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2017 Socionext Inc.
  4. // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. #include <linux/bits.h>
  6. #include <linux/gpio/driver.h>
  7. #include <linux/irq.h>
  8. #include <linux/irqdomain.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/spinlock.h>
  15. #include <dt-bindings/gpio/uniphier-gpio.h>
  16. #define UNIPHIER_GPIO_IRQ_MAX_NUM 24
  17. #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
  18. #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
  19. #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
  20. #define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */
  21. #define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */
  22. #define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */
  23. struct uniphier_gpio_priv {
  24. struct gpio_chip chip;
  25. struct irq_chip irq_chip;
  26. struct irq_domain *domain;
  27. void __iomem *regs;
  28. spinlock_t lock;
  29. u32 saved_vals[];
  30. };
  31. static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
  32. {
  33. unsigned int reg;
  34. reg = (bank + 1) * 8;
  35. /*
  36. * Unfortunately, the GPIO port registers are not contiguous because
  37. * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
  38. */
  39. if (reg >= UNIPHIER_GPIO_IRQ_EN)
  40. reg += 0x10;
  41. return reg;
  42. }
  43. static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
  44. unsigned int *bank, u32 *mask)
  45. {
  46. *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
  47. *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
  48. }
  49. static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
  50. unsigned int reg, u32 mask, u32 val)
  51. {
  52. unsigned long flags;
  53. u32 tmp;
  54. spin_lock_irqsave(&priv->lock, flags);
  55. tmp = readl(priv->regs + reg);
  56. tmp &= ~mask;
  57. tmp |= mask & val;
  58. writel(tmp, priv->regs + reg);
  59. spin_unlock_irqrestore(&priv->lock, flags);
  60. }
  61. static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
  62. unsigned int reg, u32 mask, u32 val)
  63. {
  64. struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
  65. if (!mask)
  66. return;
  67. uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
  68. mask, val);
  69. }
  70. static void uniphier_gpio_offset_write(struct gpio_chip *chip,
  71. unsigned int offset, unsigned int reg,
  72. int val)
  73. {
  74. unsigned int bank;
  75. u32 mask;
  76. uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
  77. uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
  78. }
  79. static int uniphier_gpio_offset_read(struct gpio_chip *chip,
  80. unsigned int offset, unsigned int reg)
  81. {
  82. struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
  83. unsigned int bank, reg_offset;
  84. u32 mask;
  85. uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
  86. reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
  87. return !!(readl(priv->regs + reg_offset) & mask);
  88. }
  89. static int uniphier_gpio_get_direction(struct gpio_chip *chip,
  90. unsigned int offset)
  91. {
  92. if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR))
  93. return GPIO_LINE_DIRECTION_IN;
  94. return GPIO_LINE_DIRECTION_OUT;
  95. }
  96. static int uniphier_gpio_direction_input(struct gpio_chip *chip,
  97. unsigned int offset)
  98. {
  99. uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
  100. return 0;
  101. }
  102. static int uniphier_gpio_direction_output(struct gpio_chip *chip,
  103. unsigned int offset, int val)
  104. {
  105. uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
  106. uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
  107. return 0;
  108. }
  109. static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
  110. {
  111. return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
  112. }
  113. static void uniphier_gpio_set(struct gpio_chip *chip,
  114. unsigned int offset, int val)
  115. {
  116. uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
  117. }
  118. static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
  119. unsigned long *mask, unsigned long *bits)
  120. {
  121. unsigned long i, bank, bank_mask, bank_bits;
  122. for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
  123. bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
  124. bank_bits = bitmap_get_value8(bits, i);
  125. uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
  126. bank_mask, bank_bits);
  127. }
  128. }
  129. static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  130. {
  131. struct irq_fwspec fwspec;
  132. if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
  133. return -ENXIO;
  134. fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
  135. fwspec.param_count = 2;
  136. fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
  137. /*
  138. * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
  139. * temporarily. Anyway, ->irq_set_type() will override it later.
  140. */
  141. fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
  142. return irq_create_fwspec_mapping(&fwspec);
  143. }
  144. static void uniphier_gpio_irq_mask(struct irq_data *data)
  145. {
  146. struct uniphier_gpio_priv *priv = data->chip_data;
  147. u32 mask = BIT(data->hwirq);
  148. uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
  149. irq_chip_mask_parent(data);
  150. }
  151. static void uniphier_gpio_irq_unmask(struct irq_data *data)
  152. {
  153. struct uniphier_gpio_priv *priv = data->chip_data;
  154. u32 mask = BIT(data->hwirq);
  155. uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
  156. irq_chip_unmask_parent(data);
  157. }
  158. static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
  159. {
  160. struct uniphier_gpio_priv *priv = data->chip_data;
  161. u32 mask = BIT(data->hwirq);
  162. u32 val = 0;
  163. if (type == IRQ_TYPE_EDGE_BOTH) {
  164. val = mask;
  165. type = IRQ_TYPE_EDGE_FALLING;
  166. }
  167. uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
  168. /* To enable both edge detection, the noise filter must be enabled. */
  169. uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
  170. return irq_chip_set_type_parent(data, type);
  171. }
  172. static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
  173. unsigned int hwirq)
  174. {
  175. struct device_node *np = priv->chip.parent->of_node;
  176. const __be32 *range;
  177. u32 base, parent_base, size;
  178. int len;
  179. range = of_get_property(np, "socionext,interrupt-ranges", &len);
  180. if (!range)
  181. return -EINVAL;
  182. len /= sizeof(*range);
  183. for (; len >= 3; len -= 3) {
  184. base = be32_to_cpu(*range++);
  185. parent_base = be32_to_cpu(*range++);
  186. size = be32_to_cpu(*range++);
  187. if (base <= hwirq && hwirq < base + size)
  188. return hwirq - base + parent_base;
  189. }
  190. return -ENOENT;
  191. }
  192. static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
  193. struct irq_fwspec *fwspec,
  194. unsigned long *out_hwirq,
  195. unsigned int *out_type)
  196. {
  197. if (WARN_ON(fwspec->param_count < 2))
  198. return -EINVAL;
  199. *out_hwirq = fwspec->param[0];
  200. *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  201. return 0;
  202. }
  203. static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
  204. unsigned int virq,
  205. unsigned int nr_irqs, void *arg)
  206. {
  207. struct uniphier_gpio_priv *priv = domain->host_data;
  208. struct irq_fwspec parent_fwspec;
  209. irq_hw_number_t hwirq;
  210. unsigned int type;
  211. int ret;
  212. if (WARN_ON(nr_irqs != 1))
  213. return -EINVAL;
  214. ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
  215. if (ret)
  216. return ret;
  217. ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
  218. if (ret < 0)
  219. return ret;
  220. /* parent is UniPhier AIDET */
  221. parent_fwspec.fwnode = domain->parent->fwnode;
  222. parent_fwspec.param_count = 2;
  223. parent_fwspec.param[0] = ret;
  224. parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
  225. IRQ_TYPE_EDGE_FALLING : type;
  226. ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  227. &priv->irq_chip, priv);
  228. if (ret)
  229. return ret;
  230. return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
  231. }
  232. static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
  233. struct irq_data *data, bool early)
  234. {
  235. struct uniphier_gpio_priv *priv = domain->host_data;
  236. struct gpio_chip *chip = &priv->chip;
  237. return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
  238. }
  239. static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
  240. struct irq_data *data)
  241. {
  242. struct uniphier_gpio_priv *priv = domain->host_data;
  243. struct gpio_chip *chip = &priv->chip;
  244. gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
  245. }
  246. static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
  247. .alloc = uniphier_gpio_irq_domain_alloc,
  248. .free = irq_domain_free_irqs_common,
  249. .activate = uniphier_gpio_irq_domain_activate,
  250. .deactivate = uniphier_gpio_irq_domain_deactivate,
  251. .translate = uniphier_gpio_irq_domain_translate,
  252. };
  253. static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
  254. {
  255. /*
  256. * Due to the hardware design, the noise filter must be enabled to
  257. * detect both edge interrupts. This filter is intended to remove the
  258. * noise from the irq lines. It does not work for GPIO input, so GPIO
  259. * debounce is not supported. Unfortunately, the filter period is
  260. * shared among all irq lines. Just choose a sensible period here.
  261. */
  262. writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
  263. }
  264. static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
  265. {
  266. return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
  267. }
  268. static int uniphier_gpio_probe(struct platform_device *pdev)
  269. {
  270. struct device *dev = &pdev->dev;
  271. struct device_node *parent_np;
  272. struct irq_domain *parent_domain;
  273. struct uniphier_gpio_priv *priv;
  274. struct gpio_chip *chip;
  275. struct irq_chip *irq_chip;
  276. unsigned int nregs;
  277. u32 ngpios;
  278. int ret;
  279. parent_np = of_irq_find_parent(dev->of_node);
  280. if (!parent_np)
  281. return -ENXIO;
  282. parent_domain = irq_find_host(parent_np);
  283. of_node_put(parent_np);
  284. if (!parent_domain)
  285. return -EPROBE_DEFER;
  286. ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
  287. if (ret)
  288. return ret;
  289. nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
  290. priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
  291. GFP_KERNEL);
  292. if (!priv)
  293. return -ENOMEM;
  294. priv->regs = devm_platform_ioremap_resource(pdev, 0);
  295. if (IS_ERR(priv->regs))
  296. return PTR_ERR(priv->regs);
  297. spin_lock_init(&priv->lock);
  298. chip = &priv->chip;
  299. chip->label = dev_name(dev);
  300. chip->parent = dev;
  301. chip->request = gpiochip_generic_request;
  302. chip->free = gpiochip_generic_free;
  303. chip->get_direction = uniphier_gpio_get_direction;
  304. chip->direction_input = uniphier_gpio_direction_input;
  305. chip->direction_output = uniphier_gpio_direction_output;
  306. chip->get = uniphier_gpio_get;
  307. chip->set = uniphier_gpio_set;
  308. chip->set_multiple = uniphier_gpio_set_multiple;
  309. chip->to_irq = uniphier_gpio_to_irq;
  310. chip->base = -1;
  311. chip->ngpio = ngpios;
  312. irq_chip = &priv->irq_chip;
  313. irq_chip->name = dev_name(dev);
  314. irq_chip->irq_mask = uniphier_gpio_irq_mask;
  315. irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
  316. irq_chip->irq_eoi = irq_chip_eoi_parent;
  317. irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
  318. irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
  319. uniphier_gpio_hw_init(priv);
  320. ret = devm_gpiochip_add_data(dev, chip, priv);
  321. if (ret)
  322. return ret;
  323. priv->domain = irq_domain_create_hierarchy(
  324. parent_domain, 0,
  325. UNIPHIER_GPIO_IRQ_MAX_NUM,
  326. of_node_to_fwnode(dev->of_node),
  327. &uniphier_gpio_irq_domain_ops, priv);
  328. if (!priv->domain)
  329. return -ENOMEM;
  330. platform_set_drvdata(pdev, priv);
  331. return 0;
  332. }
  333. static int uniphier_gpio_remove(struct platform_device *pdev)
  334. {
  335. struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
  336. irq_domain_remove(priv->domain);
  337. return 0;
  338. }
  339. static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
  340. {
  341. struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
  342. unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
  343. u32 *val = priv->saved_vals;
  344. unsigned int reg;
  345. int i;
  346. for (i = 0; i < nbanks; i++) {
  347. reg = uniphier_gpio_bank_to_reg(i);
  348. *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
  349. *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
  350. }
  351. *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
  352. *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
  353. *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
  354. return 0;
  355. }
  356. static int __maybe_unused uniphier_gpio_resume(struct device *dev)
  357. {
  358. struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
  359. unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
  360. const u32 *val = priv->saved_vals;
  361. unsigned int reg;
  362. int i;
  363. for (i = 0; i < nbanks; i++) {
  364. reg = uniphier_gpio_bank_to_reg(i);
  365. writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
  366. writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
  367. }
  368. writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
  369. writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
  370. writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
  371. uniphier_gpio_hw_init(priv);
  372. return 0;
  373. }
  374. static const struct dev_pm_ops uniphier_gpio_pm_ops = {
  375. SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
  376. uniphier_gpio_resume)
  377. };
  378. static const struct of_device_id uniphier_gpio_match[] = {
  379. { .compatible = "socionext,uniphier-gpio" },
  380. { /* sentinel */ }
  381. };
  382. MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
  383. static struct platform_driver uniphier_gpio_driver = {
  384. .probe = uniphier_gpio_probe,
  385. .remove = uniphier_gpio_remove,
  386. .driver = {
  387. .name = "uniphier-gpio",
  388. .of_match_table = uniphier_gpio_match,
  389. .pm = &uniphier_gpio_pm_ops,
  390. },
  391. };
  392. module_platform_driver(uniphier_gpio_driver);
  393. MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
  394. MODULE_DESCRIPTION("UniPhier GPIO driver");
  395. MODULE_LICENSE("GPL v2");