gpio-tqmx86.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TQ-Systems TQMx86 PLD GPIO driver
  4. *
  5. * Based on vendor driver by:
  6. * Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/errno.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/slab.h>
  18. #define TQMX86_NGPIO 8
  19. #define TQMX86_NGPO 4 /* 0-3 - output */
  20. #define TQMX86_NGPI 4 /* 4-7 - input */
  21. #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
  22. #define TQMX86_GPIODD 0 /* GPIO Data Direction Register */
  23. #define TQMX86_GPIOD 1 /* GPIO Data Register */
  24. #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */
  25. #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */
  26. #define TQMX86_GPII_FALLING BIT(0)
  27. #define TQMX86_GPII_RISING BIT(1)
  28. #define TQMX86_GPII_MASK (BIT(0) | BIT(1))
  29. #define TQMX86_GPII_BITS 2
  30. struct tqmx86_gpio_data {
  31. struct gpio_chip chip;
  32. struct irq_chip irq_chip;
  33. void __iomem *io_base;
  34. int irq;
  35. raw_spinlock_t spinlock;
  36. u8 irq_type[TQMX86_NGPI];
  37. };
  38. static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg)
  39. {
  40. return ioread8(gd->io_base + reg);
  41. }
  42. static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
  43. unsigned int reg)
  44. {
  45. iowrite8(val, gd->io_base + reg);
  46. }
  47. static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset)
  48. {
  49. struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
  50. return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset));
  51. }
  52. static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
  53. int value)
  54. {
  55. struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
  56. unsigned long flags;
  57. u8 val;
  58. raw_spin_lock_irqsave(&gpio->spinlock, flags);
  59. val = tqmx86_gpio_read(gpio, TQMX86_GPIOD);
  60. if (value)
  61. val |= BIT(offset);
  62. else
  63. val &= ~BIT(offset);
  64. tqmx86_gpio_write(gpio, val, TQMX86_GPIOD);
  65. raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
  66. }
  67. static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
  68. unsigned int offset)
  69. {
  70. /* Direction cannot be changed. Validate is an input. */
  71. if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
  72. return 0;
  73. else
  74. return -EINVAL;
  75. }
  76. static int tqmx86_gpio_direction_output(struct gpio_chip *chip,
  77. unsigned int offset,
  78. int value)
  79. {
  80. /* Direction cannot be changed, validate is an output */
  81. if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
  82. return -EINVAL;
  83. tqmx86_gpio_set(chip, offset, value);
  84. return 0;
  85. }
  86. static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
  87. unsigned int offset)
  88. {
  89. if (TQMX86_DIR_INPUT_MASK & BIT(offset))
  90. return GPIO_LINE_DIRECTION_IN;
  91. return GPIO_LINE_DIRECTION_OUT;
  92. }
  93. static void tqmx86_gpio_irq_mask(struct irq_data *data)
  94. {
  95. unsigned int offset = (data->hwirq - TQMX86_NGPO);
  96. struct tqmx86_gpio_data *gpio = gpiochip_get_data(
  97. irq_data_get_irq_chip_data(data));
  98. unsigned long flags;
  99. u8 gpiic, mask;
  100. mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
  101. raw_spin_lock_irqsave(&gpio->spinlock, flags);
  102. gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
  103. gpiic &= ~mask;
  104. tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
  105. raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
  106. }
  107. static void tqmx86_gpio_irq_unmask(struct irq_data *data)
  108. {
  109. unsigned int offset = (data->hwirq - TQMX86_NGPO);
  110. struct tqmx86_gpio_data *gpio = gpiochip_get_data(
  111. irq_data_get_irq_chip_data(data));
  112. unsigned long flags;
  113. u8 gpiic, mask;
  114. mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
  115. raw_spin_lock_irqsave(&gpio->spinlock, flags);
  116. gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
  117. gpiic &= ~mask;
  118. gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS);
  119. tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
  120. raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
  121. }
  122. static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
  123. {
  124. struct tqmx86_gpio_data *gpio = gpiochip_get_data(
  125. irq_data_get_irq_chip_data(data));
  126. unsigned int offset = (data->hwirq - TQMX86_NGPO);
  127. unsigned int edge_type = type & IRQF_TRIGGER_MASK;
  128. unsigned long flags;
  129. u8 new_type, gpiic;
  130. switch (edge_type) {
  131. case IRQ_TYPE_EDGE_RISING:
  132. new_type = TQMX86_GPII_RISING;
  133. break;
  134. case IRQ_TYPE_EDGE_FALLING:
  135. new_type = TQMX86_GPII_FALLING;
  136. break;
  137. case IRQ_TYPE_EDGE_BOTH:
  138. new_type = TQMX86_GPII_FALLING | TQMX86_GPII_RISING;
  139. break;
  140. default:
  141. return -EINVAL; /* not supported */
  142. }
  143. gpio->irq_type[offset] = new_type;
  144. raw_spin_lock_irqsave(&gpio->spinlock, flags);
  145. gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
  146. gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS));
  147. gpiic |= new_type << (offset * TQMX86_GPII_BITS);
  148. tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
  149. raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
  150. return 0;
  151. }
  152. static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
  153. {
  154. struct gpio_chip *chip = irq_desc_get_handler_data(desc);
  155. struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
  156. struct irq_chip *irq_chip = irq_desc_get_chip(desc);
  157. unsigned long irq_bits;
  158. int i = 0, child_irq;
  159. u8 irq_status;
  160. chained_irq_enter(irq_chip, desc);
  161. irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
  162. tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
  163. irq_bits = irq_status;
  164. for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
  165. child_irq = irq_find_mapping(gpio->chip.irq.domain,
  166. i + TQMX86_NGPO);
  167. generic_handle_irq(child_irq);
  168. }
  169. chained_irq_exit(irq_chip, desc);
  170. }
  171. /* Minimal runtime PM is needed by the IRQ subsystem */
  172. static int __maybe_unused tqmx86_gpio_runtime_suspend(struct device *dev)
  173. {
  174. return 0;
  175. }
  176. static int __maybe_unused tqmx86_gpio_runtime_resume(struct device *dev)
  177. {
  178. return 0;
  179. }
  180. static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = {
  181. SET_RUNTIME_PM_OPS(tqmx86_gpio_runtime_suspend,
  182. tqmx86_gpio_runtime_resume, NULL)
  183. };
  184. static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip,
  185. unsigned long *valid_mask,
  186. unsigned int ngpios)
  187. {
  188. /* Only GPIOs 4-7 are valid for interrupts. Clear the others */
  189. clear_bit(0, valid_mask);
  190. clear_bit(1, valid_mask);
  191. clear_bit(2, valid_mask);
  192. clear_bit(3, valid_mask);
  193. }
  194. static int tqmx86_gpio_probe(struct platform_device *pdev)
  195. {
  196. struct device *dev = &pdev->dev;
  197. struct tqmx86_gpio_data *gpio;
  198. struct gpio_chip *chip;
  199. struct gpio_irq_chip *girq;
  200. void __iomem *io_base;
  201. struct resource *res;
  202. int ret, irq;
  203. irq = platform_get_irq_optional(pdev, 0);
  204. if (irq < 0 && irq != -ENXIO)
  205. return irq;
  206. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  207. if (!res) {
  208. dev_err(&pdev->dev, "Cannot get I/O\n");
  209. return -ENODEV;
  210. }
  211. io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
  212. if (!io_base)
  213. return -ENOMEM;
  214. gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
  215. if (!gpio)
  216. return -ENOMEM;
  217. raw_spin_lock_init(&gpio->spinlock);
  218. gpio->io_base = io_base;
  219. tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD);
  220. platform_set_drvdata(pdev, gpio);
  221. chip = &gpio->chip;
  222. chip->label = "gpio-tqmx86";
  223. chip->owner = THIS_MODULE;
  224. chip->can_sleep = false;
  225. chip->base = -1;
  226. chip->direction_input = tqmx86_gpio_direction_input;
  227. chip->direction_output = tqmx86_gpio_direction_output;
  228. chip->get_direction = tqmx86_gpio_get_direction;
  229. chip->get = tqmx86_gpio_get;
  230. chip->set = tqmx86_gpio_set;
  231. chip->ngpio = TQMX86_NGPIO;
  232. chip->parent = pdev->dev.parent;
  233. pm_runtime_enable(&pdev->dev);
  234. if (irq > 0) {
  235. struct irq_chip *irq_chip = &gpio->irq_chip;
  236. u8 irq_status;
  237. irq_chip->name = chip->label;
  238. irq_chip->parent_device = &pdev->dev;
  239. irq_chip->irq_mask = tqmx86_gpio_irq_mask;
  240. irq_chip->irq_unmask = tqmx86_gpio_irq_unmask;
  241. irq_chip->irq_set_type = tqmx86_gpio_irq_set_type;
  242. /* Mask all interrupts */
  243. tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC);
  244. /* Clear all pending interrupts */
  245. irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
  246. tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
  247. girq = &chip->irq;
  248. girq->chip = irq_chip;
  249. girq->parent_handler = tqmx86_gpio_irq_handler;
  250. girq->num_parents = 1;
  251. girq->parents = devm_kcalloc(&pdev->dev, 1,
  252. sizeof(*girq->parents),
  253. GFP_KERNEL);
  254. if (!girq->parents) {
  255. ret = -ENOMEM;
  256. goto out_pm_dis;
  257. }
  258. girq->parents[0] = irq;
  259. girq->default_type = IRQ_TYPE_NONE;
  260. girq->handler = handle_simple_irq;
  261. girq->init_valid_mask = tqmx86_init_irq_valid_mask;
  262. }
  263. ret = devm_gpiochip_add_data(dev, chip, gpio);
  264. if (ret) {
  265. dev_err(dev, "Could not register GPIO chip\n");
  266. goto out_pm_dis;
  267. }
  268. dev_info(dev, "GPIO functionality initialized with %d pins\n",
  269. chip->ngpio);
  270. return 0;
  271. out_pm_dis:
  272. pm_runtime_disable(&pdev->dev);
  273. return ret;
  274. }
  275. static struct platform_driver tqmx86_gpio_driver = {
  276. .driver = {
  277. .name = "tqmx86-gpio",
  278. .pm = &tqmx86_gpio_dev_pm_ops,
  279. },
  280. .probe = tqmx86_gpio_probe,
  281. };
  282. module_platform_driver(tqmx86_gpio_driver);
  283. MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver");
  284. MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
  285. MODULE_LICENSE("GPL");
  286. MODULE_ALIAS("platform:tqmx86-gpio");