gpio-timberdale.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Timberdale FPGA GPIO driver
  4. * Author: Mocean Laboratories
  5. * Copyright (c) 2009 Intel Corporation
  6. */
  7. /* Supports:
  8. * Timberdale FPGA GPIO
  9. */
  10. #include <linux/init.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/irq.h>
  14. #include <linux/io.h>
  15. #include <linux/timb_gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/slab.h>
  18. #define DRIVER_NAME "timb-gpio"
  19. #define TGPIOVAL 0x00
  20. #define TGPIODIR 0x04
  21. #define TGPIO_IER 0x08
  22. #define TGPIO_ISR 0x0c
  23. #define TGPIO_IPR 0x10
  24. #define TGPIO_ICR 0x14
  25. #define TGPIO_FLR 0x18
  26. #define TGPIO_LVR 0x1c
  27. #define TGPIO_VER 0x20
  28. #define TGPIO_BFLR 0x24
  29. struct timbgpio {
  30. void __iomem *membase;
  31. spinlock_t lock; /* mutual exclusion */
  32. struct gpio_chip gpio;
  33. int irq_base;
  34. unsigned long last_ier;
  35. };
  36. static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
  37. unsigned offset, bool enabled)
  38. {
  39. struct timbgpio *tgpio = gpiochip_get_data(gpio);
  40. u32 reg;
  41. spin_lock(&tgpio->lock);
  42. reg = ioread32(tgpio->membase + offset);
  43. if (enabled)
  44. reg |= (1 << index);
  45. else
  46. reg &= ~(1 << index);
  47. iowrite32(reg, tgpio->membase + offset);
  48. spin_unlock(&tgpio->lock);
  49. return 0;
  50. }
  51. static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  52. {
  53. return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
  54. }
  55. static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
  56. {
  57. struct timbgpio *tgpio = gpiochip_get_data(gpio);
  58. u32 value;
  59. value = ioread32(tgpio->membase + TGPIOVAL);
  60. return (value & (1 << nr)) ? 1 : 0;
  61. }
  62. static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
  63. unsigned nr, int val)
  64. {
  65. return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
  66. }
  67. static void timbgpio_gpio_set(struct gpio_chip *gpio,
  68. unsigned nr, int val)
  69. {
  70. timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
  71. }
  72. static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  73. {
  74. struct timbgpio *tgpio = gpiochip_get_data(gpio);
  75. if (tgpio->irq_base <= 0)
  76. return -EINVAL;
  77. return tgpio->irq_base + offset;
  78. }
  79. /*
  80. * GPIO IRQ
  81. */
  82. static void timbgpio_irq_disable(struct irq_data *d)
  83. {
  84. struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
  85. int offset = d->irq - tgpio->irq_base;
  86. unsigned long flags;
  87. spin_lock_irqsave(&tgpio->lock, flags);
  88. tgpio->last_ier &= ~(1UL << offset);
  89. iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
  90. spin_unlock_irqrestore(&tgpio->lock, flags);
  91. }
  92. static void timbgpio_irq_enable(struct irq_data *d)
  93. {
  94. struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
  95. int offset = d->irq - tgpio->irq_base;
  96. unsigned long flags;
  97. spin_lock_irqsave(&tgpio->lock, flags);
  98. tgpio->last_ier |= 1UL << offset;
  99. iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
  100. spin_unlock_irqrestore(&tgpio->lock, flags);
  101. }
  102. static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
  103. {
  104. struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
  105. int offset = d->irq - tgpio->irq_base;
  106. unsigned long flags;
  107. u32 lvr, flr, bflr = 0;
  108. u32 ver;
  109. int ret = 0;
  110. if (offset < 0 || offset > tgpio->gpio.ngpio)
  111. return -EINVAL;
  112. ver = ioread32(tgpio->membase + TGPIO_VER);
  113. spin_lock_irqsave(&tgpio->lock, flags);
  114. lvr = ioread32(tgpio->membase + TGPIO_LVR);
  115. flr = ioread32(tgpio->membase + TGPIO_FLR);
  116. if (ver > 2)
  117. bflr = ioread32(tgpio->membase + TGPIO_BFLR);
  118. if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  119. bflr &= ~(1 << offset);
  120. flr &= ~(1 << offset);
  121. if (trigger & IRQ_TYPE_LEVEL_HIGH)
  122. lvr |= 1 << offset;
  123. else
  124. lvr &= ~(1 << offset);
  125. }
  126. if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  127. if (ver < 3) {
  128. ret = -EINVAL;
  129. goto out;
  130. } else {
  131. flr |= 1 << offset;
  132. bflr |= 1 << offset;
  133. }
  134. } else {
  135. bflr &= ~(1 << offset);
  136. flr |= 1 << offset;
  137. if (trigger & IRQ_TYPE_EDGE_FALLING)
  138. lvr &= ~(1 << offset);
  139. else
  140. lvr |= 1 << offset;
  141. }
  142. iowrite32(lvr, tgpio->membase + TGPIO_LVR);
  143. iowrite32(flr, tgpio->membase + TGPIO_FLR);
  144. if (ver > 2)
  145. iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
  146. iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
  147. out:
  148. spin_unlock_irqrestore(&tgpio->lock, flags);
  149. return ret;
  150. }
  151. static void timbgpio_irq(struct irq_desc *desc)
  152. {
  153. struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
  154. struct irq_data *data = irq_desc_get_irq_data(desc);
  155. unsigned long ipr;
  156. int offset;
  157. data->chip->irq_ack(data);
  158. ipr = ioread32(tgpio->membase + TGPIO_IPR);
  159. iowrite32(ipr, tgpio->membase + TGPIO_ICR);
  160. /*
  161. * Some versions of the hardware trash the IER register if more than
  162. * one interrupt is received simultaneously.
  163. */
  164. iowrite32(0, tgpio->membase + TGPIO_IER);
  165. for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
  166. generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
  167. iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
  168. }
  169. static struct irq_chip timbgpio_irqchip = {
  170. .name = "GPIO",
  171. .irq_enable = timbgpio_irq_enable,
  172. .irq_disable = timbgpio_irq_disable,
  173. .irq_set_type = timbgpio_irq_type,
  174. };
  175. static int timbgpio_probe(struct platform_device *pdev)
  176. {
  177. int err, i;
  178. struct device *dev = &pdev->dev;
  179. struct gpio_chip *gc;
  180. struct timbgpio *tgpio;
  181. struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
  182. int irq = platform_get_irq(pdev, 0);
  183. if (!pdata || pdata->nr_pins > 32) {
  184. dev_err(dev, "Invalid platform data\n");
  185. return -EINVAL;
  186. }
  187. tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
  188. if (!tgpio)
  189. return -EINVAL;
  190. tgpio->irq_base = pdata->irq_base;
  191. spin_lock_init(&tgpio->lock);
  192. tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
  193. if (IS_ERR(tgpio->membase))
  194. return PTR_ERR(tgpio->membase);
  195. gc = &tgpio->gpio;
  196. gc->label = dev_name(&pdev->dev);
  197. gc->owner = THIS_MODULE;
  198. gc->parent = &pdev->dev;
  199. gc->direction_input = timbgpio_gpio_direction_input;
  200. gc->get = timbgpio_gpio_get;
  201. gc->direction_output = timbgpio_gpio_direction_output;
  202. gc->set = timbgpio_gpio_set;
  203. gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
  204. gc->dbg_show = NULL;
  205. gc->base = pdata->gpio_base;
  206. gc->ngpio = pdata->nr_pins;
  207. gc->can_sleep = false;
  208. err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
  209. if (err)
  210. return err;
  211. platform_set_drvdata(pdev, tgpio);
  212. /* make sure to disable interrupts */
  213. iowrite32(0x0, tgpio->membase + TGPIO_IER);
  214. if (irq < 0 || tgpio->irq_base <= 0)
  215. return 0;
  216. for (i = 0; i < pdata->nr_pins; i++) {
  217. irq_set_chip_and_handler(tgpio->irq_base + i,
  218. &timbgpio_irqchip, handle_simple_irq);
  219. irq_set_chip_data(tgpio->irq_base + i, tgpio);
  220. irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
  221. }
  222. irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
  223. return 0;
  224. }
  225. static struct platform_driver timbgpio_platform_driver = {
  226. .driver = {
  227. .name = DRIVER_NAME,
  228. .suppress_bind_attrs = true,
  229. },
  230. .probe = timbgpio_probe,
  231. };
  232. /*--------------------------------------------------------------------------*/
  233. builtin_platform_driver(timbgpio_platform_driver);