gpio-thunderx.c 16 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2016, 2017 Cavium Inc.
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/pci.h>
  16. #include <linux/spinlock.h>
  17. #include <asm-generic/msi.h>
  18. #define GPIO_RX_DAT 0x0
  19. #define GPIO_TX_SET 0x8
  20. #define GPIO_TX_CLR 0x10
  21. #define GPIO_CONST 0x90
  22. #define GPIO_CONST_GPIOS_MASK 0xff
  23. #define GPIO_BIT_CFG 0x400
  24. #define GPIO_BIT_CFG_TX_OE BIT(0)
  25. #define GPIO_BIT_CFG_PIN_XOR BIT(1)
  26. #define GPIO_BIT_CFG_INT_EN BIT(2)
  27. #define GPIO_BIT_CFG_INT_TYPE BIT(3)
  28. #define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)
  29. #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4
  30. #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8
  31. #define GPIO_BIT_CFG_TX_OD BIT(12)
  32. #define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)
  33. #define GPIO_INTR 0x800
  34. #define GPIO_INTR_INTR BIT(0)
  35. #define GPIO_INTR_INTR_W1S BIT(1)
  36. #define GPIO_INTR_ENA_W1C BIT(2)
  37. #define GPIO_INTR_ENA_W1S BIT(3)
  38. #define GPIO_2ND_BANK 0x1400
  39. #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
  40. (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
  41. struct thunderx_gpio;
  42. struct thunderx_line {
  43. struct thunderx_gpio *txgpio;
  44. unsigned int line;
  45. unsigned int fil_bits;
  46. };
  47. struct thunderx_gpio {
  48. struct gpio_chip chip;
  49. u8 __iomem *register_base;
  50. struct msix_entry *msix_entries; /* per line MSI-X */
  51. struct thunderx_line *line_entries; /* per line irq info */
  52. raw_spinlock_t lock;
  53. unsigned long invert_mask[2];
  54. unsigned long od_mask[2];
  55. int base_msi;
  56. };
  57. static unsigned int bit_cfg_reg(unsigned int line)
  58. {
  59. return 8 * line + GPIO_BIT_CFG;
  60. }
  61. static unsigned int intr_reg(unsigned int line)
  62. {
  63. return 8 * line + GPIO_INTR;
  64. }
  65. static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
  66. unsigned int line)
  67. {
  68. u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
  69. return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
  70. }
  71. /*
  72. * Check (and WARN) that the pin is available for GPIO. We will not
  73. * allow modification of the state of non-GPIO pins from this driver.
  74. */
  75. static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
  76. unsigned int line)
  77. {
  78. bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
  79. WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
  80. return rv;
  81. }
  82. static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
  83. {
  84. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  85. return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
  86. }
  87. static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
  88. {
  89. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  90. if (!thunderx_gpio_is_gpio(txgpio, line))
  91. return -EIO;
  92. raw_spin_lock(&txgpio->lock);
  93. clear_bit(line, txgpio->invert_mask);
  94. clear_bit(line, txgpio->od_mask);
  95. writeq(txgpio->line_entries[line].fil_bits,
  96. txgpio->register_base + bit_cfg_reg(line));
  97. raw_spin_unlock(&txgpio->lock);
  98. return 0;
  99. }
  100. static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
  101. int value)
  102. {
  103. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  104. int bank = line / 64;
  105. int bank_bit = line % 64;
  106. void __iomem *reg = txgpio->register_base +
  107. (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
  108. writeq(BIT_ULL(bank_bit), reg);
  109. }
  110. static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
  111. int value)
  112. {
  113. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  114. u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
  115. if (!thunderx_gpio_is_gpio(txgpio, line))
  116. return -EIO;
  117. raw_spin_lock(&txgpio->lock);
  118. thunderx_gpio_set(chip, line, value);
  119. if (test_bit(line, txgpio->invert_mask))
  120. bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
  121. if (test_bit(line, txgpio->od_mask))
  122. bit_cfg |= GPIO_BIT_CFG_TX_OD;
  123. writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
  124. raw_spin_unlock(&txgpio->lock);
  125. return 0;
  126. }
  127. static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
  128. {
  129. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  130. u64 bit_cfg;
  131. if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
  132. /*
  133. * Say it is input for now to avoid WARNing on
  134. * gpiochip_add_data(). We will WARN if someone
  135. * requests it or tries to use it.
  136. */
  137. return 1;
  138. bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
  139. if (bit_cfg & GPIO_BIT_CFG_TX_OE)
  140. return GPIO_LINE_DIRECTION_OUT;
  141. return GPIO_LINE_DIRECTION_IN;
  142. }
  143. static int thunderx_gpio_set_config(struct gpio_chip *chip,
  144. unsigned int line,
  145. unsigned long cfg)
  146. {
  147. bool orig_invert, orig_od, orig_dat, new_invert, new_od;
  148. u32 arg, sel;
  149. u64 bit_cfg;
  150. int bank = line / 64;
  151. int bank_bit = line % 64;
  152. int ret = -ENOTSUPP;
  153. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  154. void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
  155. if (!thunderx_gpio_is_gpio(txgpio, line))
  156. return -EIO;
  157. raw_spin_lock(&txgpio->lock);
  158. orig_invert = test_bit(line, txgpio->invert_mask);
  159. new_invert = orig_invert;
  160. orig_od = test_bit(line, txgpio->od_mask);
  161. new_od = orig_od;
  162. orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
  163. bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
  164. switch (pinconf_to_config_param(cfg)) {
  165. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  166. /*
  167. * Weird, setting open-drain mode causes signal
  168. * inversion. Note this so we can compensate in the
  169. * dir_out function.
  170. */
  171. set_bit(line, txgpio->invert_mask);
  172. new_invert = true;
  173. set_bit(line, txgpio->od_mask);
  174. new_od = true;
  175. ret = 0;
  176. break;
  177. case PIN_CONFIG_DRIVE_PUSH_PULL:
  178. clear_bit(line, txgpio->invert_mask);
  179. new_invert = false;
  180. clear_bit(line, txgpio->od_mask);
  181. new_od = false;
  182. ret = 0;
  183. break;
  184. case PIN_CONFIG_INPUT_DEBOUNCE:
  185. arg = pinconf_to_config_argument(cfg);
  186. if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
  187. ret = -EINVAL;
  188. break;
  189. }
  190. arg *= 400; /* scale to 2.5nS clocks. */
  191. sel = 0;
  192. while (arg > 15) {
  193. sel++;
  194. arg++; /* always round up */
  195. arg >>= 1;
  196. }
  197. txgpio->line_entries[line].fil_bits =
  198. (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
  199. (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
  200. bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
  201. bit_cfg |= txgpio->line_entries[line].fil_bits;
  202. writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
  203. ret = 0;
  204. break;
  205. default:
  206. break;
  207. }
  208. raw_spin_unlock(&txgpio->lock);
  209. /*
  210. * If currently output and OPEN_DRAIN changed, install the new
  211. * settings
  212. */
  213. if ((new_invert != orig_invert || new_od != orig_od) &&
  214. (bit_cfg & GPIO_BIT_CFG_TX_OE))
  215. ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
  216. return ret;
  217. }
  218. static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
  219. {
  220. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  221. int bank = line / 64;
  222. int bank_bit = line % 64;
  223. u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
  224. u64 masked_bits = read_bits & BIT_ULL(bank_bit);
  225. if (test_bit(line, txgpio->invert_mask))
  226. return masked_bits == 0;
  227. else
  228. return masked_bits != 0;
  229. }
  230. static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
  231. unsigned long *mask,
  232. unsigned long *bits)
  233. {
  234. int bank;
  235. u64 set_bits, clear_bits;
  236. struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
  237. for (bank = 0; bank <= chip->ngpio / 64; bank++) {
  238. set_bits = bits[bank] & mask[bank];
  239. clear_bits = ~bits[bank] & mask[bank];
  240. writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
  241. writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
  242. }
  243. }
  244. static void thunderx_gpio_irq_ack(struct irq_data *d)
  245. {
  246. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  247. struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
  248. writeq(GPIO_INTR_INTR,
  249. txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
  250. }
  251. static void thunderx_gpio_irq_mask(struct irq_data *d)
  252. {
  253. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  254. struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
  255. writeq(GPIO_INTR_ENA_W1C,
  256. txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
  257. }
  258. static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
  259. {
  260. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  261. struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
  262. writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
  263. txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
  264. }
  265. static void thunderx_gpio_irq_unmask(struct irq_data *d)
  266. {
  267. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  268. struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
  269. writeq(GPIO_INTR_ENA_W1S,
  270. txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
  271. }
  272. static int thunderx_gpio_irq_set_type(struct irq_data *d,
  273. unsigned int flow_type)
  274. {
  275. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  276. struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
  277. struct thunderx_line *txline =
  278. &txgpio->line_entries[irqd_to_hwirq(d)];
  279. u64 bit_cfg;
  280. irqd_set_trigger_type(d, flow_type);
  281. bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
  282. if (flow_type & IRQ_TYPE_EDGE_BOTH) {
  283. irq_set_handler_locked(d, handle_fasteoi_ack_irq);
  284. bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
  285. } else {
  286. irq_set_handler_locked(d, handle_fasteoi_mask_irq);
  287. }
  288. raw_spin_lock(&txgpio->lock);
  289. if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
  290. bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
  291. set_bit(txline->line, txgpio->invert_mask);
  292. } else {
  293. clear_bit(txline->line, txgpio->invert_mask);
  294. }
  295. clear_bit(txline->line, txgpio->od_mask);
  296. writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
  297. raw_spin_unlock(&txgpio->lock);
  298. return IRQ_SET_MASK_OK;
  299. }
  300. static void thunderx_gpio_irq_enable(struct irq_data *data)
  301. {
  302. irq_chip_enable_parent(data);
  303. thunderx_gpio_irq_unmask(data);
  304. }
  305. static void thunderx_gpio_irq_disable(struct irq_data *data)
  306. {
  307. thunderx_gpio_irq_mask(data);
  308. irq_chip_disable_parent(data);
  309. }
  310. /*
  311. * Interrupts are chained from underlying MSI-X vectors. We have
  312. * these irq_chip functions to be able to handle level triggering
  313. * semantics and other acknowledgment tasks associated with the GPIO
  314. * mechanism.
  315. */
  316. static struct irq_chip thunderx_gpio_irq_chip = {
  317. .name = "GPIO",
  318. .irq_enable = thunderx_gpio_irq_enable,
  319. .irq_disable = thunderx_gpio_irq_disable,
  320. .irq_ack = thunderx_gpio_irq_ack,
  321. .irq_mask = thunderx_gpio_irq_mask,
  322. .irq_mask_ack = thunderx_gpio_irq_mask_ack,
  323. .irq_unmask = thunderx_gpio_irq_unmask,
  324. .irq_eoi = irq_chip_eoi_parent,
  325. .irq_set_affinity = irq_chip_set_affinity_parent,
  326. .irq_set_type = thunderx_gpio_irq_set_type,
  327. .flags = IRQCHIP_SET_TYPE_MASKED
  328. };
  329. static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
  330. unsigned int child,
  331. unsigned int child_type,
  332. unsigned int *parent,
  333. unsigned int *parent_type)
  334. {
  335. struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
  336. struct irq_data *irqd;
  337. unsigned int irq;
  338. irq = txgpio->msix_entries[child].vector;
  339. irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq);
  340. if (!irqd)
  341. return -EINVAL;
  342. *parent = irqd_to_hwirq(irqd);
  343. *parent_type = IRQ_TYPE_LEVEL_HIGH;
  344. return 0;
  345. }
  346. static void *thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip,
  347. unsigned int parent_hwirq,
  348. unsigned int parent_type)
  349. {
  350. msi_alloc_info_t *info;
  351. info = kmalloc(sizeof(*info), GFP_KERNEL);
  352. if (!info)
  353. return NULL;
  354. info->hwirq = parent_hwirq;
  355. return info;
  356. }
  357. static int thunderx_gpio_probe(struct pci_dev *pdev,
  358. const struct pci_device_id *id)
  359. {
  360. void __iomem * const *tbl;
  361. struct device *dev = &pdev->dev;
  362. struct thunderx_gpio *txgpio;
  363. struct gpio_chip *chip;
  364. struct gpio_irq_chip *girq;
  365. int ngpio, i;
  366. int err = 0;
  367. txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
  368. if (!txgpio)
  369. return -ENOMEM;
  370. raw_spin_lock_init(&txgpio->lock);
  371. chip = &txgpio->chip;
  372. pci_set_drvdata(pdev, txgpio);
  373. err = pcim_enable_device(pdev);
  374. if (err) {
  375. dev_err(dev, "Failed to enable PCI device: err %d\n", err);
  376. goto out;
  377. }
  378. err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
  379. if (err) {
  380. dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
  381. goto out;
  382. }
  383. tbl = pcim_iomap_table(pdev);
  384. txgpio->register_base = tbl[0];
  385. if (!txgpio->register_base) {
  386. dev_err(dev, "Cannot map PCI resource\n");
  387. err = -ENOMEM;
  388. goto out;
  389. }
  390. if (pdev->subsystem_device == 0xa10a) {
  391. /* CN88XX has no GPIO_CONST register*/
  392. ngpio = 50;
  393. txgpio->base_msi = 48;
  394. } else {
  395. u64 c = readq(txgpio->register_base + GPIO_CONST);
  396. ngpio = c & GPIO_CONST_GPIOS_MASK;
  397. txgpio->base_msi = (c >> 8) & 0xff;
  398. }
  399. txgpio->msix_entries = devm_kcalloc(dev,
  400. ngpio, sizeof(struct msix_entry),
  401. GFP_KERNEL);
  402. if (!txgpio->msix_entries) {
  403. err = -ENOMEM;
  404. goto out;
  405. }
  406. txgpio->line_entries = devm_kcalloc(dev,
  407. ngpio,
  408. sizeof(struct thunderx_line),
  409. GFP_KERNEL);
  410. if (!txgpio->line_entries) {
  411. err = -ENOMEM;
  412. goto out;
  413. }
  414. for (i = 0; i < ngpio; i++) {
  415. u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
  416. txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
  417. txgpio->line_entries[i].line = i;
  418. txgpio->line_entries[i].txgpio = txgpio;
  419. /*
  420. * If something has already programmed the pin, use
  421. * the existing glitch filter settings, otherwise go
  422. * to 400nS.
  423. */
  424. txgpio->line_entries[i].fil_bits = bit_cfg ?
  425. (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
  426. if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
  427. set_bit(i, txgpio->od_mask);
  428. if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
  429. set_bit(i, txgpio->invert_mask);
  430. }
  431. /* Enable all MSI-X for interrupts on all possible lines. */
  432. err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
  433. if (err < 0)
  434. goto out;
  435. chip->label = KBUILD_MODNAME;
  436. chip->parent = dev;
  437. chip->owner = THIS_MODULE;
  438. chip->request = thunderx_gpio_request;
  439. chip->base = -1; /* System allocated */
  440. chip->can_sleep = false;
  441. chip->ngpio = ngpio;
  442. chip->get_direction = thunderx_gpio_get_direction;
  443. chip->direction_input = thunderx_gpio_dir_in;
  444. chip->get = thunderx_gpio_get;
  445. chip->direction_output = thunderx_gpio_dir_out;
  446. chip->set = thunderx_gpio_set;
  447. chip->set_multiple = thunderx_gpio_set_multiple;
  448. chip->set_config = thunderx_gpio_set_config;
  449. girq = &chip->irq;
  450. girq->chip = &thunderx_gpio_irq_chip;
  451. girq->fwnode = of_node_to_fwnode(dev->of_node);
  452. girq->parent_domain =
  453. irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
  454. girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
  455. girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info;
  456. girq->handler = handle_bad_irq;
  457. girq->default_type = IRQ_TYPE_NONE;
  458. err = devm_gpiochip_add_data(dev, chip, txgpio);
  459. if (err)
  460. goto out;
  461. /* Push on irq_data and the domain for each line. */
  462. for (i = 0; i < ngpio; i++) {
  463. struct irq_fwspec fwspec;
  464. fwspec.fwnode = of_node_to_fwnode(dev->of_node);
  465. fwspec.param_count = 2;
  466. fwspec.param[0] = i;
  467. fwspec.param[1] = IRQ_TYPE_NONE;
  468. err = irq_domain_push_irq(girq->domain,
  469. txgpio->msix_entries[i].vector,
  470. &fwspec);
  471. if (err < 0)
  472. dev_err(dev, "irq_domain_push_irq: %d\n", err);
  473. }
  474. dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
  475. ngpio, chip->base);
  476. return 0;
  477. out:
  478. pci_set_drvdata(pdev, NULL);
  479. return err;
  480. }
  481. static void thunderx_gpio_remove(struct pci_dev *pdev)
  482. {
  483. int i;
  484. struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
  485. for (i = 0; i < txgpio->chip.ngpio; i++)
  486. irq_domain_pop_irq(txgpio->chip.irq.domain,
  487. txgpio->msix_entries[i].vector);
  488. irq_domain_remove(txgpio->chip.irq.domain);
  489. pci_set_drvdata(pdev, NULL);
  490. }
  491. static const struct pci_device_id thunderx_gpio_id_table[] = {
  492. { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
  493. { 0, } /* end of table */
  494. };
  495. MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
  496. static struct pci_driver thunderx_gpio_driver = {
  497. .name = KBUILD_MODNAME,
  498. .id_table = thunderx_gpio_id_table,
  499. .probe = thunderx_gpio_probe,
  500. .remove = thunderx_gpio_remove,
  501. };
  502. module_pci_driver(thunderx_gpio_driver);
  503. MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
  504. MODULE_LICENSE("GPL");