gpio-tegra186.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2017 NVIDIA Corporation
  4. *
  5. * Author: Thierry Reding <treding@nvidia.com>
  6. */
  7. #include <linux/gpio/driver.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/irq.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <dt-bindings/gpio/tegra186-gpio.h>
  14. #include <dt-bindings/gpio/tegra194-gpio.h>
  15. /* security registers */
  16. #define TEGRA186_GPIO_CTL_SCR 0x0c
  17. #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
  18. #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
  19. #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
  20. /* control registers */
  21. #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
  22. #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
  23. #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
  24. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
  25. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
  26. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
  27. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
  28. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
  29. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
  30. #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
  31. #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
  32. #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
  33. #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
  34. #define TEGRA186_GPIO_INPUT 0x08
  35. #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
  36. #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
  37. #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
  38. #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
  39. #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
  40. #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
  41. #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
  42. struct tegra_gpio_port {
  43. const char *name;
  44. unsigned int bank;
  45. unsigned int port;
  46. unsigned int pins;
  47. };
  48. struct tegra186_pin_range {
  49. unsigned int offset;
  50. const char *group;
  51. };
  52. struct tegra_gpio_soc {
  53. const struct tegra_gpio_port *ports;
  54. unsigned int num_ports;
  55. const char *name;
  56. unsigned int instance;
  57. const struct tegra186_pin_range *pin_ranges;
  58. unsigned int num_pin_ranges;
  59. const char *pinmux;
  60. };
  61. struct tegra_gpio {
  62. struct gpio_chip gpio;
  63. struct irq_chip intc;
  64. unsigned int num_irq;
  65. unsigned int *irq;
  66. const struct tegra_gpio_soc *soc;
  67. void __iomem *secure;
  68. void __iomem *base;
  69. };
  70. static const struct tegra_gpio_port *
  71. tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
  72. {
  73. unsigned int start = 0, i;
  74. for (i = 0; i < gpio->soc->num_ports; i++) {
  75. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  76. if (*pin >= start && *pin < start + port->pins) {
  77. *pin -= start;
  78. return port;
  79. }
  80. start += port->pins;
  81. }
  82. return NULL;
  83. }
  84. static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
  85. unsigned int pin)
  86. {
  87. const struct tegra_gpio_port *port;
  88. unsigned int offset;
  89. port = tegra186_gpio_get_port(gpio, &pin);
  90. if (!port)
  91. return NULL;
  92. offset = port->bank * 0x1000 + port->port * 0x200;
  93. return gpio->base + offset + pin * 0x20;
  94. }
  95. static int tegra186_gpio_get_direction(struct gpio_chip *chip,
  96. unsigned int offset)
  97. {
  98. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  99. void __iomem *base;
  100. u32 value;
  101. base = tegra186_gpio_get_base(gpio, offset);
  102. if (WARN_ON(base == NULL))
  103. return -ENODEV;
  104. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  105. if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
  106. return GPIO_LINE_DIRECTION_OUT;
  107. return GPIO_LINE_DIRECTION_IN;
  108. }
  109. static int tegra186_gpio_direction_input(struct gpio_chip *chip,
  110. unsigned int offset)
  111. {
  112. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  113. void __iomem *base;
  114. u32 value;
  115. base = tegra186_gpio_get_base(gpio, offset);
  116. if (WARN_ON(base == NULL))
  117. return -ENODEV;
  118. value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
  119. value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
  120. writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
  121. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  122. value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
  123. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
  124. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  125. return 0;
  126. }
  127. static int tegra186_gpio_direction_output(struct gpio_chip *chip,
  128. unsigned int offset, int level)
  129. {
  130. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  131. void __iomem *base;
  132. u32 value;
  133. /* configure output level first */
  134. chip->set(chip, offset, level);
  135. base = tegra186_gpio_get_base(gpio, offset);
  136. if (WARN_ON(base == NULL))
  137. return -EINVAL;
  138. /* set the direction */
  139. value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
  140. value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
  141. writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
  142. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  143. value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
  144. value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
  145. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  146. return 0;
  147. }
  148. static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
  149. {
  150. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  151. void __iomem *base;
  152. u32 value;
  153. base = tegra186_gpio_get_base(gpio, offset);
  154. if (WARN_ON(base == NULL))
  155. return -ENODEV;
  156. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  157. if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
  158. value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
  159. else
  160. value = readl(base + TEGRA186_GPIO_INPUT);
  161. return value & BIT(0);
  162. }
  163. static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
  164. int level)
  165. {
  166. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  167. void __iomem *base;
  168. u32 value;
  169. base = tegra186_gpio_get_base(gpio, offset);
  170. if (WARN_ON(base == NULL))
  171. return;
  172. value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
  173. if (level == 0)
  174. value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
  175. else
  176. value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
  177. writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
  178. }
  179. static int tegra186_gpio_set_config(struct gpio_chip *chip,
  180. unsigned int offset,
  181. unsigned long config)
  182. {
  183. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  184. u32 debounce, value;
  185. void __iomem *base;
  186. base = tegra186_gpio_get_base(gpio, offset);
  187. if (base == NULL)
  188. return -ENXIO;
  189. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  190. return -ENOTSUPP;
  191. debounce = pinconf_to_config_argument(config);
  192. /*
  193. * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
  194. * time.
  195. */
  196. if (debounce > 255000)
  197. return -EINVAL;
  198. debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
  199. value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
  200. writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
  201. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  202. value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
  203. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  204. return 0;
  205. }
  206. static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
  207. {
  208. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  209. struct pinctrl_dev *pctldev;
  210. struct device_node *np;
  211. unsigned int i, j;
  212. int err;
  213. if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
  214. return 0;
  215. np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
  216. if (!np)
  217. return -ENODEV;
  218. pctldev = of_pinctrl_get(np);
  219. of_node_put(np);
  220. if (!pctldev)
  221. return -EPROBE_DEFER;
  222. for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
  223. unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
  224. const char *group = gpio->soc->pin_ranges[i].group;
  225. port = pin / 8;
  226. pin = pin % 8;
  227. if (port >= gpio->soc->num_ports) {
  228. dev_warn(chip->parent, "invalid port %u for %s\n",
  229. port, group);
  230. continue;
  231. }
  232. for (j = 0; j < port; j++)
  233. pin += gpio->soc->ports[j].pins;
  234. err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
  235. if (err < 0)
  236. return err;
  237. }
  238. return 0;
  239. }
  240. static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
  241. const struct of_phandle_args *spec,
  242. u32 *flags)
  243. {
  244. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  245. unsigned int port, pin, i, offset = 0;
  246. if (WARN_ON(chip->of_gpio_n_cells < 2))
  247. return -EINVAL;
  248. if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
  249. return -EINVAL;
  250. port = spec->args[0] / 8;
  251. pin = spec->args[0] % 8;
  252. if (port >= gpio->soc->num_ports) {
  253. dev_err(chip->parent, "invalid port number: %u\n", port);
  254. return -EINVAL;
  255. }
  256. for (i = 0; i < port; i++)
  257. offset += gpio->soc->ports[i].pins;
  258. if (flags)
  259. *flags = spec->args[1];
  260. return offset + pin;
  261. }
  262. #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
  263. static void tegra186_irq_ack(struct irq_data *data)
  264. {
  265. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  266. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  267. void __iomem *base;
  268. base = tegra186_gpio_get_base(gpio, data->hwirq);
  269. if (WARN_ON(base == NULL))
  270. return;
  271. writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
  272. }
  273. static void tegra186_irq_mask(struct irq_data *data)
  274. {
  275. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  276. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  277. void __iomem *base;
  278. u32 value;
  279. base = tegra186_gpio_get_base(gpio, data->hwirq);
  280. if (WARN_ON(base == NULL))
  281. return;
  282. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  283. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
  284. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  285. }
  286. static void tegra186_irq_unmask(struct irq_data *data)
  287. {
  288. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  289. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  290. void __iomem *base;
  291. u32 value;
  292. base = tegra186_gpio_get_base(gpio, data->hwirq);
  293. if (WARN_ON(base == NULL))
  294. return;
  295. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  296. value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
  297. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  298. }
  299. static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
  300. {
  301. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  302. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  303. void __iomem *base;
  304. u32 value;
  305. base = tegra186_gpio_get_base(gpio, data->hwirq);
  306. if (WARN_ON(base == NULL))
  307. return -ENODEV;
  308. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  309. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
  310. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  311. switch (type & IRQ_TYPE_SENSE_MASK) {
  312. case IRQ_TYPE_NONE:
  313. break;
  314. case IRQ_TYPE_EDGE_RISING:
  315. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  316. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  317. break;
  318. case IRQ_TYPE_EDGE_FALLING:
  319. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  320. break;
  321. case IRQ_TYPE_EDGE_BOTH:
  322. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
  323. break;
  324. case IRQ_TYPE_LEVEL_HIGH:
  325. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
  326. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  327. break;
  328. case IRQ_TYPE_LEVEL_LOW:
  329. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
  330. break;
  331. default:
  332. return -EINVAL;
  333. }
  334. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  335. if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
  336. irq_set_handler_locked(data, handle_level_irq);
  337. else
  338. irq_set_handler_locked(data, handle_edge_irq);
  339. if (data->parent_data)
  340. return irq_chip_set_type_parent(data, type);
  341. return 0;
  342. }
  343. static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
  344. {
  345. if (data->parent_data)
  346. return irq_chip_set_wake_parent(data, on);
  347. return 0;
  348. }
  349. static void tegra186_gpio_irq(struct irq_desc *desc)
  350. {
  351. struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
  352. struct irq_domain *domain = gpio->gpio.irq.domain;
  353. struct irq_chip *chip = irq_desc_get_chip(desc);
  354. unsigned int parent = irq_desc_get_irq(desc);
  355. unsigned int i, offset = 0;
  356. chained_irq_enter(chip, desc);
  357. for (i = 0; i < gpio->soc->num_ports; i++) {
  358. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  359. unsigned int pin, irq;
  360. unsigned long value;
  361. void __iomem *base;
  362. base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
  363. /* skip ports that are not associated with this bank */
  364. if (parent != gpio->irq[port->bank])
  365. goto skip;
  366. value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
  367. for_each_set_bit(pin, &value, port->pins) {
  368. irq = irq_find_mapping(domain, offset + pin);
  369. if (WARN_ON(irq == 0))
  370. continue;
  371. generic_handle_irq(irq);
  372. }
  373. skip:
  374. offset += port->pins;
  375. }
  376. chained_irq_exit(chip, desc);
  377. }
  378. static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
  379. struct irq_fwspec *fwspec,
  380. unsigned long *hwirq,
  381. unsigned int *type)
  382. {
  383. struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
  384. unsigned int port, pin, i, offset = 0;
  385. if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
  386. return -EINVAL;
  387. if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
  388. return -EINVAL;
  389. port = fwspec->param[0] / 8;
  390. pin = fwspec->param[0] % 8;
  391. if (port >= gpio->soc->num_ports)
  392. return -EINVAL;
  393. for (i = 0; i < port; i++)
  394. offset += gpio->soc->ports[i].pins;
  395. *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  396. *hwirq = offset + pin;
  397. return 0;
  398. }
  399. static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
  400. unsigned int parent_hwirq,
  401. unsigned int parent_type)
  402. {
  403. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  404. struct irq_fwspec *fwspec;
  405. fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
  406. if (!fwspec)
  407. return NULL;
  408. fwspec->fwnode = chip->irq.parent_domain->fwnode;
  409. fwspec->param_count = 3;
  410. fwspec->param[0] = gpio->soc->instance;
  411. fwspec->param[1] = parent_hwirq;
  412. fwspec->param[2] = parent_type;
  413. return fwspec;
  414. }
  415. static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
  416. unsigned int hwirq,
  417. unsigned int type,
  418. unsigned int *parent_hwirq,
  419. unsigned int *parent_type)
  420. {
  421. *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
  422. *parent_type = type;
  423. return 0;
  424. }
  425. static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
  426. unsigned int offset)
  427. {
  428. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  429. unsigned int i;
  430. for (i = 0; i < gpio->soc->num_ports; i++) {
  431. if (offset < gpio->soc->ports[i].pins)
  432. break;
  433. offset -= gpio->soc->ports[i].pins;
  434. }
  435. return offset + i * 8;
  436. }
  437. static const struct of_device_id tegra186_pmc_of_match[] = {
  438. { .compatible = "nvidia,tegra186-pmc" },
  439. { .compatible = "nvidia,tegra194-pmc" },
  440. { /* sentinel */ }
  441. };
  442. static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
  443. {
  444. unsigned int i, j;
  445. u32 value;
  446. for (i = 0; i < gpio->soc->num_ports; i++) {
  447. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  448. unsigned int offset, p = port->port;
  449. void __iomem *base;
  450. base = gpio->secure + port->bank * 0x1000 + 0x800;
  451. value = readl(base + TEGRA186_GPIO_CTL_SCR);
  452. /*
  453. * For controllers that haven't been locked down yet, make
  454. * sure to program the default interrupt route mapping.
  455. */
  456. if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
  457. (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
  458. for (j = 0; j < 8; j++) {
  459. offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
  460. value = readl(base + offset);
  461. value = BIT(port->pins) - 1;
  462. writel(value, base + offset);
  463. }
  464. }
  465. }
  466. }
  467. static int tegra186_gpio_probe(struct platform_device *pdev)
  468. {
  469. unsigned int i, j, offset;
  470. struct gpio_irq_chip *irq;
  471. struct tegra_gpio *gpio;
  472. struct device_node *np;
  473. char **names;
  474. int err;
  475. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  476. if (!gpio)
  477. return -ENOMEM;
  478. gpio->soc = of_device_get_match_data(&pdev->dev);
  479. gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
  480. if (IS_ERR(gpio->secure))
  481. return PTR_ERR(gpio->secure);
  482. gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
  483. if (IS_ERR(gpio->base))
  484. return PTR_ERR(gpio->base);
  485. err = platform_irq_count(pdev);
  486. if (err < 0)
  487. return err;
  488. gpio->num_irq = err;
  489. gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
  490. GFP_KERNEL);
  491. if (!gpio->irq)
  492. return -ENOMEM;
  493. for (i = 0; i < gpio->num_irq; i++) {
  494. err = platform_get_irq(pdev, i);
  495. if (err < 0)
  496. return err;
  497. gpio->irq[i] = err;
  498. }
  499. gpio->gpio.label = gpio->soc->name;
  500. gpio->gpio.parent = &pdev->dev;
  501. gpio->gpio.request = gpiochip_generic_request;
  502. gpio->gpio.free = gpiochip_generic_free;
  503. gpio->gpio.get_direction = tegra186_gpio_get_direction;
  504. gpio->gpio.direction_input = tegra186_gpio_direction_input;
  505. gpio->gpio.direction_output = tegra186_gpio_direction_output;
  506. gpio->gpio.get = tegra186_gpio_get,
  507. gpio->gpio.set = tegra186_gpio_set;
  508. gpio->gpio.set_config = tegra186_gpio_set_config;
  509. gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
  510. gpio->gpio.base = -1;
  511. for (i = 0; i < gpio->soc->num_ports; i++)
  512. gpio->gpio.ngpio += gpio->soc->ports[i].pins;
  513. names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
  514. sizeof(*names), GFP_KERNEL);
  515. if (!names)
  516. return -ENOMEM;
  517. for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
  518. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  519. char *name;
  520. for (j = 0; j < port->pins; j++) {
  521. name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
  522. "P%s.%02x", port->name, j);
  523. if (!name)
  524. return -ENOMEM;
  525. names[offset + j] = name;
  526. }
  527. offset += port->pins;
  528. }
  529. gpio->gpio.names = (const char * const *)names;
  530. gpio->gpio.of_node = pdev->dev.of_node;
  531. gpio->gpio.of_gpio_n_cells = 2;
  532. gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
  533. gpio->intc.name = pdev->dev.of_node->name;
  534. gpio->intc.irq_ack = tegra186_irq_ack;
  535. gpio->intc.irq_mask = tegra186_irq_mask;
  536. gpio->intc.irq_unmask = tegra186_irq_unmask;
  537. gpio->intc.irq_set_type = tegra186_irq_set_type;
  538. gpio->intc.irq_set_wake = tegra186_irq_set_wake;
  539. irq = &gpio->gpio.irq;
  540. irq->chip = &gpio->intc;
  541. irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
  542. irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
  543. irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
  544. irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
  545. irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
  546. irq->handler = handle_simple_irq;
  547. irq->default_type = IRQ_TYPE_NONE;
  548. irq->parent_handler = tegra186_gpio_irq;
  549. irq->parent_handler_data = gpio;
  550. irq->num_parents = gpio->num_irq;
  551. irq->parents = gpio->irq;
  552. np = of_find_matching_node(NULL, tegra186_pmc_of_match);
  553. if (np) {
  554. irq->parent_domain = irq_find_host(np);
  555. of_node_put(np);
  556. if (!irq->parent_domain)
  557. return -EPROBE_DEFER;
  558. }
  559. tegra186_gpio_init_route_mapping(gpio);
  560. irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
  561. sizeof(*irq->map), GFP_KERNEL);
  562. if (!irq->map)
  563. return -ENOMEM;
  564. for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
  565. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  566. for (j = 0; j < port->pins; j++)
  567. irq->map[offset + j] = irq->parents[port->bank];
  568. offset += port->pins;
  569. }
  570. platform_set_drvdata(pdev, gpio);
  571. err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
  572. if (err < 0)
  573. return err;
  574. return 0;
  575. }
  576. static int tegra186_gpio_remove(struct platform_device *pdev)
  577. {
  578. return 0;
  579. }
  580. #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
  581. [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
  582. .name = #_name, \
  583. .bank = _bank, \
  584. .port = _port, \
  585. .pins = _pins, \
  586. }
  587. static const struct tegra_gpio_port tegra186_main_ports[] = {
  588. TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
  589. TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
  590. TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
  591. TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
  592. TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
  593. TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
  594. TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
  595. TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
  596. TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
  597. TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
  598. TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
  599. TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
  600. TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
  601. TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
  602. TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
  603. TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
  604. TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
  605. TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
  606. TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
  607. TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
  608. TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
  609. TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
  610. TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
  611. };
  612. static const struct tegra_gpio_soc tegra186_main_soc = {
  613. .num_ports = ARRAY_SIZE(tegra186_main_ports),
  614. .ports = tegra186_main_ports,
  615. .name = "tegra186-gpio",
  616. .instance = 0,
  617. };
  618. #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
  619. [TEGRA186_AON_GPIO_PORT_##_name] = { \
  620. .name = #_name, \
  621. .bank = _bank, \
  622. .port = _port, \
  623. .pins = _pins, \
  624. }
  625. static const struct tegra_gpio_port tegra186_aon_ports[] = {
  626. TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
  627. TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
  628. TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
  629. TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
  630. TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
  631. TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
  632. TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
  633. TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
  634. };
  635. static const struct tegra_gpio_soc tegra186_aon_soc = {
  636. .num_ports = ARRAY_SIZE(tegra186_aon_ports),
  637. .ports = tegra186_aon_ports,
  638. .name = "tegra186-gpio-aon",
  639. .instance = 1,
  640. };
  641. #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
  642. [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
  643. .name = #_name, \
  644. .bank = _bank, \
  645. .port = _port, \
  646. .pins = _pins, \
  647. }
  648. static const struct tegra_gpio_port tegra194_main_ports[] = {
  649. TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
  650. TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
  651. TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
  652. TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
  653. TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
  654. TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
  655. TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
  656. TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
  657. TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
  658. TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
  659. TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
  660. TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
  661. TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
  662. TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
  663. TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
  664. TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
  665. TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
  666. TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
  667. TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
  668. TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
  669. TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
  670. TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
  671. TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
  672. TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
  673. TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
  674. TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
  675. TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
  676. TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
  677. };
  678. static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
  679. { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
  680. { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
  681. };
  682. static const struct tegra_gpio_soc tegra194_main_soc = {
  683. .num_ports = ARRAY_SIZE(tegra194_main_ports),
  684. .ports = tegra194_main_ports,
  685. .name = "tegra194-gpio",
  686. .instance = 0,
  687. .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
  688. .pin_ranges = tegra194_main_pin_ranges,
  689. .pinmux = "nvidia,tegra194-pinmux",
  690. };
  691. #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
  692. [TEGRA194_AON_GPIO_PORT_##_name] = { \
  693. .name = #_name, \
  694. .bank = _bank, \
  695. .port = _port, \
  696. .pins = _pins, \
  697. }
  698. static const struct tegra_gpio_port tegra194_aon_ports[] = {
  699. TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
  700. TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
  701. TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
  702. TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
  703. TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
  704. };
  705. static const struct tegra_gpio_soc tegra194_aon_soc = {
  706. .num_ports = ARRAY_SIZE(tegra194_aon_ports),
  707. .ports = tegra194_aon_ports,
  708. .name = "tegra194-gpio-aon",
  709. .instance = 1,
  710. };
  711. static const struct of_device_id tegra186_gpio_of_match[] = {
  712. {
  713. .compatible = "nvidia,tegra186-gpio",
  714. .data = &tegra186_main_soc
  715. }, {
  716. .compatible = "nvidia,tegra186-gpio-aon",
  717. .data = &tegra186_aon_soc
  718. }, {
  719. .compatible = "nvidia,tegra194-gpio",
  720. .data = &tegra194_main_soc
  721. }, {
  722. .compatible = "nvidia,tegra194-gpio-aon",
  723. .data = &tegra194_aon_soc
  724. }, {
  725. /* sentinel */
  726. }
  727. };
  728. MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
  729. static struct platform_driver tegra186_gpio_driver = {
  730. .driver = {
  731. .name = "tegra186-gpio",
  732. .of_match_table = tegra186_gpio_of_match,
  733. },
  734. .probe = tegra186_gpio_probe,
  735. .remove = tegra186_gpio_remove,
  736. };
  737. module_platform_driver(tegra186_gpio_driver);
  738. MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
  739. MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
  740. MODULE_LICENSE("GPL v2");